DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/03/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang(USPGPUB DOCUMENT: 2018/0061752, hereinafter Huang) in view of Hasegawa (USPGPUB DOCUMENT: 2018/0145023, hereinafter Hasegawa) and Verma (USPGPUB DOCUMENT: 2021/0313116, hereinafter Verma) and Yoshikawa (USPGPUB DOCUMENT: 2023/0138154, hereinafter Yoshikawa).
Re claim 1 Huang discloses in Fig 5 a structure of a metal-insulator-metal (MIM) capacitor and a heat sink(42/48/50), comprising: a dielectric layer(40/22), wherein the dielectric layer(40/22) comprises a capacitor region(region that comprises 36/34/32) and a heat dispensing region(region that comprises 42/48/50); a bottom electrode(36) embedded in the dielectric layer(40/22);a first heat conductive layer(44)(since 44 may conduct heat, this may be interpreted as a first heat conductive layer)[0028] covering the dielectric layer(40/22) and the heat dispensing region(region that comprises 42/48/50); a capacitor dielectric layer(34) disposed on the first heat conductive layer(44) within the capacitor region(region that comprises 36/34/32); a second heat conductive layer(46/38) (since 46/38 may conduct heat, this may be interpreted as a second heat conductive layer)[0028] covering and contacting the capacitor dielectric layer(34) and the first heat conductive layer(44), wherein the second heat conductive layer(46/38) is disposed within the capacitor region(region that comprises 36/34/32) and the heat dispensing region(region that comprises 42/48/50) ;a top electrode(32) disposed within the capacitor region(region that comprises 36/34/32) and the heat dispensing region(region that comprises 42/48/50), and covering the second heat conductive layer(46/38);a first heat sink(48/50) disposed within the heat dispensing region(region that comprises 42/48/50); and a second heat sink(42) disposed within the heat dispensing region(region that comprises 42/48/50) and contacting the first heat conductive layer(44) and the second heat conductive layer(46/38).
Huang does not disclose a first heat sink(48/50) contacting the top electrode(32); wherein the first heat conductive layer is sandwiched between the bottom electrode and the capacitor dielectric layer; wherein the second heat conductive layer is sandwiched between the top electrode and the capacitor dielectric layer; wherein a bottom surface of the capacitor dielectric layer physically contacts the first heat conductive layer, and the second heat conductive layer physically contacts a topmost surface and a sidewall of the capacitor dielectric layer;
Hasegawa discloses in Fig 2A, rotated 180 degrees, a first heat sink(10) contacting the top electrode(34/35);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Hasegawa to the teachings of Huang in order to avoid degrading the capacitor [0002, Hasegawa].
Huang and Hasegawa does not disclose wherein the first heat conductive layer is sandwiched between the bottom electrode and the capacitor dielectric layer; wherein the second heat conductive layer is sandwiched between the top electrode and the capacitor dielectric layer; wherein a bottom surface of the capacitor dielectric layer physically contacts the first heat conductive layer, and the second heat conductive layer physically contacts a topmost surface and a sidewall of the capacitor dielectric layer;
Verma discloses in Fig 7, wherein the first heat conductive layer(18a/b/c/d)[0024] is sandwiched between the bottom electrode(20a) and the capacitor dielectric layer(22b); wherein the second heat conductive layer(18a/b/c/d) is sandwiched between the top electrode(20d) and the capacitor dielectric layer;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Verma to the teachings of Huang in order to increase the capacitance density in the same area [0003, Verma].
Huang and Hasegawa does not disclose wherein a bottom surface of the capacitor dielectric layer physically contacts the first heat conductive layer, and the second heat conductive layer physically contacts a topmost surface and a sidewall of the capacitor dielectric layer;
Yoshikawa disclose wherein a bottom surface of the capacitor dielectric layer(4/5) physically contacts the first heat conductive layer(21), and the second heat conductive layer(R2/M1) physically contacts a topmost surface and a sidewall of the capacitor dielectric layer(4/5);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Yoshikawa to the teachings of Huang in order to ensure a sufficient area for the first via conductor and prevent the occurrence of peeling in the vicinity of the second via conductor [0009, Yoshikawa].
Regarding the limitation a capacitor dielectric layer disposed on the first heat conductive layer". The interpretation of "on" is being interpreted as used to indicate immediate proximity. This interpretation is being based from a general purpose dictionary (see www.Dictionary.com) is the evidence that's being relied upon to show that it's a reasonable interpretation.
Re claim 2 Huang, Hasegawa, Verma and Yoshikawa disclose the structure of an MIM capacitor and a heat sink(42/48/50) of claim 1, wherein the second heat sink(42) penetrates the dielectric layer(40/22) and an end of the second heat sink(42) contacts the first heat conductive layer(44) and the second heat conductive layer(46/38).
Re claim 3 Huang, Hasegawa, Verma and Yoshikawa disclose the structure of an MIM capacitor and a heat sink(42/48/50) of claim 1, wherein the capacitor dielectric layer(34) is only disposed in the capacitor region(region that comprises 36/34/32).
Re claim 4 Huang, Hasegawa, Verma and Yoshikawa disclose the structure of an MIM capacitor and a heat sink(42/48/50) of claim 1, wherein an end of the first heat sink(48/50) contacts the top electrode(32).
Re claim 5 Huang, Hasegawa, Verma and Yoshikawa disclose the structure of an MIM capacitor and a heat sink(42/48/50) of claim 1, further comprising a first plug disposed in the capacitor region(region that comprises 36/34/32) and contacting the top electrode(32), and a second plug disposed in the capacitor region(region that comprises 36/34/32) and contacting the bottom electrode(36).
Re claim 6 Huang, Hasegawa, Verma and Yoshikawa disclose the structure of an MIM capacitor and a heat sink(42/48/50) of claim 1, wherein the dielectric layer(40/22) further comprising: an active region; and a metal interconnection structure[0002 of Hasegawa] disposed within the dielectric layer(40/22) within the active region, wherein the first heat conductive layer(44) and the second heat conductive layer(46/38) extend to the active region, and the second heat conductive layer contacts the metal interconnection structure[0002 of Hasegawa].
Re claim 7 Huang, Hasegawa, Verma and Yoshikawa disclose the structure of an MIM capacitor and a heat sink(42/48/50) of claim 6, further comprising:a substrate disposed under the dielectric layer(40/22); and a power amplifier disposed on the substrate, wherein the power amplifier[0038 of Hasegawa] is electrically connected to the metal interconnection structure[0002 of Hasegawa].
Re claim 8 Huang, Hasegawa, Verma and Yoshikawa disclose the structure of an MIM capacitor and a heat sink(42/48/50) of claim 7, wherein the second heat sink(42) is a through silicon via, and the second heat sink(42) penetrates the substrate.
Re claim 9 Huang, Hasegawa, Verma and Yoshikawa disclose the structure of an MIM capacitor and a heat sink(42/48/50) of claim 1, wherein the first heat conductive layer(44) comprises amorphous aluminum nitride, and the second heat conductive layer(46/38) comprises amorphous aluminum nitride[0025 of Hasegawa].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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