DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 8, 11 – 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication No. 2024/0213325 to Vega et al.
Regarding claim 1, Vega et al. teach a semiconductor structure, comprising:
a first active region comprising a plurality of first active channel layers (107a, 107b, 107c) vertically stacked;
a second active region disposed adjacent to the first active region and comprising a plurality of second active channel layers (107a, 107b, 107c) vertically stacked, wherein there is a space between the first active region and the second active region (Fig. 12);
a metal gate (130, 130’, ¶ [0055]) formed on the first active region and the second active region; and
a dielectric wall (223) formed within the space between the first active region and the second active region;
wherein the dielectric wall has a first wall width and a second wall width different from the first wall width. See Fig. 12.
Regarding claims 2 and 14, Vega et al. teach a semiconductor structure, wherein the dielectric wall extends in a first direction, the first active region comprises one of a source epitaxy and a drain epitaxy (¶ [0034]), the second active region comprises another of the source epitaxy and the drain epitaxy, and the metal gate extends in a second direction perpendicular to the first direction; wherein the source epitaxy, the drain epitaxy and the metal gate form a transistor (¶ [0052]).
Regarding claims 3 and 15, Vega et al. teach a semiconductor structure, wherein the dielectric wall extends in a first direction, the first active region comprises a first epitaxy and a second epitaxy, the first epitaxy is corresponding to the first wall width in a second direction perpendicular to the first direction, and the second epitaxy is corresponding to the second wall width in the second direction. See Fig. 12.
Regarding claims 4 and 16, Vega et al. teach a semiconductor structure, wherein the second active region comprises a third epitaxy and a fourth epitaxy, the third epitaxy is corresponding to the first wall width in the second direction, and the fourth epitaxy is corresponding to the second wall width in the second direction. See Fig. 12.
Regarding claims 5 and 17, Vega et al. teach a semiconductor structure, wherein the space comprises a first sub-space and a second sub-space, the first sub-space has a first space width, the second sub-space has a second space width different from the first space width. See Fig. 12.
Regarding claim 6, Vega et al. teach a semiconductor structure, wherein the first sub-space and the second sub-space are located at opposite two sides of a metal gate. See Fig. 12, where the first sub-space is opposite the metal gate.
Regarding claim 7, Vega et al. teach a semiconductor structure, wherein the dielectric wall comprises a first wall portion having the first wall width and a second wall portion having the second wall width, the first wall portion has a first lateral surface and a third lateral surface opposite to the first lateral surface, the second wall portion has a second lateral surface and a fourth lateral surface opposite to the second lateral surface, the fourth lateral surface protrudes relative to the third lateral surface, and the first lateral surface and the second lateral surface are flushed with each other. See Fig. 12.
Regarding claim 8, Vega et al. teach a semiconductor structure, wherein the dielectric wall comprises a first wall portion having the first wall width and a second wall portion having the second wall width, the first wall portion has a first lateral surface and a third lateral surface opposite to the first lateral surface, the second wall portion has a second lateral surface and a fourth lateral surface opposite to the second lateral surface, the second lateral surface protrudes relative to the first lateral surface, and the fourth lateral surface protrudes relative to the third lateral surface. See Fig. 12.
Regarding claim 11, Vega et al. teach a semiconductor structure, comprising:
a first active region comprising a plurality of first active channel layers vertically stacked (107a, 107b, 107c);
a second active region disposed adjacent to the first active region and comprising a plurality of second active channel layers vertically stacked (107a, 107b, 107c), wherein there is a space between the first active region and the second active region (Fig. 12); and
a dielectric wall (223) formed within the space between the first active region and the second active region, and comprising a first wall portion and a second wall portion, wherein the first wall portion has a first lateral surface, the second wall portion protrudes with respect to the first lateral surface of the first wall portion.
Regarding claim 12, Vega et al. teach a semiconductor structure, wherein the second wall portion has a second lateral surface protruding beyond the first lateral surfaces of the first wall portion, and the first wall portion further has a third lateral surface opposite to the first lateral surface, the second wall portion protrudes with respect to the third lateral surface of the first wall portion. See Fig. 12.
Regarding claim 13, Vega et al. teach a semiconductor structure, wherein the second wall portion has a second lateral surface, and the first lateral surface and the second lateral surface are flushed with each other. See Fig. 12.
Regarding claim 19, Vega et al. teach a manufacturing method of a semiconductor structure, comprising:
forming a first fin structure and a second fin structure adjacent to the first fin structure, wherein the first fin structure comprising a plurality of first sheets (107a-107c ¶ [0049]) and a plurality of first spacers (105a-105d), the second fin structure comprising a plurality of second sheets (107a-107c) and a plurality of second spacer (105a-105d)), the first sheets and the first spacers are stacked to each other, the second sheets and the second spacers are stacked to each other, and there is a space between the first fin structure and the second fin structure (Fig. 12); and
forming a dielectric wall (223) within the space between the first fin structure and the second fin structure, wherein the dielectric wall has a first wall width and a second wall width different from the first wall width.
Allowable Subject Matter
Claims 9, 10, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2024/0145540 to Ju et al. teach a semiconductor structure with a pair of vertically stacked active regions and a space with a dielectric wall therebetween Ju et al. do not teach that the dielectric wall has a first width, and a second width different from the first width.
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DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897