Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The current office action replaces the previous office action, mailed on 10/07/2026.
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the specification for the claimed limitation of “wherein a height of the conductive plug is equal to a thickness of the insulating layer”, as recited in claim 13.
There is no support in the specification for the claimed limitation of “a height of the second word line is equal to a height of the first word line”, as recited in claim 17.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (2013/0151277) in view of Taketani (2012/0211813).Regarding claim 9, Wu et al. teach in figure 3E and related text a memory device, comprising:
a semiconductor substrate 200 defined with an active area 214 and including a plurality of fins protruding from the semiconductor substrate and disposed within the active area 214,
wherein each of the plurality of fins has a first planar top surface to form a plurality of first recesses alternating with the plurality of fins, wherein each of the plurality of fins has a first planar top surface formed at a top surface of the semiconductor substrate, wherein a top portion of each of the fins is the active area;
a first word line 216 extending into the semiconductor substrate and between an adjacent two of the plurality of fins 204, wherein the first word line is disposed within one of the first recesses,
wherein the first word line 216 includes an oxide layer 208 conformal to surfaces of the adjacent two of the plurality of fins, a first conductive member 210 surrounded by the oxide layer 208, and a first nitride layer 216 disposed over the first conductive member and surrounded by the oxide layer; and
an isolation 206 extending into the semiconductor substrate and surrounding the active area 214, wherein a second recess extends into the isolation 206, and
a second word line (another 216) disposed within the second recess at the isolation, wherein the second word line comprises a second conductive member (another 210) in direct contact with a bottom surface and side surfaces of the second recess (since dielectric 208 is not part of the second recess), and a second nitride layer (another 216) disposed over the second conductive member;
wherein a top surface of the first conductive member 210 within the first recess is coplanar with a top surface of the second conductive member (another 210) within the second recess;
wherein a height of the first nitride layer 216 within the first recess is equal to a height of the second nitride layer (another 216) within the second recess;
wherein the first nitride layer has a second planar top surface substantially coplanar with the first planar top surface of each of the plurality of fins.
Wu et al. do not teach that a height of the second recess is equal to a height of each of the first recesses and do not explicitly using plurality of gates (i.e. an additional “another 210 element).
Taketani teaches in figure 8 and related text that a height of the second recess of isolation trench 32B is equal to a height of each of the first recesses of the gate trenches 31A and in figure 1B using plurality of gates 31.
Wu et al. and Taketani are analogous art because they are directed to fins and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a height of the second recess is equal to a height of each of the first recesses and to use plurality of gates, as taught by Taketani, in Wu et al.’s device, in order to simplify the processing steps of making the device and in order to use the device in practical device, respectively.
Regarding claim 10, Wu et al. teach in figure 3E and related text that the oxide layer has a third planar top surface substantially coplanar with the first planar top surface of each of the plurality of fins and the second planar top surface of the first nitride layer.
Regarding claim 11, Wu et al. teach in figure 3E and related text that the third planar top surface of the oxide layer is coupled with the first planar top surface of one of the plurality of fins and the second planar top surface of the first nitride layer.
Regarding claim 12, Wu et al. do not teach an insulating layer disposed over the semiconductor substrate and the isolation, and a conductive plug extending through the insulating layer and contacting the first planar top surface of one of the plurality of fins,
Taketani teaches in figure 1B, and related text an insulating layer 43 disposed over the semiconductor substrate and the isolation, and a conductive plug 52 extending through the insulating layer 43 and contacting (at least electrically contacting) the first planar top surface of one of the plurality of fins.
Wu et al. and Taketani are analogous art because they are directed to fins and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form an insulating layer disposed over the semiconductor substrate and the isolation, and a conductive plug extending through the insulating layer and contacting the first planar top surface of one of the plurality of fins,
Wherein, in the combined device, a bottom surface of the insulating layer is in contact with the top surface of the semiconductor substrate, a fourth planar top surface of the isolation, the second planar top surface of the first nitride layer of the first word line, and a top surface of the second nitride layer of the second word line, as taught by Taketani, in Wu et al.’s device, in order to provide better protection to the device.
Regarding claim 13, in the combined device, a planar interface is disposed between the conductive plug and the first planar top surface of one of the plurality of fins, such that the conductive plug is not in contact with the first word lines.
The combined device does not teach that a height of the conductive plug is equal to a thickness of the insulating layer.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a height of the conductive plug is equal to a thickness of the insulating layer in prior art’s device in order to provide better protection to the conductive plug.
Regarding claim 14, in the combined device, the isolation has the fourth planar top surface substantially coplanar with the first planar top surface of each of the plurality of fins.
Regarding claim 15, since the combined device comprises pluralities of word lines and since the isolation surrounds the word lines, then the second word line is surrounded by and in direct contact with the isolation.
Regarding claim 16, in the combined device, the second word line is separated from the first word line by the plurality of fins.
Claim 17, Wu et al. teach in figure 3B and related text that a height of the second word line is equal to a height of the first word line, wherein a height of the second conductive member is equal to a height of the first conductive member, wherein the first conductive member and the second conductive member are made of a same material, wherein the first nitride and the second nitride layer are made of a same material.
Wu et al. do not teach in figure 3B and related text that a height of the second word line is greater than a height of the first word line. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a height of the second word line is greater than a height of the first word line in prior art’s device in order to improve the conductivity of the second word line.
Response to Arguments
1. Applicants argue that “Wu fails to teach that "a top portion of each of the fins is the active area", as disclosed and supported at least in paragraph [0028] and FIGS. 3 and 11 of the present application”, because “Wu merely discloses that, in paragraph [0020], "in the vertical transistor, each doping region 214 of the predetermined conductivity type has a polarity which is different from that of the charges (not shown) trapped in the charge-trapping dielectric layer 204'. Particularly, the top portion of the charge-trapping dielectric layer 204 as taught by WU is NOT the doping region 214, as clearly shown in FIGS. 2E and 3E of Wu”.
1. Claim 9 recites “a top portion of each of the fins is the active area”. Wu teaches in figure 3E and related text that a top portion of each of the fins is the active area 214. Even applicants agree by stating “doping region 214”.
2. Applicants argue that “Wu fails to teach that "a top surface of the first conductive member is coplanar with a top surface of the second conductive member".
2. Wu teaches in figure 3E and related text that a top surface of the first conductive member 210 is coplanar with a top surface of the second conductive member (another 210), wherein Taketani teaches in figure 1B and related text using plurality of gates 31.
3. Applicants argue that “as shown in the below FIG. 3E of Wu, another 216
and another 210 as pointed out by the Examiner are NOT disposed in the liner insulating layer 206 which is alleged as the isolation of the present application”.
3. It is noted that the phrase “the liner insulating layer” is not recited in claim 9.
4. Applicants argue that “Wu fails to teach that "a bottom surface of the insulating layer is in contact with the top surface of the semiconductor substrate, a fourth planar top surface of the isolation, the second planar top surface of the first nitride layer of the first word line, and a top surface of the second nitride layer of the second word line".
4. Applicants do not articulate as to which element(s) Wu does not teach.
5. Applicants argue that “Wu fails to teach that "a height of the conductive plug is equal to a thickness of the insulating layer".
Applicants state that paragraph [0065] and related figures provide support for the above limitation.
5. There is no support for the claimed limitation of “a height of the conductive plug is equal to a thickness of the insulating layer”, because annotated figure 22 improperly equate “thickness” and “height” as having the same coordinates.
6. Applicants argue that “Wu fails to teach that "a height of the second
conductive member 106a is greater than a height of the first conductive member 105b", as disclosed and supported at least in FIGS. 3, 18, and 20 of the present application”.
6. The specification does not provide support for the claimed limitation of "a height of the second conductive member is greater than a height of the first conductive member”, because the height of the second conductive member and the height of the first conductive member both reach the same elevation point and have the same y coordinates as depicted in figure 22 of the present application.
7. Applicants argue that “The first dielectric layer 202 and the gate electrode 210 as taught by Wu are made of different materials while the charge-trapping dielectric layer 204 and the second dielectric layer 216 as taught by Wu are also made of different materials”.
7. It is correct that the first dielectric layer 202 and the gate electrode 210 as taught by Wu are made of different materials (since one is dielectric and one is conductive) while the charge-trapping dielectric layer 204 and the second dielectric layer 216 as taught by Wu are also made of different materials (since one is dielectric and one is conductive).
8. Applicants argue that “the gate trench 31A and the second isolation trench 32B as taught by Taketani are different from the first recess and the second recess of the present application”.
8. The combined device of Wu in view of Taketani teaches the claimed first recess second recess.
9. Applicants argue that “Neither the second interlayer insulating film 42 nor the third interlayer insulating film 43 as taught by Taketani is in contact with the top surface of the semiconductor substrate 1 or any top surface of the isolation”.
9. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
10/14/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights