DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 2, 4, 9-14, 16, 21-25 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ochii et al. (US 5281843; herein “Ochii”) in view of Kang et al. (US 20090008638; herein “Kang”) and Li et al. (US 20080023698; herein “Li”).
Regarding claim 2, Ochii discloses in Fig. 1-3 and related text a semiconductor device comprising:
a first transistor (Q6, see col. 3 line 65) and a second transistor (Q3, see col. 3 line 63),
wherein one of a source and a drain of the first transistor is electrically connected to a gate electrode of the second transistor (see Fig. 1),
wherein the first transistor comprises a first channel formation region (in P-sub 11),
wherein a potential is supplied to the gate electrode of the second transistor by turning on the first transistor.
Ochii does not disclose
the first channel formation region in an oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a crystal,
wherein a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer.
In the same field of endeavor, Kang teaches a second transistor (TFT transistor) wherein the first channel formation region in an oxide semiconductor layer (see [0045] at least).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Ochii by having the thin film transistor channel formation region in an oxide semiconductor, as taught by Kang, in order achieve a TFT having improved electrical characteristics such as good channel mobility and on/off ratio (see [0007] at least).
In the same field of endeavor, Li teaches a transistor with an oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a crystal,
wherein a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer (see [0035] at least).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ochii and Kang by having the oxide semiconductor layer comprises a crystal and a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer, as taught by Li, in order to improve channel mobility (see Li [0035] at least).
Note that is it is the Office' s position that the limitation of “a potential is supplied to the gate electrode of the second transistor by turning on the first transistor” is a functional limitation of the apparatus claimed. While features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. See MPEP 2114.I and 2112.01. Additionally, because the combined device has all of the structural limitations of the claimed invention the device is capable of operating in the manner claimed by the applicant. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. See MPEP 2114.II and 2112.01.
Regarding claim 14, Ochii discloses in Fig. 1-3 and related text a semiconductor device comprising:
a first transistor (Q6, see col. 3 line 65) and a second transistor (Q3, see col. 3 line 63),
wherein one of a source and a drain of the first transistor is electrically connected to a gate electrode of the second transistor (see Fig. 1),
wherein the semiconductor device comprises a floating gate portion where the one of the source and the drain of the first transistor is electrically connected to the gate electrode of the second transistor,
wherein the first transistor comprises a first channel formation region (in P-sub 11),
wherein a potential is supplied to the gate electrode of the second transistor by turning on the first transistor.
Kang and Li teach the remaining claimed limitations in substantially the same manner and for the same reasons as applied to claim 2 above.
Note that is it is the Office' s position that the limitation of “the semiconductor device comprises a floating gate portion where the one of the source and the drain of the first transistor is electrically connected to the gate electrode of the second transistor” is a functional limitation of the apparatus claimed. While features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. See MPEP 2114.I and 2112.01. Additionally, because the combined device has all of the structural limitations of the claimed invention the device is capable of operating in the manner claimed by the applicant. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. See MPEP 2114.II and 2112.01. In particular, it is noted that applicant’s disclosure ascribes the “floating gate portion” as being an effect which occurs due to the source electrode or the drain electrode of the oxide semiconductor transistor being electrically connected to the gate electrode of the silicon transistor (see [0224] of published version of applicant’s disclosure). As the combined device shows this connection, it is the position of the Office that the claimed limitation is taught.
Regarding claims 4 and 16, Ochii further discloses a capacitor electrically connected to the gate electrode of the second transistor (e.g. the capacitor formed by gate 14 of Q3 and overlapped region of 15(G1), see Fig. 2-3).
Regarding claims 9 and 21, the combined device shows the oxide semiconductor layer comprises an In-Ga-Zn-O-based oxide semiconductor layer, an In-Sn-Zn-O-based oxide semiconductor layer, an In-Al-Zn-O-based oxide semiconductor layer, a Sn-Ga-Zn-O-based oxide semiconductor layer, an Al-Ga-Zn-O- based oxide semiconductor layer, a Sn-Al-Zn-O-based oxide semiconductor layer, an In-Zn-O- based oxide semiconductor layer, a Sn-Zn-O-based oxide semiconductor layer, an Al-Zn-O- based oxide semiconductor layer, an In-O-based oxide semiconductor layer, a Sn-O-based oxide semiconductor layer, or a Zn-O-based oxide semiconductor layer (Kang: see [0045]).
Regarding claims 10 and 22, Ochii further discloses wherein the second transistor comprises a channel formation region in a silicon region (see col. 4 lines 19-27; see also col. 1 line 11-13, col. 2 lines 16-17).
Regarding claims 11 and 23, the combined device shows a memory cell (Ochii: see col. 1 lines 7-9) comprising the semiconductor device according to claims 2 and 14, respectively.
Regarding claims 12 and 24, the combined device does not explicitly disclose a memory cell array comprising the memory cell according to claims 11 and 23, respectively.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to have an array of memory cells in order to achieve improved storage capacity over having a single cell, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It has also been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04
Regarding claims 13 and 25, the combined device shows a non-volatile memory comprising the memory cell according to claims 11 and 23, respectively.
Note that is it is the Office' s position that the limitation of “a non-volatile memory” is a functional limitation of the apparatus claimed. While features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. See MPEP 2114.I and 2112.01. Additionally, because the combined device has all of the structural limitations of the claimed invention the device is capable of operating in the manner claimed by the applicant. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. See MPEP 2114.II and 2112.01. In particular, it is noted that applicant’s disclosure ascribes the “substantially non-volatile” device as being an effect which occurs due to oxide semiconductor layer of the first transistor having a low off current as a result of the features as claimed. As the combined device shows the oxide layer having the structure as claimed, it is the position of the Office that the claimed limitation is taught.
Claims 5 and 17 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ochii in view of Kang and Li, as applied to claims 2 and 14 above, and further in view of Yamazaki et al. (US 20100102312; herein “Yamazaki”).
Regarding claims 5 and 17, Ochii as modified does not explicitly disclose a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x1019 atoms/cm3 or less.
In the same field of endeavor, Yamazaki teaches in Fig. 1B, 10and related text a transistor with an oxide semiconductor layer, wherein a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x1019 atoms/cm3 or less (see, e.g., [0148]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ochii as modified by having a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x1019 atoms/cm3 or less, as shown by Yamazaki, in order to improve mobility of the thin film transistor and to obtain a sufficient on-off ratio with off current suppressed (see Yamazaki [0010] at least).
Claims 5 and 17 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ochii in view of Kang and Li, as applied to claims 2 and 14 above, and further in view of Iwasaki et al. (US 20090065771; herein “Iwasaki”).
Regarding claims 5 and 17, Ochii as modified does not explicitly disclose a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x1019 atoms/cm3 or less.
In the same field of endeavor, Iwasaki teaches in Fig. 1A, 13 and related text a transistor with an oxide semiconductor layer, wherein a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x1019 atoms/cm3 or less (see, e.g. [0123]-[0124], [0137]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ochii as modified by having a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x1019 atoms/cm3 or less, as shown by Iwasaki, in order to improve mobility of the thin film transistor (see Iwasaki [0011] at least).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 4, 9-14, 16, and 21-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-32 of U.S. Patent No. claims 1-32 of U.S. Patent No. 10490553 (herein “‘553”) in view of Kang and Li. In the instant case, ‘553 recites all of the claimed limitations except for the crystal features of the oxide semiconductor. Kang and Li teach the limitations for the same reasons as applied to claims 2 and 4 above.
Claims 2, 4, 9-14, 16, and 21-25 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2 and 11-14 of copending Application No. 18538009 (reference application; herein “’009”) in view of in view of Kang and Li. In the instant case, ‘009 recites all of the claimed limitations except for the crystal features of the oxide semiconductor. Kang and Li teach the limitations for the same reasons as applied to claims 2 and 4 above.
This is a provisional nonstatutory double patenting rejection.
Claims 2, 4, 9-14, 16, and 21-25 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2 and 6-11 of copending Application No. 18537929 (reference application; herein “’929”) in view of in view of Kang and Li. In the instant case, ‘929 recites all of the claimed limitations except for the crystal features of the oxide semiconductor. Kang and Li teach the limitations for the same reasons as applied to claims 2 and 4 above.
This is a provisional nonstatutory double patenting rejection.
Response to Arguments
Applicant's arguments filed 8/12/2026 have been fully considered but are moot in view of the new grounds of rejection presented above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAUREN R BELL/Primary Examiner, Art Unit 2896
Prosecution Insights