DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Election/Restrictions
Applicant’s election of Species I (drawn to Fig. 15A and 22A-B) in the reply filed on 3/24/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The combined Information Disclosure Statements (IDS) filed in the application contain nearly 600 references. The examiner has considered the references to the extent reasonably expected during normal examination time.
If applicant considers there is a particular reference or teaching particularly relevant to the claimed invention it is requested from the applicant to provide a statement indicating such relevance and a clear identification of such reference. Further, it is noted that it is desirable to avoid the submission of long lists of documents when possible. Clearly irrelevant and marginally pertinent cumulative information should be eliminated. If a long list is submitted, those documents which have been specifically brought to applicant's attention and/or are known to be of most significance should be highlighted by Applicant. See Penn Yan Boats, Inc. v. Sea Lark Boats, Inc., 359 F. Supp. 948, 175 USPQ 260 (S.D. Fla. 1972), aff 'd, 479 F.2d 1338, 178 USPQ 577 (5th Cir. 1973), cert. denied, 414 U.S. 874 (1974). But cf. Molins PLC v. Textron Inc., 48 F.3d 1172, 33 USPQ2d 1823 (Fed. Cir. 1995).
Drawings
The drawings are objected to because the axis of Fig. 29 appears to be mislabeled as “zA/mm.” Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 25 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for some values of off-state current less than 1x10-13A, does not reasonably provide enablement for the entire range of values less than 1x10-13A. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention commensurate in scope with these claims.
In determining that the claims do not satisfy the enablement requirement, the examiner has considered each of the factors specified in In re Wands. (858 F.2d 731, 737 (Fed. Cir. 1988).)
(A) The breadth of the claims;
(B) The nature of the invention;
(C) The state of the prior art;
(D) The level of one of ordinary skill;
(E) The level of predictability in the art;
(F) The amount of direction provided by the inventor;
(G) The existence of working examples; and
(H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure.
Regarding claim 25, the full scope of “an off-state current of the first transistor is 1x10-13A or less,” is not enabled.
The specification, while being enabling for some range of off-state current within the claimed range, does not reasonably provide enablement for any off-state current within the claimed range. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
Note that, as a matter of claim interpretation, note that “off-state current,” as best understood, is intended to be the same characteristic as the disclosed “off current” and the two terms will herein be used synonymously.
A: The breadth of the claims, and B: The nature of the invention
A transistor functions as a switch. The gate electrode of the transistor controls current flow in the channel of the transistor between the source and the drain of the transistor. When the gate electrode is in an on-state current freely flows between the source and drain. In a theoretically ideal transistor, when the gate electrode is an off-state zero current would flow between the source and the drain. In a real-world transistor, however, some small quantity of current flows between the source and drain even when the gate electrode is in the off state. This “leakage” of current is referred to as the “off current.” The nature of this invention includes a transistor having a very low off current, achieved by employing a purified oxide semiconductor layer as the channel of the transistor.
The claimed invention includes the transistor with a claimed “off-state current of 1x10-13A or less.” The range recited in the claims includes no lower endpoint. Accordingly, the scope of the claim includes values of off current which are physically impossible. In particular, the scope of the claims includes an off-current of, for example, 0 A. This complete absence of leakage would be understood to be possible only in a theoretically perfect transistor with materials having no imperfections and/or at conditions which are only theoretically achievable, such as a temperature of 0K. Additionally, the scope of the claims includes negative values of off current, indicative of a current which would be spontaneously flowing in the opposite direction even though the transistor is in the off state. Such a spontaneous current is understood to be impossible.
Lastly, the scope of the claim includes off-current values for which, even if not entirely impossible, the specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. For example, the scope of the claim includes values such as 1x10-25A, 1x10-50A, or 1x10-100A, which are many orders of magnitude smaller than the working examples disclosed by applicants and the state of the prior art.
C: The state of the prior art
As applicant concedes in the disclosure, an off-state current of 1x10-13A is “extremely low.”
Also, as shown in the following table of prior art references, the lowest off current values in the prior art are on the order of 10-14.
Prior art reference
Lowest off current
Hayashi et al. (Improved Amorphous In-Ga-Zn-O TFTs, 2008)
10-14 A (see pg. 621, col. 2, para. 2)
Braddock (US 6989556)
10-14 A (see col. 2 line 58-64)
Comeau (US 6842318)
10-14 A (see col. 1 para. 1)
Yamazaki et al. (US 6997985)
10-12 (see col. 31 para. 1)
Ohtani et al. (US 20090075460)
10-12 (see [0184])
Dairiki et al. (US 20090218568)
10-10 (see [0281])
Li et al. (US 20080003697)
10-10 (see [0031])
Song et al. (US 20080093595)
10-12 (see [0031])
Imai et al. (US 20090127550)
10-13 (see Table 2)
Kim et al. (US 20090184319)
10-13 (see [0098])
Itagaki et al. (US 20090269880)
10-12 (see [0097])
Therefore an off-state current with no lower limit would include values which are less than the off current values of the prior art by unlimited orders of magnitude.
F: The amount of direction provided by the inventor, and G: The existence of working examples
First working example which provides some direction:
Paragraph [0317] includes a transistor having an off current of “smaller than or equal to 1x10-13 A.” The working example specifies a channel width of 1 m, a drain voltage of +1 V or +10 V, and a gate voltage within the range of -5 V to -20 V.
It is first noted that, although the off current is disclosed as being dependent on other parameters such as temperature (see e.g. [0059]), source-drain voltage (see e.g. [0343]), and/or capacitance of the associated capacitor (see [0340]), none of these parameters are specified for this working example and therefore no direction is provided as to the parameters under which this off current is measured.
The working example further specifies that the off current per channel width is “smaller than or equal to 1x10-18 A/µm.” It is noted, however, that the off current per channel width of 1x10-18 A/µm appears to be inconsistent with and contradictory to the off current of 1x10-13 A or less. Rather, the working example provided having the 1 m channel and a off current smaller than or equal to 1x10-13 A, the resulting off current per channel width would be 1x10-19 A/µm.
Further, the examiner contends that a transistor of 1 m channel width is impracticable large. One of ordinary skill in the art would not understand how to make a transistor of this size. In particular, because the inventive channel has to be highly purified to achieve the low off current, it would seem that no instruments and/or processing chambers would exist in order to purify a channel which is 1 m wide, especially to the degree required to achieve the desired low off current.
Lastly, it is noted that the value of 1x10-13 A represents a detection limit, thus a lower limit of off current was not and cannot be measured in this working example.
Accordingly, while the disclosure does provide this working example, the extent to which it provides direction is limited by the lack of specified parameters on which the off current depends, the conflicting nature of the resulting values presented, and the impracticability of the disclosed size of the device. Further, the working example does not provide any specific value of off current lower than
1x10-13A and provides no direction whatsoever as to how one would achieve a device having an off current with specific values consistent with the entire scope of the claimed range.
Second working example which provides some direction:
Paragraphs [0319]-[0344] further present working examples of transistors in the circuit shown in Fig. 26. The working example is a transistor with channel length of 10 µm and channel width of 50 µm. The working example is shown to have varied off current per channel width dependent on a source-drain voltage and the capacitance of the associated capacitor (see Figs. 29 and 30). At 25˚C, the disclosure recites the off current per channel width is “smaller than or equal to 10 zA/µm” (1x10-20A/µm) (see [0343]), however the lowest off current shown per channel width is around 2 zA/µm” (2x10-21A/µm) (see Fig. 29). At 85˚C, the disclosure does not recite a range of off current per channel width, however the lowest off current per channel width shown for the working example is around 11 zA/µm” (1.1x10-20A/µm).
Therefore, for the example transistor having channel width of 50 µm, the lowest off current of the working example is approximately 5x10-19A at 25˚C and approximately 5.5x10-19 A at 85˚C.
Accordingly, while the disclosure does provide this working example, it does not provide any specific value of off current lower than approximately 5x10-19A and provides no direction whatsoever as to how one would achieve a device having an off current with specific values consistent with the entire scope of the claimed range.
Additional direction provided by the inventor:
Applicant attributes the low off current of the invention to the highly purified nature of the oxide semiconductor layer which forms the channel of the transistor:
[0059] Here, the oxide semiconductor layer 140 is preferably a highly purified oxide semiconductor layer from which impurities such as hydrogen are sufficiently removed. Specifically, the concentration of hydrogen in the oxide semiconductor layer 140 is 5x1019 atoms/cm3 or less, preferably 5x1018 atoms/cm3 or less, more preferably 5x1017 atoms/cm3 or less. Such an extremely low hydrogen concentration leads to a sufficiently low carrier concentration (e.g., less than 1x1012/cm3, or less than 1.45x1010/cm3) as compared to a general silicon wafer (a silicon wafer to which an impurity such as a slight amount of phosphorus or boron is added) having a carrier concentration of approximately 1x1014/cm3. The transistor 162 with significantly excellent off current characteristics can be obtained with the use of such an oxide semiconductor that is highly purified by a sufficient reduction in hydrogen concentration and becomes intrinsic (i-type) or substantially intrinsic (i-type). For example, the off current (per unit channel width (1 m), here) of the transistor 162 at room temperature (25 °C) is 10 zA/µm (1 zA (zeptoampere) is 1x10-21 A) or less, preferably 1 zA/µm or less. The off current of the transistor 162 at 85 °C is 100 zA/µm (1x10-19A/µm) or less, preferably 10 zA/µm (1x10-20A/µm) or less. The oxide semiconductor layer 140 which is made to be intrinsic or substantially intrinsic by a sufficient reduction in hydrogen concentration is used so that the off current of the transistor 162 is reduced, whereby a semiconductor device with a novel structure can be realized. Note that the concentration of hydrogen in the oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS).
Although the disclosure does provide direction as to reducing the hydrogen concentration to achieve some values of off current in the claimed range, Applicant has not provided any direction as to how one would achieve hydrogen concentration substantially lower than 5x1019 atoms/cm3 or if further reduction in hydrogen concentration alone might result in a device having an off current with specific values consistent with the entire scope of the claimed range.
H: The quantity of experimentation needed to make or use the invention based on the content of the disclosure
The instant disclosure sets forth some details related to achieving a device having some values of off current consistent with a portion of the claimed range, i.e. down to approximately ~10-19A. In no instance, however, does the disclosure provide direction of how to achieve an off current which is orders of magnitude lower, an off current of 0A, or a negative off current. Accordingly, the quantity of experimentation required to make an invention with the entire range of off current claimed is significant and undue.
Additionally, since the disclosure recites that off current can be dependent on or effected by such myriad parameters as temperature (see e.g. [0059]), channel width (see e.g. [0059]), channel length (see e.g. [0340]), drain voltage (see e.g. [0317]), gate voltage (see e.g. [0317]), source-drain voltage (see e.g. [0343]), capacitance of the associated capacitor (see [0340]), and/or impurity concentration (see [0149]), and the possible ranges of each are extremely broad and further unspecified by applicant in most instances, the quantity of experimentation required to make an invention with the range of off current claimed is significant and undue.
Lastly, given the conflicting, incomplete, and impractical details presented in the first working example above, the quantity of experimentation required to make an invention with the range of off current claimed is significant and undue.
Enablement conclusion:
The examiner has considered the factors above and found that the scope of “1x10-13A or less” far exceeds what is known in the art, and the quantity of experimentation necessary to reproduce the entire range of off-state currents claimed is undue. The limitation in question would cover off-state currents theoretically impossible, yet to be discovered, and not discoverable by routine experimentation.
Accordingly, claim 25 is rejected for lack of enablement.
Claim 25 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 25, the limitation “an off-state current of the first transistor is 1x10-13A or less,” is an unbounded and open-ended recitation which is insufficiently supported by applicant’s original disclosure. Specifically, it has been held that the scope of the claims must bear a reasonable correlation to the scope of enablement provided by the specification and that when applicant has not enabled values significantly different than the bounded end of a claimed range, the claims are insufficiently supported. (see In re Fisher, 427 F.2d 833 (CCPA 1970)).
Note the dependent claims do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 24, 25 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 24, the limitation “wherein the first channel formation region is formed in a semiconductor layer,” is unclear as to how it is related to the silicon of claim 20.
Regarding claim 25, the limitation “off-state current” is unclear as to what an “off-state current” is. It is specifically noted that applicant’s specification discusses “off current” at great length and it is unclear as to if “off-state current” is intended to be the same characteristic or a different characteristic. For examination purposes it will be interpreted as the same as “off current.”
Regarding claim 25, the limitation “off-state current of the first transistor is 1x10-13A or less,” is so broad as to be indefinite. Specifically, applicant’s disclosure appears to indicate that off current can be dependent on temperature (see e.g. [0059]), channel width (see e.g. [0059]), channel length (see e.g. [0340]) drain voltage (see e.g. [0317]), gate voltage (see e.g. [0317]), source-drain voltage (see e.g. [0343]), capacitance of the associated capacitor (see [0340]), and/or impurity concentration (see [0149]). As none of these are specified in the claim, the breadth of claim would include nearly any transistor at a given value of temperature, channel width, etc. For example, nearly any transistor at a low enough voltage and/or temperature would read on the claim. Accordingly, the boundaries of the protected subject matter are not clearly delineated and the scope is unclear.
Additionally the limitation is unclear as to if it is a property of the transistor itself or an operational characteristic. Specifically, applicant’s disclosure does not provide clarity as to if the off current is merely a function of how the device is operated (e.g. how the device is biased), or if the transistor can be said to have a given off current which is a defined value. It would be as if a transistor was claimed with a range of currents through the channel as compared to a resistance of the channel. The currents would be entirely a function of how the transistor is being biased during operation, whereas the resistance of the channel would be a property of the transistor itself. The proper interpretation of the limitation cannot be ascertained because, as the claim is a device claim, a property of the device would be given substantially different weight than a functional or operational limitation.
Further, it is unclear as to what properties of a transistor would be understood to achieve the structure having the off current as claimed. Specifically, applicant’s disclosure appears to attribute the low off current to the purity of the channel region. Applicant has been his or her own lexicographer to the term “i-type” as “elimination of impurities such as hydrogen and water and oxygen vacancy as much as possible” (see [0149] of Applicant’s disclosure). However, applicant’s definition is undefined because the phrase "such as" renders the claim indefinite because it is unclear whether the phrase is required of the claimed invention. See MPEP § 2173.05(d). In particular, it is unclear if hydrogen, water, and oxygen vacancies are merely examples of which impurities need to be removed in order to achieve “i-type.” For example, it is unclear if removal of a different impurity, e.g. nitrogen, would result in an “i-type” material. Therefore, which impurities must be removed cannot be defined and therefore which materials would or would not read on “i-type” cannot be defined. Additionally, “as much as possible” is indefinite. In particular, it is clear that “as much as possible” would be largely dependent on different methods of removal, different instrumentation and apparatus available, the current technology at the time of removal, etc. Therefore, the amount of impurities required to be removed to meet “as much as possible” cannot be defined and therefore which materials would or would not read on “i-type” cannot be defined. Lastly, the term “substantially” is a relative term which renders the claim indefinite. The term is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In particular it is noted that “substantially i-type” would require elimination of impurities such as hydrogen and water and oxygen vacancy substantially as much as possible. Even if “as much as possible” could be defined—which the examiner contends it cannot be—it is noted that an amount of impurities removed simply cannot be simultaneously “as much as possible” and “substantially” because “substantially” allows for less than “as much as possible.”
Regarding claim 26, the limitation “wherein a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x10 19 atoms/cm3 or less” is unclear as to what is required by the claim. Specifically, “measured by SIMS” appears to be a recitation of a method of using the device (i.e. testing), however the claim is a product claim. It is therefore unclear as to the proper interpretation and/or weight of the limitation. It is further unclear as to how the method of testing the hydrogen concentration would/would not affect the resulting concentration. Specifically, it would seem that if the concentration is required to be 5x10 19 atoms/cm3 or less, that the measured value would and should be the value irrespective of the method of measuring.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 20-25 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ochii et al. (US 5281843; herein “Ochii”) in view of Hayashi (US 5331170; herein “Hayashi”) and Kang et al. (US 20090008638; herein “Kang”).
Regarding claim 20, Ochii discloses in Fig. 1-3 and related text a semiconductor device comprising:
a circuit comprising a first transistor (Q2, see col. 3 line 56), a second transistor (Q6, see col. 3 line 65), and a capacitor (e.g. capacitor formed between 14(WL) of Q2 and portion of 16 overlapping, see Fig. 3),
wherein the first transistor comprises a first channel formation region (in P-sub 11),
wherein the second transistor comprises a second channel formation region (17 of Q6, see col. 4 line 40-42),
wherein the first channel formation region comprises silicon (see col. 4 lines 19-27; see also col. 1 line 11-13, col. 2 lines 16-17),
wherein the second channel formation region comprises a thin film semiconductor layer (16/17),
wherein a first conductive layer (15) functioning as one of a source electrode and a drain electrode of the second transistor (functioning as S/D at portion connected to S/D 16 of Q6, see col. 4 lines 36-39) has a region in contact with a second conductive layer (14) functioning as a gate electrode of the first transistor (functioning as gate at portion above of channel in 11 of Q2, see col. 4 line 29-30); and
wherein, when seen from above, the capacitor has a region overlapping with the first channel formation region (see Fig. 2 and 3).
Ochii does not disclose
a plurality of circuits arranged in matrix,
wherein each of the plurality of circuits comprises the first transistor, the second transistor, and the capacitor,
wherein the second channel formation region comprises an oxide semiconductor layer.
In the same field of endeavor, Hayashi teaches a semiconductor device comprising
a plurality of circuits arranged in matrix (see Fig. 10),
wherein each of the plurality of circuits comprises the same circuitry (see Fig. 10 and col. 6 lines 57-66).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Ochii by having a plurality of same circuits arranged in matrix in order to achieve a robust memory device. Further, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have a memory array, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It has also been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. The limitation “wherein each of the plurality of circuits comprises the first transistor, the second transistor, and the capacitor” is taught by the combination of the array with cells having the same circuitry, as shown by Hayashi, in combination with the cell having the first transistor, the second transistor and the capacitor as shown by Ochii.
In the same field of endeavor, Kang teaches a second transistor (TFT transistor) wherein the second channel formation region comprises an oxide semiconductor layer (see [0045] at least).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Ochii by having the thin film transistor channel formation region comprising an oxide semiconductor, as taught by Kang, in order achieve a TFT having improved electrical characteristics such as good channel mobility and on/off ratio (see [0007] at least).
Regarding claim 21, Ochii further discloses a third conductive layer (e.g. 18(BL)) over the first transistor, the second transistor, and the capacitor, wherein the third conductive layer is electrically connected to the first channel formation region (of Q2, see Fig. 1 and 3).
Regarding claim 22, Ochii further discloses wherein the third conductive layer has a region overlapping with the second channel formation region (see Fig. 3).
Regarding claim 23, the combined device shows wherein the first conductive layer (Ochii: 15) has a region in contact with the oxide semiconductor layer (16/17 of Q6).
Regarding claim 24, Ochii further discloses wherein the first channel formation region (in P-sub 11 of Q2) is formed in a semiconductor layer (see col. 4 lines 19-27; see also col. 1 line 11-13, col. 2 lines 16-17).
Regarding claim 25, the combined device shows an off-state current of the first transistor is 1x10-13 A or less (Kang: [0072]).
Note that the range disclosed by Kang overlaps the claimed range. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the off current to be a result effective variable affecting the electrical properties of the transistor (see Kang [0072]). Thus, it would have been obvious to modify the combined device to have the off current within the claimed range in order to improve electrical properties of the transistor, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Claim 26 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ochii in view of Hayashi and Kang, as applied to claim 21 above, and in further view of Iwasaki et al (US 20090065771; herein “Iwasaki”).
Regarding claim 26, Ochii as modified does not teach or suggest a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x10 19 atoms/cm3 or less.
In the same field of endeavor, Iwasaki teaches a semiconductor device with a channel formation comprising oxide semiconductor (see [0108]) wherein a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5x10 19 atoms/cm3 or less (note that hydrogen is added to the S/D region which results in a concentration of 1x1019 atoms/cm3 or less, see [0123], and the hydrogen concentration in the channel formation region would be smaller).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ochii by having the hydrogen concentration as claimed, as shown by Iwasaki, in order to achieve a transistor with improved mobility and electrical characteristics (see Iwasaki [0010]-[0012]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12543366 (herein “’366”). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of ‘366 recite additional elements of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hayashi et al. (2008) Improved amorphous In-Ga-Zn-O TFTs (previously cited by applicant) is noted for showing an oxide semiconductor channel with an off current as claimed.
US 20080023698 and US 20070187678 are each cited for showing an oxide semiconductor channel with a c-axis alignment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAUREN R BELL/Primary Examiner, Art Unit 2896
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