DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 20-23 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ochii et al. (US 5281843; herein “Ochii”) in view of Hayashi (US 5331170; herein “Hayashi”) and Kang et al. (US 20090008638; herein “Kang”).
Regarding claim 20, Ochii discloses in Fig. 1-3 and related text a semiconductor device comprising:
a circuit comprising a first transistor (Q2, see col. 3 line 56), a second transistor (Q6, see col. 3 line 65), and a capacitor (e.g. capacitor formed between 14(WL) of Q2 and portion of 16 overlapping, see Fig. 3),
wherein the first transistor comprises a first channel formation region (in P-sub 11),
wherein the second transistor comprises a second channel formation region (17 of Q6, see col. 4 line 40-42),
wherein the first channel formation region comprises silicon (see col. 4 lines 19-27; see also col. 1 line 11-13, col. 2 lines 16-17),
wherein the second channel formation region comprises a thin film semiconductor layer (16/17),
wherein a first conductive layer (15) configured to be one of a source electrode and a drain electrode of the second transistor (functioning as S/D at portion connected to S/D 16 of Q6, see col. 4 lines 36-39) has a region in contact with a second conductive layer (14) configured to be a gate electrode of the first transistor (functioning as gate at portion above of channel in 11 of Q2, see col. 4 line 29-30); and
wherein, when seen from above, the capacitor has a region overlapping with the first channel formation region (see Fig. 2 and 3).
Ochii does not disclose
a plurality of circuits arranged in matrix,
wherein each of the plurality of circuits comprises the first transistor, the second transistor, and the capacitor,
wherein the second channel formation region comprises an oxide semiconductor layer.
In the same field of endeavor, Hayashi teaches a semiconductor device comprising
a plurality of circuits arranged in matrix (see Fig. 10),
wherein each of the plurality of circuits comprises the same circuitry (see Fig. 10 and col. 6 lines 57-66).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Ochii by having a plurality of same circuits arranged in matrix in order to achieve a robust memory device. Further, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have a memory array, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It has also been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. The limitation “wherein each of the plurality of circuits comprises the first transistor, the second transistor, and the capacitor” is taught by the combination of the array with cells having the same circuitry, as shown by Hayashi, in combination with the cell having the first transistor, the second transistor and the capacitor as shown by Ochii.
In the same field of endeavor, Kang teaches a second transistor (TFT transistor) wherein the second channel formation region comprises an oxide semiconductor layer (see [0045] at least).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Ochii by having the thin film transistor channel formation region comprising an oxide semiconductor, as taught by Kang, in order achieve a TFT having improved electrical characteristics such as good channel mobility and on/off ratio (see [0007] at least).
Regarding claim 21, Ochii further discloses a third conductive layer (e.g. 18(BL)) over the first transistor, the second transistor, and the capacitor, wherein the third conductive layer is electrically connected to the first channel formation region (of Q2, see Fig. 1 and 3).
Regarding claim 22, Ochii further discloses wherein the third conductive layer has a region overlapping with the second channel formation region (see Fig. 3).
Regarding claim 23, the combined device shows wherein the first conductive layer (Ochii: 15) has a region in contact with the oxide semiconductor layer (16/17 of Q6).
Response to Arguments
Applicant's arguments filed 8/26/2026 have been fully considered but they are not persuasive.
Applicant argues (page 4) the combination of Ochii, Hayashi and Kangdoes not teach or suggest the claimed invention because Ochii “does not describe or suggest, in FIGS. 1-3 or elsewhere, that the first conductive layer 15 is configured to be one of a source electrode and a drain electrode of the second transistor Q6 having a region in contact with the second conductive layer 14 that is configured to be a gate electrode of the first transistor Q2.”
In response, the examiner disagrees. Specifically, it is first noted that Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Further, they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made, nor do they show how the amendments avoid such references or objections.
In the instant case, it is noted that amending the claims from “functioning as” to “configured to be” makes no notable difference as to the scope of the claim. Applicant has not pointed out how the language “configured to” supposedly overcomes the rejection of the previous Office action or how it distinguishes the invention from the prior art.
It is noted that Ochii has a first conductive layer 15 and a second conductive layer 14. At least a portion of layer 15 of Ochii, which is directly connected to source/drain region of the TFT Q6 (see col. 1 lines 62-65), is a source/drain electrode of that transistor, regardless of whether Ochii explicitly calls it a “source electrode” or “drain electrode.” At least a portion layer 14 is explicitly disclosed as gate electrode (functioning as gate at portion above of channel in 11 of Q2, see col. 4 line 29-30), and one would readily recognize it is a gate electrode by Figs. 1-3. Layer 15 has a “region” in contact with, e.g. direct contact, with layer 14 as shown in Fig. 3. It is noted that the claim does not require the source/drain electrode to be in contact with the gate electrode. Rather, the claim merely requires the conductive layers to be in contact.
Additionally, although shown by the prior art, it is noted that the limitation of “configured to be” is a functional limitation of the apparatus claimed. While features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. Additionally, because the device of the prior art has all of the structural limitations of the claimed invention the device is capable of being operated in the manner claimed by the applicant. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. See MPEP 2114.I, 2114.II and 2112.01.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896
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