Prosecution Insights
Last updated: April 19, 2026
Application No. 18/234,502

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Non-Final OA §112
Filed
Aug 16, 2023
Examiner
LI, MEIYA
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
3y 8m
To Grant
95%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allow Rate
628 granted / 912 resolved
+0.9% vs TC avg
Strong +26% interview lift
Without
With
+26.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
52 currently pending
Career history
964
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
34.3%
-5.7% vs TC avg
§102
26.5%
-13.5% vs TC avg
§112
36.0%
-4.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 912 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of group I, species I(a), claims 1-17 and 21-23, in the reply filed on December 8, 2025 is acknowledged. Information Disclosure Statement The information disclosure statements (IDS) submitted on 8/16/23, 8/23/24, 1/22/25, 2/14/25, 3/20/25 and 8/28/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Specification The disclosure is objected to because of the following informalities: Undefined acronyms/symbols, such as “FET” (first occurrence: [0014]); “STI” (first occurrence: [0024]); and “RIE” and “NBE” (first occurrence: [0028]). The examiner suggests that applicant spell out all the acronyms/symbols when using them for the first time in the disclosure. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Objections Claims 1-17 and 21-23 are objected to because of the following informalities: Inconsistent terminologies. Changing “the fin structures” to “the adjacent fin structures” (claims 1 and 5); and to “the two fin structures” (claims 9, 16 and 21), are suggested. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-17 and 21-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitations of "sidewalls and tops of the fin structures", as recited in claim 1, are unclear as to whether said limitations are in one-to-one, one-to-multiple or multiple-to-one between the sidewall and the fin structure, and between the top and the fin structure applicant refers. The term "substantially" in claims 1, 11, 12 and 16 is a relative term which renders the claim indefinite. The term "substantially" is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The claimed limitations of "a height of the fin structures", as recited in claims 1 and 16, is unclear as to a height of each or total of the fin structures applicant refers. The claimed limitation of "the spacer comprises a first portion having a “U” shape disposed on the isolation region", as recited in claim 1, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0029]. See MPEP §2173.03. The claimed limitation of "a first portion of each fin structure", as recited in claim 3, is unclear as to whether said limitation is the same as or different from "a portion of each fin structure", as recited in claim 1. The claimed limitation of "the spacer further comprises a second portion disposed on side surfaces of the sacrificial gate stack", as recited in claim 3, which indefinite and renders the claim uncertain because said limitation is inconsistent with the specification disclosure: i.e. [0028]. See MPEP §2173.03. Claim 4 recites the limitation "the second semiconductor layers" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “alternating first and second semiconductor layers”, as recited in claim 2. The claimed limitation of "portions of the second semiconductor layers", as recited in claim 1, is unclear as to whether said limitation is in one-to-one, one-to-multiple or multiple-to-one between the portion and the second semiconductor layer applicant refers. The claimed limitation of "vertical adjacent first semiconductor layers", as recited in claim 4, is unclear as to whether said limitation is the same as or different from "alternating first and second semiconductor layers", as recited in claim 2. The claimed limitation of "the first", as recited in claims 5 and 6, is unclear as to the first of which element applicant refers. The claimed limitation of "second portions", as recited in claims 5 and 6, is unclear as to whether said limitation is the same as or different from "second portion", as recited in claim 3. The claimed limitation of "portion of the dielectric material", as recited in claim 7, is unclear as to whether said limitation is the same as or different from "portion of the dielectric material", as recited in claim 6. The claimed limitation of "vertical adjacent first semiconductor layers", as recited in claims 7 and 8, is unclear as to whether said limitation is the same as or different from "alternating first and second semiconductor layers", as recited in claim 2 and/or “vertical adjacent first semiconductor layers”, as recited in claim 4. The claimed limitation of "dielectric spacers in the cavities", as recited in claim 8, is unclear as to whether said limitation is in one-to-one, one-to-multiple or multiple-to-one between the dielectric spacer and the cavity applicant refers. The claimed limitation of "the portions of the dielectric material", as recited in claim 8, is unclear as to whether said limitation is the same as or different from “portions of the dielectric material”, as recited in claim 6 and/or claim 7. The claimed limitation of "a portion of each fin structure", as recited in claim 9, line 6-7, is unclear as to whether said limitation is the same as or different from ‘a first portion of each fin structure”, as recited in claim 9, line 4. The claimed limitation of "the portion of each fin structure", as recited in claim 9, line 8, is unclear as to which portion of each fin structure applicant refers: “a first portion”, “a second portion”, and/or “a portion”, as recited in claim 9, lines 4-7. The claimed limitation of “removing the sacrificial gate stack …", as recited in claims 9 and 21, is unclear as to removing the sacrificial gate stack of which element applicant refers. Claim 9 recites the limitation "the first portion of the fin structures" in line 9. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different form “a first portion of each fin structure”, as recited in claim 9, line 4. The claimed limitation of "depositing a dielectric layer", as recited in claims 9 and 21, is unclear as to the structure relationship between said limitation and the claimed device. The claimed limitations of "remaining portions of the dielectric layer are disposed on the first portions of the fin structures and the first portion of the isolation region", as recited in claim 9, are unclear as to whether said limitations are in one-to-one, one-to-multiple or multiple-to-one relationship between the remaining portion and the first portion of the fin structures, and between the remaining portion and the first portion of the isolation region applicant refers. The claimed limitations of "a thickness of the … portions", as recited in claim 1, is unclear as to a thickness of each or total of the … portions applicant refers. The claimed limitation of "portions of the spacer layers", as recited in claim 17, is unclear as to whether said limitation is the same as or different from "a portion of the spacer layer", as recited in claim 16. Claim 21 recites the limitation "the portion of the fin structures" in line 10. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different form “a portion of each fin structure”, as recited in claim 21, line 5. The claimed limitations of "remaining portions of the dielectric layer are disposed on the portions of the fin structures and the portion of the isolation region", as recited in claim 9, are unclear as to whether said limitations are in one-to-one, one-to-multiple or multiple-to-one relationship between the remaining portion and the portion of the fin structures, and between the remaining portion and the portion of the isolation region applicant refers. The claimed limitation of "adjacent semiconductor layers", as recited in claim 23, is unclear as to whether said limitation is the same as or different from "adjacent semiconductor layer", as recited in claim 22. The claimed limitation of "the portions of the dielectric layer", as recited in claim 23, is unclear as to whether said limitation is the same as or different from "portions of the dielectric layer" and/or “remaining portions of the dielectric layer”, as recited in claim 22. Allowable Subject Matter Claims 1-11 and 21-23 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “forming a mask on the spacer layer between the fin structures, wherein the mask has a height less than a height of each of the fin structures; removing portions of the spacer layer and recessing the fin structures to form a spacer and to expose a portion of each fin structure, wherein the spacer comprises a second portion having a "U" shape disposed on the isolation region, the portion of each fin structure has a top surface located at a level below a level of a top surface of the isolation region”, as recited in claim 1; depositing a dielectric layer on the isolation region, sidewalls and top of each fin structure and a sidewall of the sacrificial gate stack; removing portions of the dielectric layer, wherein remaining portions of the dielectric layer are disposed on the first portions of the fin structures and the first portion of the isolation region, respectively”, as recited in claims 9 and 21. Claims 1-17 and 21-23 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ref's A-C are cited as being related to a method of forming a semiconductor structure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEIYA LI/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Aug 16, 2023
Application Filed
Feb 19, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
95%
With Interview (+26.0%)
3y 8m
Median Time to Grant
Low
PTA Risk
Based on 912 resolved cases by this examiner. Grant probability derived from career allow rate.

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