/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847 DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/02/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 4 and 7 – 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakai et al. (US 20060103004 A1, “Sakai”).
Regarding claim 1, Sakai discloses (Figs. 2 and 7) an integrated substrate, comprising: a) a top structure (First Layer) having a plurality of first pads (106 – 108) for mounting electronic devices (121), wherein each of the first pads is electrically coupled with a corresponding electronic device (Fig. 2 or 7), such that each of the first pads has a corresponding potential; b) a bottom structure (Fifth Layer) having a plurality of second pads (111 – 113) for coupling with peripheral circuits; c) a plurality of intermediate metal layers (Second, Third and Fourth Layers) stacked up and down and located between the top structure and the bottom structure, wherein the plurality of intermediate metal layers is configured to complete a partial electrical connection in order to form a full electrical connection; (See Fig. 7) d) a first type of penetrating connection structures (109a, 109b, 109d, 109e) configured to couple the intermediate metal layers and a part of the first pads, such that the intermediate metal layers have the same potential as the part of the first pads; and e) a second type of penetrating connection structures (109c, 109f, 109g) configured to couple the intermediate metal layers and the second pads, such that the second pads have the same potential as the part of the first pads (See Fig. 2 or 7).
Regarding claim 2, Sakai discloses the integrated substrate of claim 1, wherein different first pads (106 – 108) are coupled to the plurality of the intermediate metal layers (Second, Third and Fourth Layers) through the plurality of the first type of penetrating connection structures (109a, 109b, 109d, 109e) respectively, such that potentials of the intermediate metal layers and the first pads are correspondingly equal (Figs. 2 or 7 and Claims 1 – 3).
Regarding claim 3, Sakai discloses the integrated substrate of claim 1, wherein the plurality of the intermediate metal layers (Second, Third and Fourth Layers) are not in the same plane (see Fig. 2 or 7), and different intermediate metal layers respectively correspond to different potentials (Third and Fourth Layers will have different potentials).
Regarding claim 4, Sakai discloses the integrated substrate of claim 3, wherein an adjacent two intermediate metal layers (Third and Fourth Layers) are at least partially overlapped (see Fig. 2 or 7).
Regarding claim 7 Sakai discloses the integrated substrate of claim 1, wherein insulating materials are filled between any adjacent two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See para [0052]).
Regarding claim 8, Sakai discloses the integrated substrate of claim 1, wherein at least one hole is opened in at least one of the top structure, the bottom structure, and the plurality of intermediate metal layers, for avoiding one or more corresponding penetrating connection structures (Fig. 2 or 7).
Regarding claim 9, Sakai discloses the integrated substrate of claim 1, wherein: a) one penetrating connection structure comprising the first type of penetrating connection structure (109a, 109b, 109d, 109e) and the second type of penetrating connection structure (109c, 109f, 109g) is configured to connect only two of the top structure (First Layer), the bottom structure (Fifth Layer), and the plurality of intermediate metal layers (Second, Third and Fourth Layers); and b) a hole is opened in each layer between the only two of the top structure (First Layer), the bottom structure (Fifth Layer), and the plurality of intermediate metal layers (Second, Third and Fourth Layers), in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer between the two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See Fig. 2 or 7).
Regarding claim 10, Sakai discloses the integrated substrate of claim 1, wherein:
a) one penetrating connection structure comprising the first type of penetrating connection structure (109a, 109b, 109d, 109e) and the second type of penetrating connection structure (109c, 109f, 109g) is configured to connect only two of the top structure (First Layer), the bottom structure (Fifth Layer), and the plurality of intermediate metal layers (Second, Third and Fourth); and b) a hole is opened in each layer except the only two of the top structure, the bottom structure, and the plurality of intermediate metal layers, in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer except the two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See Fig. 2 or 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 – 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20060103004 A1, “Sakai”) in view of FU et al. (US 20230345643 A1, “FU”)
Regarding claim 5, Sakai discloses the integrated substrate of claim 1,
Sakai is silent on further comprising electronic devices arranged on the intermediate metal layers, wherein pins of the electronic devices are electrically coupled with the intermediate metal layers.
However, FU discloses (Fig. 11) further comprising electronic devices (50) arranged on the intermediate metal layers (91), wherein pins of the electronic devices are electrically coupled with the intermediate metal layers (See para [0036]).
Sakai and FU are both considered to be analogous to the claimed invention because they are in the same field of integrated substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakai to incorporate the teachings of FU and provide further comprising electronic devices (50) arranged on the intermediate metal layers (91), wherein pins of the electronic devices are electrically coupled with the intermediate metal layers (See para [0036]). Doing so would contribute to a more reliable, compact, and thermally stable packaging structure by reducing dependency on crack-prone soldering processes, and improving electrical performance (para [0041] – [0043]).
Regarding claim 6, Sakai in view of FU discloses the integrated substrate of claim 5, wherein Sakai further discloses (Fig. 2 or 7) that the intermediate metal layer has a plurality of discontinuous regions, and potentials of the plurality of discontinuous regions are not all equal (Fig. 2 or 7).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20060103004 A1, “Sakai”) in view of GREANEY et al. (US 20210352802 A1, “GREANEY”)
Regarding claim 10, In the event that a judicial tribunal finds that Sakai fails to disclose all the limitations of claim 10, claim 10 is alternately rejected under 103 over Sakai in view of GREANEY
Sakai discloses the integrated substrate of claim 1, wherein:
a) one penetrating connection structure comprising the first type of penetrating connection structure (109a, 109b, 109d, 109e) and the second type of penetrating connection structure (109c, 109f, 109g) is configured to connect only two of the top structure (First Layer), the bottom structure (Fifth Layer), and the plurality of intermediate metal layers (Second, Third and Fourth); and
Sakai is silent on b) a hole is opened in each layer except the only two of the top structure, the bottom structure, and the plurality of intermediate metal layers, in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer except the two of the top structure, the bottom structure, and the plurality of intermediate metal layers.
However, GREANEY discloses (Fig. 4A) a hole is opened in each layer (404, 406) except the only two of the top structure, the bottom structure, and the plurality of intermediate metal layers (402, 408), in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer except the two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See para [0083] & [0084] and Fig. 4A).
Sakai and GREANEY are both considered to be analogous to the claimed invention because they are in the same field of integrated substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakai to incorporate the teachings of GREANEY and provide a hole is opened in each layer (404, 406) except the only two of the top structure, the bottom structure, and the plurality of intermediate metal layers (402, 408), in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer except the two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See para [0083] & [0084] and Fig. 4A). Doing so would improve performance (para [0084]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai et al. (US 20060103004 A1, “Sakai”) as applied to claim 8 above, and further in view of Kushta (US 20130099876 A1, “Kushta”).
Regarding claim 11, Sakai discloses the integrated substrate of claim 8,
Sakai is silent on wherein a distance between an edge of the hole and the penetrating connection structure is greater than a predetermined threshold
However Kushta discloses (Fig. 3A) wherein a distance between an edge of the hole and the penetrating connection structure is greater than a predetermined threshold (since the predetermined threshold is between 0.00254 mm to 0.0254 mm, see para [0092]).
Sakai and Kushta are both considered to be analogous to the claimed invention because they are in the same field of integrated substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sakai to incorporate the teachings of Kushta and provide wherein a distance between an edge of the hole and the penetrating connection structure is greater than a predetermined threshold (since the predetermined threshold is between 0.00254 mm to 0.0254 mm, see para [0092]). Doing so would minimizes the capacitive discontinuity and help control the coupling.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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/SIDI M MAIGA/Examiner, Art Unit 2847
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