DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/19/2025 have been fully considered but they are not persuasive. Applicant argued that the prior art does not disclose “an integrated substrate that includes a plurality of intermediate metal layers stacked up and down and located between the top structure and the bottom structure, and being configured to complete partial electrical connections, such that the intermediate metal layers have the same potential as the part of the first pads and the second pads”. Examiner respectfully disagree: as it can be seen from Fig. 1A of Kushta discloses an integrated substrate that includes a plurality of intermediate metal layers (1L2, 1L4, 1L6) stacked up and down and located between the top structure and the bottom structure, and being configured to complete partial electrical connections (Conductor plates 1L2, 1L4 are not connected to the signal via (101)) such that the intermediate metal layers have the same potential as the part of the first pads and the second pads (See Fig. 1A)
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 stated that “and being configured to complete partial electrical connection”. This statement is indefinite: it’s not clear what partial electrical connection is.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 4, 7 – 9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kushta (US 20130099876 A1, “Kushta”).
Regarding claim 1, Kushta discloses (Figs. 1A, 2A, 3A) an integrated substrate, comprising: a) a top structure (1L1) having a plurality of first pads (104) for mounting electronic devices, wherein each of the first pads is electrically coupled with a corresponding electronic device (See annotated figure below), such that each of the first pads has a corresponding potential; b) a bottom structure (1L12) having a plurality of second pads (See annotated figure below) for coupling with peripheral circuits; c) a plurality of intermediate metal layers (1L2, 1L4, 1L6) stacked up and down and located between the top structure and the bottom structure, and being configured to complete partial electrical connection (Conductor plates 1L2, 1L4 are not connected to the signal via (101)); d) a first type of penetrating connection structures (101) configured to couple the intermediate metal layers and a part of the first pads, such that the intermediate metal layers have the same potential as the part of the first pads; and e) a second type of penetrating connection structures (112) configured to couple the intermediate metal layers and the second pads, such that the second pads have the same potential as the part of the first pads (See annotated figure below).
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Regarding claim 2, Kushta discloses the integrated substrate of claim 1, wherein different first pads (104) are coupled to the plurality of the intermediate metal layers (1L2, 1L6) through the plurality of the first type of penetrating connection structures (101) respectively, such that potentials of the intermediate metal layers (1L2, 1L6) and the first pads (104) are correspondingly equal.
Regarding claim 3, Kushta discloses the integrated substrate of claim 1, wherein the plurality of the intermediate metal layers (1L2 – 1L11) are not in the same plane (see Fig. 1A), and different intermediate metal layers respectively correspond to different potentials (1L4 and 1L6 will have different potentials).
Regarding claim 4, Kushta discloses the integrated substrate of claim 3, wherein an adjacent two intermediate metal layers (1L4 and 1L6) are at least partially overlapped (see Fig. 1A).
Regarding claim 7 Kushta discloses the integrated substrate of claim 1, wherein insulating materials (116) are filled between any adjacent two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See Fig. 1A).
Regarding claim 8, Kushta discloses the integrated substrate of claim 1, wherein at least one hole (118) is opened in at least one of the top structure, the bottom structure, and the plurality of intermediate metal layers, for avoiding one or more corresponding penetrating connection structures (Fig. 1A and para [0065]).
Regarding claim 9, Kushta discloses the integrated substrate of claim 1, wherein: a) one penetrating connection structure comprising the first type of penetrating connection structure (101) and the second type of penetrating connection structure (112) is configured to connect only two of the top structure (1L1), the bottom structure (1L12), and the plurality of intermediate metal layers (1L2, 1L4, 1L6); and b) a hole (118) is opened in each layer between the only two of the top structure (1L1), the bottom structure (1L12), and the plurality of intermediate metal layers (1L2, 1L4, 1L6), in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer between the two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See Fig. 1A).
Regarding claim 11, Kushta discloses the integrated substrate of claim 8, wherein a distance between an edge of the hole and the penetrating connection structure is greater than a predetermined threshold (since the predetermined threshold is between 0.00254 mm to 0.0254 mm, see annotated figure below).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 – 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kushta (US 20130099876 A1, “Kushta”) in view of FU et al. (US 20230345643 A1, “FU”)
Regarding claim 5, Kushta discloses the integrated substrate of claim 1,
Kushta is silent on further comprising electronic devices arranged on the intermediate metal layers, wherein pins of the electronic devices are electrically coupled with the intermediate metal layers.
However, FU discloses (Fig. 11) further comprising electronic devices (50) arranged on the intermediate metal layers (91), wherein pins of the electronic devices are electrically coupled with the intermediate metal layers (See para [0036]).
Kushta and FU are both considered to be analogous to the claimed invention because they are in the same field of integrated substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kushta to incorporate the teachings of FU and provide further comprising electronic devices (50) arranged on the intermediate metal layers (91), wherein pins of the electronic devices are electrically coupled with the intermediate metal layers (See para [0036]). Doing so would contribute to a more reliable, compact, and thermally stable packaging structure by reducing dependency on crack-prone soldering processes, and improving electrical performance (para [0041] – [0043]).
Regarding claim 6, Kushta in view of FU discloses the integrated substrate of claim 5, wherein Kushta further discloses (Fig. 2A) that the intermediate metal layer has a plurality of discontinuous regions (218, 206, 213, 220), and potentials of the plurality of discontinuous regions are not all equal.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kushta (US 20130099876 A1, “Kushta”) in view of GREANEY et al. (US 20210352802 A1, “GREANEY”)
Regarding claim 10, Kushta discloses the integrated substrate of claim 1, wherein:
a) one penetrating connection structure comprising the first type of penetrating connection structure (101) and the second type of penetrating connection structure (112) is configured to connect only two of the top structure (1L1), the bottom structure (1L12), and the plurality of intermediate metal layers (1L2, 1L4, 1L6); and
Kushta is silent on b) a hole is opened in each layer except the only two of the top structure, the bottom structure, and the plurality of intermediate metal layers, in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer except the two of the top structure, the bottom structure, and the plurality of intermediate metal layers.
However, GREANEY discloses (Fig. 4A) a hole is opened in each layer (404, 406) except the only two of the top structure, the bottom structure, and the plurality of intermediate metal layers (402, 408), in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer except the two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See para [0083] & [0084] and Fig. 4A).
Kushta and GREANEY are both considered to be analogous to the claimed invention because they are in the same field of integrated substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kushta to incorporate the teachings of GREANEY and provide a hole is opened in each layer (404, 406) except the only two of the top structure, the bottom structure, and the plurality of intermediate metal layers (402, 408), in order to generate a conductor-free region for avoiding the penetrating connection structure, such that the penetrating connection structure is not connected with the each layer except the two of the top structure, the bottom structure, and the plurality of intermediate metal layers (See para [0083] & [0084] and Fig. 4A). Doing so would improve performance (para [0084]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SIDI M MAIGA/
Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847