DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 05/23/2026 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claim(s) 1, 9, 11, and 16-17 filed on 06/14/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 2-8, 10, 12-15, and 16-20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 11-16, filed 04/06/2026 with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LEEH, and CHO.
Regarding Independent Claim(s) 1 and 16. The Applicant argues (see Remarks, page 12) that the SUNG art fails to teach or suggest that “ a display device comprising: the second connection wiring is disposed on a same layer as the second oxide semiconductor pattern.” The Applicant further amended the independent claim(s) 1 and 16, now recites, “a display device comprising: a first connection wiring…a top surface of a same layer…each of the first connection wiring…directly contacting… which they are disposed, a second connection wiring…a top surface…each of the second connection wiring…semiconductor pattern…same layer…disposed.” The Examiner agrees that the arguments and further amendments to Claim(s) 1 and 16, are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of LEEH teaches a display device comprising: a second connection wiring (Fig. 7B, 1175G, second electrode layer) electrically connecting (Fig. 7B, 1163G, second contact hole) the second silicon transistor or the second oxide transistor (Fig. 7B, TFT2, switching thin film transistor) to the second sub-light emitting element (Fig. 7B, OLED2), overlapping the first area (Fig. 7B, PX1/PX2, first/second pixel), disposed on a top surface of a same layer (Figs. 7B, 115, interlayer insulating layer) as the second oxide semiconductor pattern (Fig. 7B, 1175B, third electrode layer), and including a transparent conductive oxide ([0101]), each of the second connection wiring (Fig. 7B, 1175G, second electrode layer) and the second oxide semiconductor pattern (Fig. 7B, 1175B, third electrode layer) directly contacting the top surface of the same layer (Figs. 7B, 115, interlayer insulating layer) on which they are disposed.
Regarding Independent Claim(s) 11. The Applicant argues (see Remarks, page 15), that the prior art, SUNG fails to teach or suggest, “the first connection wiring and the second connection wiring, disposed on different layers from each other.” The Examiner agrees that the arguments with respect to Claim(s) 11, are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, CHO teaches a display device (Fig. 1, [0030]) comprising: a first connection wiring (Fig. 5, 185, connection electrodes) electrically connecting (Fig. 5, 63, connection hole) the first silicon transistor or the first oxide transistor (Fig. 5, T6) and the first sub-light emitting element (Fig. 5, OLED), overlapping the first area (Fig. 1, DA, display area), disposed on a same layer (Fig. 5, 118/119, first/second planarization layer) as the first upper electrode (Fig. 5, 183, supply voltage line), and including a transparent conductive oxide (the connection electrodes, may each include material having high conductivity, such as a metal or a conductive oxide, [0138]), a second connection wiring (Fig. 5, 173, connection electrodes) electrically connecting (Fig. 5, 34, contact hole) the second silicon transistor or the second oxide transistor (Fig. 5, T3) and the second sub-light emitting element (Fig. 5, OLED), overlapping the first area (Fig. 1, DA, display area), disposed on a layer (Fig. 5, 116, interlayer insulation layer) different from the first connection wiring (Fig. 5, 185, connection electrodes), and including a transparent conductive oxide (the connection electrodes, 173 may each include material having high conductivity, such as a metal or a conductive oxide, [0138]).
Regarding Claim(s) 2-10, 12-15 and 17-20: The dependent claims 2-10, 12-15, and 17-20 follow similar arguments as Claim(s) 1, 11, and 16, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Donghyun LEED et al, (hereinafter LEED), US 20200194532 A1, in view of Eun Jin Sung et al, (hereinafter SUNG), US 20200104562 A1, and Hyeonbum LEE et al, (hereinafter LEEH), US 20210225987 A1.
Regarding Claim 1, LEED teaches in Figure 5, a display device (EL display device, [0024]) comprising:
a display area (AA) including a first area (TEA, transparent emission area) and a second area (DEA, driving emission area) adjacent to the first area (TEA, transparent emission area); and
a display panel ([0006]) including a base layer (SUB, substrate) including a peripheral area (IA, non-display area, [0046]) adjacent to the display area (AA), an insulating layer (buffer film (not illustrated), [0085]) disposed on the base layer (SUB, substrate), and a first pixel (annotated Figure 5, TEP, transparent emission pixels) and a second pixel (annotated Figure 5, DEP, driving emission pixels) disposed on the base layer (SUB, substrate),
wherein the first pixel (annotated Figure 5, TEP, transparent emission pixels) comprises a first sub-pixel (annotated Figure 5, plurality of TEP, transparent emission pixels, [0115]) and a second sub-pixel (annotated Figure 5, plurality of TEP, transparent emission pixels, [0115]) that are different from each other, wherein the first sub-pixel (annotated Figure 5, plurality of TEP, transparent emission pixels, [0115]) comprises a first sub-light emitting element (annotated Figure 5, ED, light emitting element) disposed in the first area (TEA, transparent emission area) and a first sub-pixel circuit electrically connected (annotated Figure 5, PCT, transparent emission pixel circuits) the first sub-light emitting element (annotated Figure 5, ED, light emitting element),
wherein the second sub-pixel (annotated Figure 5, plurality of TEP, transparent emission pixels, [0115]) comprises a second sub-light emitting element (annotated Figure 5, ED, light emitting element) disposed in the first area (TEA, transparent emission area) and a second sub-pixel circuit electrically connected (annotated Figure 5, PCT, transparent emission pixel circuits) to the second sub-light emitting element (annotated Figure 5, ED, light emitting element),
wherein the second pixel (annotated Figure 5, DEP, driving emission pixels) comprises a second light emitting element (annotated Figure 5, ED, light emitting element) disposed in the second area (DEA, driving emission area) and a second pixel circuit electrically connected (annotated Figure 5, PCD, driving emission pixel circuits) to the second light emitting element (annotated Figure 5, ED, light emitting element) and disposed in the second area (DEA, driving emission area),
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wherein the first sub-pixel circuit (annotated Figure 5, PCT, transparent emission pixel circuits) comprises:
a first silicon transistor (Figs. 2/4, DT2/ST2, second driving thin-film transistor/ second switching thin-film transistor, [0062], [0090]) including a first silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]) including a drain area (Fig. 4, DD2, second drain electrode), an active area (Fig. 4, DA2, second semiconductor layer), and a source area (Fig. 4, first DS2, second source electrode) and a first gate electrode (Fig. 4, DG2, first gate electrode) overlapping the active area (Fig. 4, DA2, first semiconductor layer) of the first silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]), and disposed in the second area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]);
a first oxide transistor (Fig. 2, ST2/DT2, second switching transistor/second driving thin-film transistor, [0062], [0090]) including a first oxide semiconductor pattern including a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern (see note below), and disposed in the second area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]); [Note: even though the reference does not disclose or suggest a drain area, an active area, a source area and a second gate area, however it is known in the art that the second switching transistor (ST2) or second driving transistor (DT2) as first oxide transistor will necessarily include a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern, [0062], [0090]).
wherein the second sub-pixel circuit (Figure 5, PCT, transparent emission pixel circuits) comprises:
a second silicon transistor (Figs. 2/4, DT2/ST2, second driving thin-film transistor/ second switching thin-film transistor, [0062], [0090]) including a second silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]) including a drain area (Fig. 4, DD2, second drain electrode), an active area (Fig. 4, DA2, second semiconductor layer), and a source area (Fig. 4, first DS2, second source electrode) and a third gate electrode (Fig. 4, DG2, first gate electrode) overlapping the active area (Fig. 4, DA2, first semiconductor layer) of the second silicon semiconductor pattern (Fig. 3, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]), and disposed in the second area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]);
a second oxide transistor (Fig. 2, ST2/DT2, second switching thin-film transistor/ second driving thin-film transistor, [0062], [0090]) including a second oxide semiconductor pattern including a drain area, an active area, and a source area and a fourth gate electrode overlapping the active area of the second oxide semiconductor pattern (see note below), and disposed in the second area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]); [Note: even though the reference does not disclose or suggest a drain area, an active area, a source area and a second gate area, however it is known in the art that the second switching transistor (ST2) or second driving transistor (DT2) as first oxide transistor will necessarily include a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern, [0062], [0090]).
LEED does not disclose explicitly a display device comprising: a first upper electrode overlapping the first gate electrode; and a second upper electrode overlapping the third gate electrode.
SUNG teaches in Figures 15-16, a display device (Fig. 1, 100, [104]) comprising:
a first upper electrode (Fig. 15, UE, [0210]) overlapping the first gate electrode (Fig. 15, GE1, [0210]); and
a second upper electrode (Fig. 15, UE, [0210]) overlapping the third gate electrode (Fig. 15, GE1, [0210]);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEED to incorporate the teachings of SUNG, such that a display device comprising: a first upper electrode overlapping the first gate electrode; and a second upper electrode overlapping the third gate electrode, The aforementioned arrangement of plurality of transistors in connection with contact electrodes, light emitting element thus facilitates as a sensor device for finger printing that can prevent the moiré effect that may occur in the photo-sending by adjusting the resolutions of a light transmitting hole array layer and a photo-sensor array layer that overlaps with the light transmitting hole layer (SUNG, [0278]).
LEED as modified by SUNG does not explicitly disclose a display device comprising: a first connection wiring electrically connecting the first silicon transistor or the first oxide transistor to the first sub-light emitting element, overlapping the first area, disposed on a top surface of a same layer as the first upper electrode, and including a transparent conductive oxide, each of the first connection wiring and the first upper electrode directly contacting the top surface of the same layer on which they are disposed; and a second connection wiring electrically connecting the second silicon transistor or the second oxide transistor to the second sub-light emitting element, overlapping the first area, disposed on a top surface of a same layer as the second oxide semiconductor pattern, and including a transparent conductive oxide, each of the second connection wiring and the second oxide semiconductor pattern directly contacting the top surface of the same layer on which they are disposed.
LEEH teaches a display device (Fig. 2, 10, display panel) comprising:
a first connection wiring (Fig. 7B, 1175R, first electrode layer) electrically connecting (Fig. 7B, 1163R, first contact hole) the first silicon transistor or the first oxide transistor (Fig. 7B, TFT1, driving thin film transistor) to the first sub-light emitting element (Fig. 7B, OLED1), overlapping the first area (Fig. 7B, PX1/PX2, first/second pixel), disposed on a top surface of a same layer (Figs. 7B, 115, interlayer insulating layer) as the first upper electrode (Figs. 7B, DL/PL, data line/driving voltage line), and including a transparent conductive oxide ([0101]), each of the first connection wiring (Fig. 7B, 1175R, first electrode layer) and the first upper electrode (Figs. 7B, DL/PL, data line/driving voltage line) directly contacting the top surface of the same layer (Figs. 7B, 115, interlayer insulating layer) on which they are disposed; and
a second connection wiring (Fig. 7B, 1175G, second electrode layer) electrically connecting (Fig. 7B, 1163G, second contact hole) the second silicon transistor or the second oxide transistor (Fig. 7B, TFT2, switching thin film transistor) to the second sub-light emitting element (Fig. 7B, OLED2), overlapping the first area (Fig. 7B, PX1/PX2, first/second pixel), disposed on a top surface of a same layer (Figs. 7B, 115, interlayer insulating layer) as the second oxide semiconductor pattern (Fig. 7B, 1175B, third electrode layer), and including a transparent conductive oxide ([0101]), each of the second connection wiring (Fig. 7B, 1175G, second electrode layer) and the second oxide semiconductor pattern (Fig. 7B, 1175B, third electrode layer) directly contacting the top surface of the same layer (Figs. 7B, 115, interlayer insulating layer) on which they are disposed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG to incorporate the teachings of LEEH, such that a display device comprising: a first connection wiring electrically connecting the first silicon transistor or the first oxide transistor to the first sub-light emitting element, overlapping the first area, disposed on a top surface of a same layer as the first upper electrode, and including a transparent conductive oxide, each of the first connection wiring and the first upper electrode directly contacting the top surface of the same layer on which they are disposed; and a second connection wiring electrically connecting the second silicon transistor or the second oxide transistor to the second sub-light emitting element, overlapping the first area, disposed on a top surface of a same layer as the second oxide semiconductor pattern, and including a transparent conductive oxide, each of the second connection wiring and the second oxide semiconductor pattern directly contacting the top surface of the same layer on which they are disposed, so that the display apparatuses has fabricated with various configurations to increase their display quality (LEEH, [0005]).
Regarding Claim 2, LEED as modified by SUNG and LEEH teaches the display device of claim 1.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein the insulating layer ([0180]) comprises:
a lower insulating layer (Fig. 16B, INS1, first insulating layer, [0224]) under the first upper electrode (Fig. 16A, LE) and the second upper electrode (Fig. 16A, UE); and
an upper insulating layer (Figs. 16A/16B, INS2/INS3, second insulating layer/third insulating layer, [0224]) on the first upper electrode (Fig. 16A, LE) and the second upper electrode (Fig. 16A, UE); (NOTE: the circuit element layer, BPL may include a plurality of circuit elements each of which is formed in a corresponding one of the pixel areas, PXA to form a pixel circuit of the corresponding pixel PXL, [0109]).
Regarding Claim 3, LEED as modified by SUNG and LEEH teaches the display device of claim 2.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein the first and second oxide semiconductor patterns (Figs. 16B, ACT1/ GE1; DE2/SE3; Fig. 16A, ACT3b/DE3b/DE4b/DE4a; ACT7/SE7/GE7/DE7) and the second connection wiring (Figs. 16A/16B, CNL, OPN/CH1/CH2/CH7) are disposed on the upper insulating layer (Figs. 16A/16B, INS2/INS3, second insulating layer/third insulating layer, [0224]).
Regarding Claim 4, LEED as modified by SUNG and LEEH teaches the display device of claim 2.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein the upper insulating layer (Figs. 16A/16B, INS2/INS3, second insulating layer/third insulating layer, [0224]) covers the first connection wiring (Figs. 16A/16B, CNL, AUX, CH8/CH7/CH2/CH1), the first upper electrode (Fig. 16A, LE) and the second upper electrode (Fig. 16A, UE).
Regarding Claim 5, LEED as modified by SUNG and LEEH teaches the display device of claim 2.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), further comprising insulating patterns (Figs. 16A/16B, INS1/INS2/INS3, first insulating layer/second insulating layer/third insulating layer, [0224]) disposed between the active area of the first oxide semiconductor pattern (Figs. 16A/16B, ACT7/ACT3/ACT1) and the second gate electrode (Figs. 16A/16B, GE7/GE1) and between the active area of the second oxide semiconductor pattern (Figs. 16A/16B, ACT7/ACT3/ACT1) and the fourth gate electrode (Figs. 16A/16B, GE7/GE1/GE4), respectively. (NOTE: the circuit element layer, BPL may include a plurality of circuit elements each of which is formed in a corresponding one of the pixel areas, PXA to form a pixel circuit of the corresponding pixel PXL, [0109]).
Regarding Claim 6, LEED as modified by SUNG and LEEH teaches the display device of claim 2.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein the insulating layer (Figs. 16A/16B, INS4, fourth insulating layer/third insulating layer, [0224]) is disposed on the upper insulating layer (Figs. 16A/16B, INS1/INS2/INS3, second insulating layer/third insulating layer, [0224]) and further comprises a cover insulating layer (Figs. 16A/16B, INS4, fourth insulating layer/third insulating layer, [0224]) covering the first and second oxide semiconductor patterns Figs. 16B, ACT1/ GE1; DE2/SE3; Fig. 16A, ACT3b/DE3b/DE4b/DE4a; ACT7/SE7/GE7/DE7) and the second connection wiring .
Regarding Claim 7, LEED as modified by SUNG and LEEH teaches the display device of claim 6.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein the cover insulating layer (Figs. 16A/16B, INS4, fourth insulating layer/third insulating layer, [0224]) has an opening (Fig. 16A, CH10, tenth contact hole) corresponding to the first area (Fig. 16A, PXA),
wherein a portion of the second connection wiring (Fig. 16A, CNL, connection line) is exposed by the opening (Fig. 16A, CH10, tenth contact hole) defined in the cover insulating layer (Figs. 16A/16B, INS4, fourth insulating layer/third insulating layer, [0224]).
Regarding Claim 10, LEED as modified by SUNG and LEEH teaches the display device of claim 1.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein an electrical conductivity (third conductive layer is formed of metal, [0238-0239]) of the second connection wiring (Fig. 16A, CNL, connection line) is greater than (connection line, CNL is formed of metal having electrical conductivity greater than the semiconductor patterns with gate electrodes and active layers formed of conductive polymers or conductive metal oxides) an electrical conductivity (first conductive layer formed of a conductive polymer or conductive metal oxide, [0223], [0273]) of the active area (ACT1 to ACT7, [0273]) of the first and second oxide semiconductor patterns (GE1 to GE7, [0273]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEED, in view of SUNG and LEEH as applied to Claim(s) 1-7, and 10 above, and further in view of Ji Hun Ryu et al, (hereinafter RYU), US 20200394381 A1.
Regarding Claim 8, LEED as modified by SUNG and LEEH teaches the display device of claim 1.
LEED as modified by SUNG and LEEH does not explicitly disclose the display device, wherein the first connection wiring, the second connection wiring, the first and second upper electrodes, and the first and second oxide semiconductor patterns each comprise at least one of In, Zn, and Sn.
RYU teaches the display device (Fig. 2, 10), wherein the first connection wiring (Fig. 20, Si-1/Si/Si+1, control lines, [0248]), the second connection wiring (Fig. 20, Si-1/Si/Si+1, control lines, [0248]), the first and second upper electrodes (Fig. 20, capacitor electrodes, [0248]), and the first and second oxide semiconductor patterns (Fig. 18, GE1-GE7, gate electrodes, [0248]) each comprise at least one of In, Zn, and Sn (Indium Tin Zinc Oxide (ITZO), ZnO/SnO2, Indium Zinc Oxide (IZO), [0248]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG and LEEH to incorporate the teachings of RYU, such that the display device, wherein the first connection wiring, the second connection wiring, the first and second upper electrodes, and the first and second oxide semiconductor patterns each comprise at least one of In, Zn, and Sn, so that the circuit components such as control lines, capacitor electrodes and semiconductor gate electrodes exhibit excellent electrical conductive properties for a photo-sensing display device (RYU, [0090-0091], [0248]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEED, in view of SUNG and LEEH as applied to Claim(s) 1-7, and 10 above, and further in view of Yangzhao Ma et al, (hereinafter MA), US 20220035408 A1, and Miao Chang et al, (hereinafter CHANG), US 20220093682 A1.
Regarding Claim 9, LEED as modified by SUNG and LEEH teaches the display device of claim 1.
LEED as modified by SUNG and LEEH does not explicitly disclose the display device, wherein the display area further comprises a third area adjacent to the second area, wherein the display panel further comprises a third pixel disposed in the third area, wherein the third pixel comprises a third light emitting element disposed in the third area and a third pixel circuit electrically connected to the third light emitting element and disposed in the third area.
MA teaches the display device (Fig. 14, 2),
wherein the display area (Fig. 2, AA) further comprises a third area (Fig. 2, AA1, first display area) adjacent to the second area (Fig. 2, AA2, second display area),
wherein the display panel (Fig. 2, 2) further comprises a third pixel (annotated Figures 2) disposed in the third area (Fig. 2, AA1, first display area),
wherein the third pixel (annotated Figures 2) comprises a third light emitting element (Fig. 2, EM1, first light-emitting units) disposed in the third area (Fig. 2, AA1, first display area) and a third pixel circuit (Fig. 2, PD1, first pixel circuits) electrically connected (Fig. 3, [0054]) to the third light emitting element (Fig. 2, EM1, first light-emitting units) and disposed in the third area (Fig. 2, AA1, first display area).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG and LEEH to incorporate the teachings of MA, such that the display device, wherein the display area further comprises a third area adjacent to the second area, wherein the display panel further comprises a third pixel disposed in the third area, wherein the third pixel comprises a third light emitting element disposed in the third area and a third pixel circuit electrically connected to the third light emitting element and disposed in the third area, so that the light transmittance of the display area, AA is increased (MA, [0076]).
LEED as modified by SUNG, LEEH and MA does not explicitly disclose the display device, wherein a number of second light emitting elements disposed per unit area of the second area is less than a number of third light emitting elements disposed per unit area of the third area, wherein a sum of numbers of first sub-light emitting elements and second sub-light emitting elements disposed per unit area of the first area is less than the number of third light emitting elements disposed per unit area of the third area, and
CHANG teaches the display device (Fig. 7, displace device includes a housing, [0058]),
wherein a number of second light emitting elements disposed per unit area (Fig. 2, 31, sub-pixels) of the second area (Fig. 2, 30, third display area) is less than ([0044]) a number of third light emitting elements disposed per unit area (Fig. 2, 21, sub-pixels) of the third area (Fig. 2, 20, second display area), and
wherein a sum of numbers of first sub-light emitting elements and second sub-light emitting elements disposed per unit area (Fig. 2, 11, sub-pixels) of the first area (Fig. 2, 10, first display area) is less than ([0044]) the number of third light emitting elements (Fig. 2, 21, sub-pixels) disposed per unit area of the third area (Fig. 2, 20, second display area).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG, LEEH and MA to incorporate the teachings of CHANG, such that the display device, wherein a number of second light emitting elements disposed per unit area of the second area is less than a number of third light emitting elements disposed per unit area of the third area, and wherein a sum of numbers of first sub-light emitting elements and second sub-light emitting elements disposed per unit area of the first area is less than the number of third light emitting elements disposed per unit area of the third area. With this arrangement, a number of the pixel circuits, 32 corresponding to the sub-pixels, 31, in the third display area, 30 is small so there can be extra space in the third display are, 30 for arranging the pixel circuits, 12 corresponding to the sub-pixels, 11 in the first display area can be ensured to have a high definition (CHANG, [0045], [0051]).
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Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEED, in view of SUNG, and CHANG as applied to Claim(s) 1-10 above, and further in view of Yoonjong Cho et al, (hereinafter CHO), US 20210249498 A1.
Regarding Claim 11, LEED teaches in Figure 5, a display device (EL display device, [0024]) comprising:
a display area (AA) including a first area (TEA, transparent emission area) and a second area (DEA, driving emission area) adjacent to the first area (TEA, transparent emission area); and
a display panel ([0006]) including a base layer (SUB, substrate) including a peripheral area (IA, non-display area, [0046]) adjacent to the display area (AA), an insulating layer (buffer film (not illustrated), [0085]) disposed on the base layer (SUB, substrate), and a first pixel (annotated Figure 5, TEP, transparent emission pixels) and a second pixel (annotated Figure 5, DEP, driving emission pixels) disposed on the base layer (SUB, substrate),
wherein the first pixel (annotated Figure 5, TEP, transparent emission pixels) comprises a first sub-pixel (annotated Figure 5, plurality of TEP, transparent emission pixels, [0115]) and a second sub-pixel (annotated Figure 5, plurality of TEP, transparent emission pixels, [0115]) that are different from each other,
wherein the first sub-pixel (annotated Figure 5, plurality of TEP, transparent emission pixels, [0115]) comprises a first sub-light emitting element (annotated Figure 5, ED, light emitting element) disposed in the first area (TEA, transparent emission area) and a first sub-pixel circuit electrically connected (annotated Figure 5, PCT, transparent emission pixel circuits) the first sub-light emitting element (annotated Figure 5, ED, light emitting element),
wherein the second sub-pixel (annotated Figure 5, plurality of TEP, transparent emission pixels, [0115]) comprises a second sub-light emitting element (annotated Figure 5, ED, light emitting element) disposed in the first area (TEA, transparent emission area) and a second sub-pixel circuit electrically connected (annotated Figure 5, PCT, transparent emission pixel circuits) to the second sub-light emitting element (annotated Figure 5, ED, light emitting element),
wherein the second pixel (annotated Figure 5, DEP, driving emission pixels) comprises a second light emitting element (annotated Figure 5, ED, light emitting element) disposed in the second area (DEA, driving emission area) and a second pixel circuit electrically connected (annotated Figure 5, PCD, driving emission pixel circuits) to the second light emitting element (annotated Figure 5, ED, light emitting element) and disposed in the second area (DEA, driving emission area),
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wherein the first sub-pixel circuit (annotated Figure 5, PCT, transparent emission pixel circuits) comprises:
a first silicon transistor (Figs. 2/4, DT2/ST2, second driving thin-film transistor/ second switching thin-film transistor, [0062], [0090]) including a first silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]) including a drain area (Fig. 4, DD2, second drain electrode), an active area (Fig. 4, DA2, second semiconductor layer), and a source area (Fig. 4, first DS2, second source electrode) and a first gate electrode (Fig. 4, DG2, first gate electrode) overlapping the active area (Fig. 4, DA2, first semiconductor layer) of the first silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]), and disposed in the second area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]);
a first oxide transistor (Fig. 2, ST2/DT2, second switching transistor/second driving thin-film transistor, [0062], [0090]) including a first oxide semiconductor pattern including a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern (see note below), and disposed in the second area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]); [Note: even though the reference does not disclose or suggest a drain area, an active area, a source area and a second gate area, however it is known in the art that the second switching transistor (ST2) or second driving transistor (DT2) as first oxide transistor will necessarily include a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern, [0062], [0090]).
wherein the second sub-pixel circuit (annotated Figure 5, PCT, transparent emission pixel circuits) comprises:
a second silicon transistor (Figs. 2/4, DT2/ST2, second driving thin-film transistor/ second switching thin-film transistor, [0062], [0090]) including a second silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]) including a drain area (Fig. 4, DD2, second drain electrode), an active area (Fig. 4, DA2, second semiconductor layer), and a source area (Fig. 4, first DS2, second source electrode) and a third gate electrode (Fig. 4, DG2, first gate electrode) overlapping the active area (Fig. 4, DA2, first semiconductor layer) of the second silicon semiconductor pattern (Fig. 3, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]), and disposed in the second area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]);
a second oxide transistor (Fig. 2, ST2/DT2, second switching thin-film transistor/ second driving thin-film transistor, [0062], [0090]) including a second oxide semiconductor pattern including a drain area, an active area, and a source area and a fourth gate electrode overlapping the active area of the second oxide semiconductor pattern (see note below), and disposed in the second area Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]); [Note: even though the reference does not disclose or suggest a drain area, an active area, a source area and a second gate area, however it is known in the art that the second switching transistor (ST2) or second driving transistor (DT2) as first oxide transistor will necessarily include a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern, [0062], [0090]).
LEED does not disclose explicitly a display device comprising: a first upper electrode overlapping the first gate electrode; and a second upper electrode overlapping the third gate electrode.
SUNG teaches in Figures 15-16, a display device (Fig. 1, 100, [104]) comprising:
a first upper electrode (Fig. 15, UE, [0210]) overlapping the first gate electrode (Fig. 15, GE1, [0210]); and
a second upper electrode (Fig. 15, UE, [0210]) overlapping the third gate electrode (Fig. 15, GE1, [0210]);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEED to incorporate the teachings of SUNG, such that a display device comprising: a first upper electrode overlapping the first gate electrode; and a second upper electrode overlapping the third gate electrode, The aforementioned arrangement of plurality of transistors in connection with contact electrodes, light emitting element thus facilitates as a sensor device for finger printing that can prevent the moiré effect that may occur in the photo-sending by adjusting the resolutions of a light transmitting hole array layer and a photo-sensor array layer that overlaps with the light transmitting hole layer (SUNG, [0278]).
LEED as modified by SUNG does not explicitly disclose a display device comprising: a first connection wiring electrically connecting the first silicon transistor or the first oxide transistor and the first sub-light emitting element, overlapping the first area, disposed on a same layer as the first upper electrode, and including a transparent conductive oxide, a second connection wiring electrically connecting the second silicon transistor or the second oxide transistor and the second sub-light emitting element, overlapping the first area, disposed on a layer different from the first connection wiring, and including a transparent conductive oxide.
CHO teaches a display device (Fig. 1, [0030]) comprising: a first connection wiring (Fig. 5, 185, connection electrodes) electrically connecting (Fig. 5, 63, connection hole) the first silicon transistor or the first oxide transistor (Fig. 5, T6) and the first sub-light emitting element (Fig. 5, OLED), overlapping the first area (Fig. 1, DA, display area), disposed on a same layer (Fig. 5, 118/119, first/second planarization layer) as the first upper electrode (Fig. 5, 183, supply voltage line), and including a transparent conductive oxide (the connection electrodes, may each include material having high conductivity, such as a metal or a conductive oxide, [0138]), a second connection wiring (Fig. 5, 173, connection electrodes) electrically connecting (Fig. 5, 34, contact hole) the second silicon transistor or the second oxide transistor (Fig. 5, T3) and the second sub-light emitting element (Fig. 5, OLED), overlapping the first area (Fig. 1, DA, display area), disposed on a layer (Fig. 5, 116, interlayer insulation layer) different from the first connection wiring (Fig. 5, 185, connection electrodes), and including a transparent conductive oxide (the connection electrodes, 173 may each include material having high conductivity, such as a metal or a conductive oxide, [0138]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG to incorporate the teachings of CHO, such that a first connection wiring electrically connecting the first silicon transistor or the first oxide transistor and the first sub-light emitting element, overlapping the first area, disposed on a same layer as the first upper electrode, and including a transparent conductive oxide, a second connection wiring electrically connecting the second silicon transistor or the second oxide transistor and the second sub-light emitting element, overlapping the first area, disposed on a layer different from the first connection wiring, and including a transparent conductive oxide, so that the above arrangements enables to accurately control light emission of the display element and luminescence level of the light emitted from the display element, the number of TFTs electrically connected to ne display element has increased (CHO, [0004]).
LEED as modified by SUNG and CHO does not explicitly disclose the display device, wherein the third pixel comprises a third light emitting element disposed in the third area and a third pixel circuit electrically connected to the third light emitting element, wherein a sum of numbers of first sub-light emitting elements and second sub-light emitting elements disposed per unit area of the first area is less than a number of third light emitting elements disposed per unit area of the third area, wherein a number of second light emitting elements disposed per unit area of the second area is less than a number of third light emitting elements disposed per unit area of the third area,.
CHANG teaches the display device (Fig. 7, displace device includes a housing, [0058]),
wherein the third pixel comprises a third light emitting element (Fig. 2, 21, sub-pixels) disposed in the third area (Fig. 2, 20, second display area) and a third pixel circuit (Fig. 3, 22, sub-pixels) electrically connected ([0028]) to the third light emitting element (Fig. 2, 21, sub-pixels),
wherein a sum of numbers of first sub-light emitting elements and second sub-light emitting elements disposed per unit area (Fig. 2, 11, sub-pixels) of the first area (Fig. 2, 10, first display area) is less than ([0044]) number of third light emitting elements (Fig. 2, 21, sub-pixels) disposed per unit area of the third area (Fig. 2, 20, second display area).
wherein a number of second light emitting elements disposed per unit area (Fig. 2, 31, sub-pixels) of the second area (Fig. 2, 30, third display area) is less than ([0044]) a number of third light emitting elements disposed per unit area (Fig. 2, 21, sub-pixels) of the third area (Fig. 2, 20, second display area),
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG and CHO to incorporate the teachings of CHANG, such that the display device, wherein a number of second light emitting elements disposed per unit area of the second area is less than a number of third light emitting elements disposed per unit area of the third area, wherein a sum of numbers of first sub-light emitting elements and the second sub-light emitting elements disposed per unit area of the first area is less than a number of third light emitting elements disposed per unit area of the third area. With this arrangement, a number of the pixel circuits, 32 corresponding to the sub-pixels, 31, in the third display area, 30 is small so there can be extra space in the third display are, 30 for arranging the pixel circuits, 12 corresponding to the sub-pixels, 11 in the first display area can be ensured to have a high definition (CHANG, [0045], [0051]).
Regarding Claim 12, LEED as modified by SUNG, CHO and CHANG teaches the display device of claim 11.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein the insulating layer ([0180]) comprises:
a lower insulating layer (Fig. 16B, INS1, first insulating layer, [0224]) under the first upper electrode (Fig. 16A, LE) and the second upper electrode (Fig. 16A, UE); and
an upper insulating layer (Figs. 16A/16B, INS2/INS3, second insulating layer/third insulating layer, [0224]) on the first upper electrode (Fig. 16A, LE) and the second upper electrode (Fig. 16A, UE); (NOTE: the circuit element layer, BPL may include a plurality of circuit elements each of which is formed in a corresponding one of the pixel areas, PXA to form a pixel circuit of the corresponding pixel PXL, [0109]).
Regarding Claim 13, LEED as modified by SUNG, CHO and CHANG teaches the display device of claim 12.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein the first (Fig. 16A, LE) and second upper electrodes (Fig. 16A, UE) and the first and second oxide semiconductor patterns (Figs. 16A/16B, ACT7/ACT3/ACT1) are disposed on a same layer on the lower insulating layer (Figs. 16A/16B, INS1/INS2/INS3, first insulating layer/second insulating layer/third insulating layer, [0224]),
wherein the first (Fig. 16A, LE) and second upper electrodes (Fig. 16A, UE) and the first and second oxide semiconductor patterns (Figs. 16A/16B, ACT7/ACT3/ACT1) are covered by the upper insulating layer (Figs. 16A/16B, INS2/INS3, second insulating layer/third insulating layer, [0224]).
Regarding Claim 14, LEED as modified by SUNG, CHO and CHANG teaches the display device of claim 12.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), further comprising a first insulating pattern (Figs. 16A/16B, INS1/INS2/INS3, first insulating layer/second insulating layer/third insulating layer, [0224]) disposed between the active area of the first oxide semiconductor pattern (Figs. 16A/16B, ACT7/ACT3/ACT1) and the second gate electrode (Figs. 16A/16B, GE7/GE1) and between the active area of the second oxide semiconductor pattern (Figs. 16A/16B, ACT7/ACT3/ACT1) and the fourth gate electrode (Figs. 16A/16B, GE7/GE1/GE4), and a second insulating pattern disposed between the lower insulating layer (Figs. 16A/16B, INS1/INS2/INS3, first insulating layer/second insulating layer/third insulating layer, [0224]) and the second connection wiring (Figs. 16A/16B, CNL, AUX, CH8/CH7/CH2/CH1).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEED, in view of SUNG, LEEH, CHANG, and RYU as applied to Claim(s) 1-10 above.
Regarding Claim 15, LEED as modified by SUNG, CHO and CHANG teaches the display device of claim 14.
LEED as modified by SUNG, LEEH and CHANG does not explicitly disclose the display device, wherein the first connection wiring, the second connection wiring, the first and second upper electrodes, and the first and second oxide semiconductor patterns each comprise at least one of In, Zn, and Sn.
RYU teaches the display device (Fig. 2, 10), wherein the first connection wiring (Fig. 20, Si-1/Si/Si+1, control lines, [0248]), the second connection wiring (Fig. 20, Si-1/Si/Si+1, control lines, [0248]), the first and second upper electrodes (Fig. 20, capacitor electrodes, [0248]), and the first and second oxide semiconductor patterns (Fig. 18, GE1-GE7, gate electrodes, [0248]) each comprise at least one of In, Zn, and Sn (Indium Tin Zinc Oxide (ITZO), ZnO/SnO2, Indium Zinc Oxide (IZO), [0248]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG, CHO and CHANG to incorporate the teachings of RYU, such that the display device, wherein the first connection wiring, the second connection wiring, the first and second upper electrodes, and the first and second oxide semiconductor patterns each comprise at least one of In, Zn, and Sn, so that the circuit components such as control lines, capacitor electrodes and semiconductor gate electrodes exhibit excellent electrical conductive properties for a photo-sensing display device (RYU, [0090-0091], [0248]).
Claim(s) 16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEED, in view of SUNG, LEEH as applied to Claim(s) 1-10 above, and further in view of Junhyun Park et al, (hereinafter PARK), US 20190319212 A1.
Regarding Claim 16, LEED teaches in Figure 5, an electronic device ([0163]) comprising:
a display device (EL display device, [0024]) including a sensing area configured to enable an optical signal to pass therethrough (SN, optical sensor, [0056]), a display area (AA) adjacent to the sensing area (SN, optical sensor, [0056]), and a peripheral area (IA, non-display area, [0046]) adjacent to the display area (AA), wherein the sensing area (SN, optical sensor, [0056]) comprises an element area (TEP, transmission emission pixel, [0056]) overlapped by a first light emitting element (ED, light emitting element in TEP, [0056]) including a first sub-light emitting element (annotated Figure 5, ED, light emitting element) and a second sub-light emitting element (annotated Figure 5, ED, light emitting element), and a transmissive area (TEA, transparent emission area, [0057]) non-overlapped (annotated Figure 5) by the first light emitting element (ED, light emitting element in TEP, [0056]); and
wherein the display device (EL display device, [0024]) comprises:
a first sub-light emitting element (annotated Figure 5, ED, light emitting element) disposed in the element area (TEA, transparent emission area, [0057]) and a first sub- pixel circuit electrically connected (annotated Figure 5, PCT, transparent emission pixel circuits) to the first sub-light emitting element (annotated Figure 5, ED, light emitting element); and
a second sub-light emitting element (annotated Figure 5, ED, light emitting element) disposed in the element area (TEA, transparent emission area, [0057]), and a second sub-pixel circuit electrically connected (annotated Figure 5, PCT, transparent emission pixel circuits) to the second sub-light emitting element (annotated Figure 5, ED, light emitting element),
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wherein the first sub-pixel circuit (annotated Figure 5, PCT, transparent emission pixel circuits) comprises:
a first transistor (Figs. 2/4, DT2/ST2, second driving thin-film transistor/ second switching thin-film transistor, [0062], [0090]) including a first silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]) including a drain area (Fig. 4, DD2, second drain electrode), an active area (Fig. 4, DA2, first semiconductor layer), and a source area (Fig. 4, first DS2, second source electrode) and a first gate electrode (Fig. 4, DG2, first gate electrode) overlapping the active area (Fig. 4, DA2, first semiconductor layer) of the first silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]) , and disposed in the display area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]);
a second transistor (Figs. 2/4, DT2/ST2, second driving thin-film transistor/ second switching thin-film transistor, [0062], [0090]) including a first oxide semiconductor pattern including a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern (see note below), and disposed in the display area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]); [Note: even though the reference does not disclose or suggest a drain area, an active area, a source area and a second gate area, however it is known in the art that the second switching transistor (ST2) or second driving transistor (DT2) as first oxide transistor will necessarily include a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern, [0062], [0090]).
wherein the second sub-pixel circuit (annotated Figure 5, PCT, transparent emission pixel circuits) comprises:
a third transistor (Figs. 2/4, DT2/ST2, second driving thin-film transistor/ second switching thin-film transistor, [0062], [0090]) including a second silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]) including a drain area (Fig. 4, DD2, second drain electrode), an active area (Fig. 4, DA2, first semiconductor layer), and a source area (Fig. 4, first DS2, second source electrode) and a third gate electrode (Fig. 4, DG2, first gate electrode) overlapping the active area (Fig. 4, DA2, first semiconductor layer) of the second silicon semiconductor pattern (Fig. 4, DA2, second semiconductor layer, a silicon-based semiconductor material, [0090]), and disposed in the display area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]);
a fourth transistor (Fig. 2, ST2/DT2, second switching thin-film transistor/ second driving thin-film transistor, [0062], [0090]) including a second oxide semiconductor pattern including a drain area, an active area, and a source area and a fourth gate electrode overlapping the active area of the second oxide semiconductor pattern (see note below), and disposed in the display area (Figs. 1-3, DEA, driving emission area) or the peripheral area (IA, non-display area, [0046]); [Note: even though the reference does not disclose or suggest a drain area, an active area, a source area and a second gate area, however it is known in the art that the second switching transistor (ST2) or second driving transistor (DT2) as first oxide transistor will necessarily include a drain area, an active area, and a source area and a second gate electrode overlapping the active area of the first oxide semiconductor pattern, [0062], [0090]).
LEED does not disclose explicitly a display device comprising: a first upper electrode overlapping the first gate electrode; and a second upper electrode overlapping the third gate electrode.
SUNG teaches in Figures 15-16, a display device (Fig. 1, 100, [104]) comprising:
a first upper electrode (Fig. 15, UE, [0210]) overlapping the first gate electrode (Fig. 15, GE1, [0210]); and
a second upper electrode (Fig. 15, UE, [0210]) overlapping the third gate electrode (Fig. 15, GE1, [0210]);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEED to incorporate the teachings of SUNG, such that a display device comprising: a first upper electrode overlapping the first gate electrode; and a second upper electrode overlapping the third gate electrode, The aforementioned arrangement of plurality of transistors in connection with contact electrodes, light emitting element thus facilitates as a sensor device for finger printing that can prevent the moiré effect that may occur in the photo-sending by adjusting the resolutions of a light transmitting hole array layer and a photo-sensor array layer that overlaps with the light transmitting hole layer (SUNG, [0278]).
LEED as modified by SUNG does not explicitly disclose a display device comprising: a first connection wiring electrically connecting the first silicon transistor or the first oxide transistor to the first sub-light emitting element, overlapping the first area, disposed on a top surface of a same layer as the first upper electrode, and including a transparent conductive oxide, each of the first connection wiring and the first upper electrode directly contacting the top surface of the same layer on which they are disposed; and a second connection wiring electrically connecting the second silicon transistor or the second oxide transistor to the second sub-light emitting element, overlapping the first area, disposed on a top surface of a same layer as the second oxide semiconductor pattern, and including a transparent conductive oxide, each of the second connection wiring and the second oxide semiconductor pattern directly contacting the top surface of the same layer on which they are disposed.
LEEH teaches a display device (Fig. 2, 10, display panel) comprising:
a first connection wiring (Fig. 7B, 1175R, first electrode layer) electrically connecting (Fig. 7B, 1163R, first contact hole) the first silicon transistor or the first oxide transistor (Fig. 7B, TFT1, driving thin film transistor) to the first sub-light emitting element (Fig. 7B, OLED1), overlapping the first area (Fig. 7B, PX1/PX2, first/second pixel), disposed on a top surface of a same layer (Figs. 7B, 115, interlayer insulating layer) as the first upper electrode (Figs. 7B, DL/PL, data line/driving voltage line), and including a transparent conductive oxide ([0101]), each of the first connection wiring (Fig. 7B, 1175R, first electrode layer) and the first upper electrode (Figs. 7B, DL/PL, data line/driving voltage line) directly contacting the top surface of the same layer (Figs. 7B, 115, interlayer insulating layer) on which they are disposed; and
a second connection wiring (Fig. 7B, 1175G, second electrode layer) electrically connecting (Fig. 7B, 1163G, second contact hole) the second silicon transistor or the second oxide transistor (Fig. 7B, TFT2, switching thin film transistor) to the second sub-light emitting element (Fig. 7B, OLED2), overlapping the first area (Fig. 7B, PX1/PX2, first/second pixel), disposed on a top surface of a same layer (Figs. 7B, 115, interlayer insulating layer) as the second oxide semiconductor pattern (Fig. 7B, 1175B, third electrode layer), and including a transparent conductive oxide ([0101]), each of the second connection wiring (Fig. 7B, 1175G, second electrode layer) and the second oxide semiconductor pattern (Fig. 7B, 1175B, third electrode layer) directly contacting the top surface of the same layer (Figs. 7B, 115, interlayer insulating layer) on which they are disposed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG to incorporate the teachings of LEEH, such that a display device comprising: a first connection wiring electrically connecting the first silicon transistor or the first oxide transistor to the first sub-light emitting element, overlapping the first area, disposed on a top surface of a same layer as the first upper electrode, and including a transparent conductive oxide, each of the first connection wiring and the first upper electrode directly contacting the top surface of the same layer on which they are disposed; and a second connection wiring electrically connecting the second silicon transistor or the second oxide transistor to the second sub-light emitting element, overlapping the first area, disposed on a top surface of a same layer as the second oxide semiconductor pattern, and including a transparent conductive oxide, each of the second connection wiring and the second oxide semiconductor pattern directly contacting the top surface of the same layer on which they are disposed, so that the display apparatuses has fabricated with various configurations to increase their display quality (LEEH, [0005]).
LEED as modified by SUNG and LEEH does not disclose an electronic device comprising: an electronic module disposed below the display device, overlapping the sensing area, and configured to receive the optical signal.
PARK teaches an electronic device (Fig. 2A, EA, electronic apparatus) comprising:
an electronic module (Fig. 2, 300) disposed below the display device (Fig. 2, 100, display panel), overlapping the sensing area (touch sensing unit, TSU (may be omitted in Fig. 2A), [0069]), and configured to receive the optical signal (TSU may sense an input, light, [0070]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEED as modified by SUNG and LEEH to incorporate the teachings of PARK, such that an electronic module disposed below the display device, overlapping the sensing area, and configured to receive the optical signal, so that to manufacture a display device having relatively lower power consumption, high brightness and high response speed characteristics (PARK, [0003]).
Regarding Claim 18, LEED as modified by SUNG and LEEH and PARK teaches the electronic device of claim 16.
SUNG further teaches in Figures 15-16, a display device (Fig. 1, 100, [104]), wherein an electrical conductivity (third conductive layer is formed of metal, [0238-0239]) of the second connection wiring (Fig. 16A, CNL, connection line) is greater than (connection line, CNL is formed of metal having electrical conductivity greater than the semiconductor patterns with gate electrodes and active layers formed of conductive polymers or conductive metal oxides) an electrical conductivity (first conductive layer formed of a conductive polymer or conductive metal oxide, [0223], [0273]) of the active area (ACT1 to ACT7, [0273]) of the first and second oxide semiconductor patterns (GE1 to GE7, [0273]).
LEED further teaches in Figure 5, the electronic device ([0163]), wherein the electronic module comprises a camera module (Fig. 5, CM, [0121]).
Regarding Claim 19, LEED as modified by SUNG and LEEH and PARK teaches the electronic device of claim 16.
SUNG further teaches in Figures 15-16, the electronic device (Fig. 1, 100, [104]), wherein an electrical conductivity (third conductive layer is formed of metal, [0238-0239]) of the second connection wiring (Fig. 16A, CNL, connection line) is greater than (connection line, CNL is formed of metal having electrical conductivity greater than the semiconductor patterns with gate electrodes and active layers formed of conductive polymers or conductive metal oxides) each electrical conductivity (first conductive layer formed of a conductive polymer or conductive metal oxide, [0223], [0273]) of the active area (ACT1 to ACT7, [0273]) of the first oxide semiconductor pattern and the active area of the second oxide semiconductor pattern (GE1 to GE7, [0273]).
Regarding Claim 20, LEED as modified by SUNG and LEEH and PARK teaches the electronic device of claim 16.
PARK further teaches the electronic device (Fig. 2A, EA, electronic apparatus), wherein the display device ([0003]) further comprises a window (Fig. 2A, 200, window member),
wherein the window (Fig. 2A, 200) comprises a base film (Fig. 2, glass substrate, a sapphire substrate or a plastic film, [0077]) and a bezel pattern (Fig. 2, BZA, bezel area) disposed on the base film (Fig. 2, glass substrate, a sapphire substrate or a plastic film, [0077]) and overlapping the peripheral area (Fig. 2, NDA).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEED, in view of SUNG, LEEH, PARK, MA, and CHANG as applied to Claim(s) 1-10 as above.
Regarding Claim 17, LEED as modified by SUNG and LEEH and PARK teaches the electronic device of claim 16.
LEED as modified by SUNG and LEEH and PARK does not explicitly disclosed the electronic device, wherein the display device comprises a display pixel including a second light emitting element disposed in the display area and a second pixel circuit electrically connected to the second light emitting element and disposed in the display area.
MA teaches the electronic device ([0087]), wherein the display device (Fig. 14, 2) comprises a display pixel (annotated Figures 2) including a second light emitting element (Fig. 2, EM1, first light-emitting units) disposed in the display area (Fig. 2, AA) and a second pixel circuit (Fig. 2, PD1, first pixel circuits) electrically connected (Fig. 3, [0054]) to the second light emitting element (Fig. 2, EM1, first light-emitting units) and disposed in the display area (Fig. 2, AA).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG and LEEH and PARK to incorporate the teachings of MA, such that the electronic device, wherein the display device comprises a display pixel including a second light emitting element disposed in the display area and a second pixel circuit electrically connected to the second light emitting element and disposed in the display area, so that the light transmittance of the display area, AA is increased (MA, [0076]).
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LEED as modified by SUNG, PARK and MA does not explicitly disclose the electronic device, wherein a sum of numbers of first sub-light emitting elements and second sub-light emitting elements per unit area disposed in the sensing area is less than a number of second light emitting elements disposed per unit area in the display area.
CHANG teaches the electronic device ([0022]), wherein a sum of numbers of first sub-light emitting elements and the second sub-light emitting elements per unit area (Fig. 2, 11, sub-pixels) disposed in the sensing area (Fig. 2, 10, first display area) is less than ([0044]) a number of second light emitting elements disposed per unit area (Fig. 2, 21, sub-pixels) in the display area (Fig. 2, 20, second display area).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LEED as modified by SUNG, PARK and MA to incorporate the teachings of CHANG, such that the electronic device, wherein a sum of numbers of first sub-light emitting elements and the second sub-light emitting elements per unit area disposed in the sensing area is less than a number of second light emitting elements disposed per unit area in the display area. With this arrangement, a number of the pixel circuits, 32 corresponding to the sub-pixels, 31, in the third display area, 30 is small so there can be extra space in the third display are, 30 for arranging the pixel circuits, 12 corresponding to the sub-pixels, 11 in the first display area can be ensured to have a high definition (CHANG, [0045], [0051]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210028272 A1 – Figure 6
STATEMENT OF RELEVANCE – A schematic cross-sectional view of a display device with the pad layer connecting the transistor and the OLED.
US 20190267440 A1 – Figure 12
STATEMENT OF RELEVANCE – The intermediate connection line, 155, connecting the OLED with the transistor, T1, disposed on top surface of the interlayer insulating layer, 115 and on the same surface as the electrodes (unlabeled).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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