DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 02/03/2026 amendments of claims 1-5, 9-10, 23-24, 27-30 and 32-33 have been noted and entered.
Response to Arguments
Applicant's arguments filed 02/03/2026 regarding the rejection of claims 1-11 and 23-33 under 35 U.S.C. 102 and 35 U.S.C. 103 have been fully considered but they are not persuasive in light of the newly added amendments. The amendments introduced to claims 1 and 23 contain unsupported limitations. Details of the new rejections are shared below.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: The specification of the incident application is missing the support for the claimed limitation which are cited in claims 1 and 23: “… and the horizontal connector coupled between the vertical connector and the first gate electrode without overlapping with the gate metal layer.” (emphasis added).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 23 and all their dependent claims (2-11 and 24-31) are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1; claim 1, in the last two lines of the claim, contains the limitations: “…, and the horizontal connector coupled between the vertical connector and the first gate electrode without overlapping with the gate metal layer.” (emphasis added). By examining the specification it is found that such language or any other similar language that might describe such a limitation is absent. Additionally, by examining Fig (1B) as a representative figure for the layout of the device, it appears that there is an overlap between the horizontal connector (Instant application: Fig (1B): 13c1) and the gate metal layer (G) along the horizontal direction identified as (+Y) in annotated copies of Fig (1B) of the instant application which are shared below to help clarify the examiner’s position.
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Regarding claim 23; claim 23, in the last three lines of the claim, contains the limitations: “…, and the horizontal connector coupled between the vertical connector and the first gate electrode without overlapping with the gate metal layer.” (emphasis added). By examining the specification it is found that such language or any other similar language that might describe such a limitation is absent. Additionally, by examining Fig (1B) as a representative figure for the layout of the device, it appears that there is an overlap between the horizontal connector (Instant application: Fig (1B): 13c1) and the gate metal layer (G) along the horizontal direction identified as (+Y) in annotated copies of Fig (1B) of the instant application which are shared above to help clarify the examiner’s position..
Allowable Subject Matter
Claims 1-11 and 23-31 are objected to for containing unsupported limitations, but would be allowable if rewritten in a form that overcomes the 35 U.S.C. 112(a) rejections detailed above.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1; Kikuchi in combination with other available art teaches a vertical semiconductor power device, comprising: a substrate, the substrate comprising: a first surface and a second surface opposite to each other, a doped region close to the second surface, and a first trench extending from the second surface toward the first surface; a first in-trench dielectric layer disposed along an inner surface of the first trench; a first shield electrode, disposed in the first trench and surrounded by the first in-trench dielectric layer; [[and]] a first gate electrode, disposed in the first in-trench dielectric layer and surrounding the first shield electrode, the first gate electrode being surrounded by the first in-trench dielectric layer without adjoining the first shield electrode and the substrate; a gate metal layer, disposed on and in contact with an interlayer dielectric layer that is on the second surface; and a gate electrode connector coupled between the gate metal layer and the first gate electrode, the gate electrode connector comprising a vertical connector and a first horizontal connector, the vertical connector coupled between the gate metal layer and the first horizontal connector.
However, Kikuchi alone or in combination with any other available art, does not teach the first horizontal connector coupled between the vertical connector and the first gate electrode without overlapping with the gate metal layer.
Claims 2-11 are objected to for their dependence on an objected to but otherwise allowable base claim 1.
Regarding claim 23; Kikuchi in combination with other available art teaches a vertical semiconductor power device, comprising: a substrate, comprising a first surface and a second surface opposite to the first surface; a first trench, extending from the second surface of the substrate into the substrate; a first in-trench dielectric layer, disposed along an inner surface of the first trench; a first shield electrode, disposed in the first trench and surrounded by the first in-trench dielectric layer; a first gate electrode, disposed in the first in-trench dielectric layer, surrounding the first shield electrode, and separated from the first shield electrode by the first in-trench dielectric layer; a doped region in the substrate and adjacent to the first trench and the second surface of the substrate; an interlayer dielectric layer disposed on the second surface; a gate metal layer, disposed on and in contact with the interlayer dielectric layer; and a gate electrode connector coupling the gate metal layer and the first gate electrode, the gate electrode connector comprising a vertical connector and a first horizontal connector, the vertical connector coupled between the gate metal layer and the first horizontal connector.
However, Kikuchi alone or in combination with any other available art does not teach the first horizontal connector coupled between the vertical connector and the first gate electrode without overlapping with the gate metal layer.
Claims 24-31 are objected to for their dependence on an objected to but otherwise allowable base claim 23.
Claims 32-33 are allowable over prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 32; Kikuchi in combination with other available art teaches a vertical semiconductor power device, comprising: a substrate, comprising a first surface and a second surface opposite to the first surface; a first trench, extending from the second surface of the substrate into the substrate; a first in-trench dielectric layer, disposed along an inner surface of the first trench; a first shield electrode, disposed in the first trench and surrounded by the first in-trench dielectric layer; a first gate electrode, disposed in the first in-trench dielectric layer, surrounding the first shield electrode, and separated from the first shield electrode by the first in-trench dielectric layer; a second trench, extending from the second surface of the substrate into the substrate and spaced apart from the first trench; a second in-trench dielectric layer, disposed along an inner surface of the second trench; a second shield electrode, disposed in the second trench and surrounded by the second in- trench dielectric layer; a second gate electrode, disposed in the second in-trench dielectric layer, surrounding the second shield electrode, and separated from the second shield electrode by the second in-trench dielectric layer; a doped region disposed in the substrate between the first trench and the second trench; a source region, disposed in the doped region between the first trench and the second trench; and an interlayer dielectric layer disposed on and covering the second surface of the substrate, the first trench and the second trench; a source metal layer on and in contact with the interlayer dielectric layer and covering the first trench and the second trench; a gate metal layer on and in contact with the interlayer dielectric layer without overlapping with the first trench and the second trench; and a gate electrode connector comprising a vertical connector, a first horizontal connector and a second horizontal connector, the vertical connector coupled between the gate metal layer and the first horizontal connector, the first horizontal connector coupled between the first gate electrode and the vertical connection.
However, Kikuchi alone or in combination with any other available art does not teach the second horizontal connector coupled between the first gate electrode and the second gate electrode without overlapping with the gate metal layer.
Claim 33 is allowable for its dependence on an allowable claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 21, 2026
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