DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Group II, Claims 17-36, in the reply filed on 11/06/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 25, lines 4-5, the recitation of “the semiconductor layer is formed on one of the first surface, the second surface, and the top electrode is formed over the semiconductor layer” is unclear because the top electrode is aslo recited as formed over the semiconductor layer.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17, 19-24, 34 and 36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh et al. (CN219269471U, see US 2023/0292526).
Regarding claim 17, Hsieh et al. discloses, as shown in Figures 17-18, a manufacturing method of a semiconductor device comprising:
forming a semiconductor structure (252), wherein the semiconductor structure comprises a ferroelectric layer (248), a semiconductor layer (240) and a top electrode (250), the ferroelectric layer has a first surface and a second surface opposite to the first surface, the semiconductor layer is formed on one of the first surface and the second surface, and the top electrode is formed over the semiconductor layer;
forming an oxide layer (262, [0032]-[0033], IMD has similar composition to ILD), to cover the semiconductor structure and the top electrode; and
forming a metal via (264) passing through the oxide layer to electrically connect the top electrode.
Regarding claim 19, Hsieh et al. discloses, in forming the semiconductor structure, the semiconductor structure further comprises a bottom electrode (236), and the semiconductor layer (240) is formed between the bottom electrode and the ferroelectric layer (248) (Figures 17-18).
Regarding claim 20, Hsieh et al. discloses, in forming the semiconductor structure, the semiconductor layer is in directly contact with the ferroelectric layer ([0065]).
Regarding claim 21, Hsieh et al. discloses, in forming the semiconductor structure, there is no interaction layer between the semiconductor layer and the ferroelectric layer ([0065]).
Regarding claim 22, Hsieh et al. discloses, in forming the semiconductor structure, the semiconductor layer has a thickness ranging between 2 (angstrom) Å and 300 Å ([0054], each of the thickness t1, t2 and t3 may be not larger than about 10 nm (or 100 Å)).
Regarding claim 23, Hsieh et al. discloses, in forming the semiconductor structure, the ferroelectric layer has a thickness ranging between 10 Å and 200 Å (less than 100 Å, [0019] [0057]).
Regarding claim 24, Hsieh et al. discloses, in forming the semiconductor structure, the semiconductor layer is formed of Ge, GeTe, GeSb, SiGe, a-Si, or ZGZO [0045].
Regarding claim 34, Hsieh et al. discloses, as shown in Figures 17-18, a manufacturing method of a semiconductor device comprising:
forming a semiconductor structure (252), wherein the semiconductor structure comprises a ferroelectric layer (248), a semiconductor layer (240) and a top electrode (250), the ferroelectric layer has a first surface and a second surface opposite to the first surface, the semiconductor layer is formed on one of the first surface and the second surface, and the top electrode is formed over the semiconductor layer;
forming a plurality oxide layer (262, [0032]-[0033], ILD has one or more multilayers, IMD has similar composition to ILD), to cover the semiconductor structure and the top electrode; and
forming a metal via (264) passing through the oxide layer to electrically connect the top electrode.
Regarding claim 36, Hsieh et al. discloses, in forming the semiconductor structure, the semiconductor structure further comprises a bottom electrode (236), and the semiconductor layer (240) is formed between the bottom electrode and the ferroelectric layer (248) (Figures 17-18).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18, 25-33 and 35, in compliance with 35 USC, 112, is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (CN219269471U, see US 2023/0292526) in view of Chen et al. (US 2023/0017020).
Regarding claim 25, Hsieh et al. discloses, as shown in Figures 17-18, a manufacturing method of a semiconductor device comprising:
forming a semiconductor structure (252), wherein the semiconductor structure comprises a ferroelectric layer (248), a semiconductor layer (240) and a top electrode (250), the ferroelectric layer has a first surface and a second surface opposite to the first surface, the semiconductor layer is formed on one of the first surface and the second surface, and the top electrode is formed over the semiconductor layer;
forming an oxide layer (262, [0032]-[0033], IMD has similar composition to ILD), to cover the semiconductor structure and the top electrode; and
forming a metal via (264) passing through the oxide layer to electrically connect the top electrode.
Hsieh et al. does not disclose the semiconductor layer has a width less than that of the ferroelectric layer. However, Chen et al. discloses a manufacturing method of a ferroelectric structure comprising an interfacial layer (104) and a top electrode (110) having the width that is equal or less than a width of the ferroelectric layer (106) depending on the circuit design. Note Figures 8A-10E. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the semiconductor layer of Hsieh et al. having a width less than that of the ferroelectric layer, such as taught by Chen et al. in order to have the desired structure.
Regarding claim 26, Hsieh et al. and Chen disclose, in forming the semiconductor structure, the top electrode (110) has a width less than that of the ferroelectric layer (106) (Figures 8A, 8D, and 10A-10C).
Regarding claims 18, 27 and 35, Hsieh et al. discloses, in forming the semiconductor structure, the semiconductor structure further comprises a bottom electrode (236), and the semiconductor layer (240) is formed between the bottom electrode and the ferroelectric layer (248). Hsieh et al. does not disclose the ferroelectric layer is formed between the bottom electrode and the semiconductor layer. However, Chen et al. discloses a manufacturing method of a ferroelectric structure comprising an interfacial layer (104, 104a, 104b) can be formed under or above the ferroelectric layer (106) depending on the circuit design. Note Figures 8A-10E. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the semiconductor layer of Hsieh et al. under or above the ferroelectric layer, such as taught by Chen et al. in order to have the desired structure.
Regarding claim 28, Hsieh et al. and Chen disclose, in forming the semiconductor structure, the semiconductor structure further comprises a bottom electrode (236), and the semiconductor layer (252) is formed between the bottom electrode and the ferroelectric layer (248) (Figures 17-18).
Regarding claim 29, Hsieh et al. and Chen disclose, in forming the semiconductor structure, the semiconductor layer is in directly contact with the ferroelectric layer ([0065]).
Regarding claim 30, Hsieh et al. and Chen disclose, in forming the semiconductor structure, there is no interaction layer between the semiconductor layer and the ferroelectric layer ([0065]).
Regarding claim 31, Hsieh et al. and Chen disclose, in forming the semiconductor structure, the semiconductor layer has a thickness ranging between 2 (angstrom) Å and 300 Å ([0054], each of the thickness t1, t2 and t3 may be not larger than about 10 nm (or 100 Å)).
Regarding claim 32, Hsieh et al. and Chen disclose, in forming the semiconductor structure, the ferroelectric layer has a thickness ranging between 10 Å and 200 Å (less than 100 Å, [0019] [0057]).
Regarding claim 33, Hsieh et al. and Chen disclose, in forming the semiconductor structure, the semiconductor layer is formed of Ge, GeTe, GeSb, SiGe, a-Si, or ZGZO [0045].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACOB CHOI can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUNG K VU/ Primary Examiner, Art Unit 2897