DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group 1 (claims 1-6 readable thereon, claims 7-10 withdrawn) in the reply filed on 1/14/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US PGPub 2016/0240465) in view of Lee et al. (US PGPub 2020/0185352; hereinafter “Lee”) and Chen et al. (US PGPub 2016/0240391; hereinafter “Chen2”).
Re claim 1: Chen teaches (e.g. figs. 1-13, and 15A) a method for manufacturing a packaging structure having an organic interposer layer, comprising: forming a rewiring layer (SiN 24, RDL 26, SiN 28; e.g. paragraphs 15, 16; hereinafter “RL”) over a carrier substrate (carrier 20; e.g. paragraph 14), wherein the rewiring layer (RL) comprises metal wiring layers (26) and inorganic dielectric layers (24, 28), each on top of one of the metal wiring layers (26), wherein the metal wiring layers (26) and the inorganic dielectric layers (24, 28) are formed in an alternating sequence on a surface of the carrier substrate (20); forming conductive pillars (32) over the rewiring layer (RL), wherein the conductive pillars (32) are electrically connected to the rewiring layer (RL); forming an organic dielectric layer (resin 44; e.g. paragraph 22) over the rewiring layer (RL), with the organic dielectric layer (44) covering (molding layer 44 is higher than the top ends of metal pillars 32; e.g. paragraph 22) the rewiring layer (RL) and the conductive pillars (32), and thinning (CMP of the molding layer to expose pillars 32; e.g. paragraph 23) the organic dielectric layer (44) and the conductive pillars (32), wherein the thinned organic dielectric layer (44) and the thinned conductive pillar (32) are flush (fig. 5 shows 44 and 32 having flush upper surfaces) with each other; forming solder bumps (connectors 60; e.g. paragraph 28) over the thinned organic dielectric layer (44) and the thinned conductive pillars (32), with the solder bumps (60) electrically connected to the conductive pillars (32); bonding a support substrate (carrier 62; e.g. paragraph 30) to the solder bumps (60) through an adhesive layer (adhesive 64; e.g. paragraph 30); removing the semiconductor substrate (20) to expose surfaces of the metal wiring layers (26) facing away from the organic dielectric layer (44); and forming bonding pads (70 of fig. 15A) on the exposed surfaces of the metal wiring layers (top surface of 26 shown in fig. 15A), with the bonding pads (70) being electrically connected to the metal wiring layers (26); and disengaging the support substrate (62) by removing the adhesive layer (64) to obtain an intermediate structure (between fig. 13 and 15A, the adhesive 64 is removed to expose solder balls 60).
Chen is silent as to explicitly teaching the carrier substrate is a semiconductor substrate; and connecting a cutting carrier to the bonding pads.
Lee teaches the carrier substrate (carrier substrate 102 is a silicon wafer; e.g. paragraph 23) is a semiconductor substrate.
Chen2 teaches (figs. 29-33) connecting (directly or indirectly) a cutting carrier (flipped over and attached to a tape 170; e.g. paragraph 56) to the bonding pads (70 of Chen).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the semiconductor carrier substrate as taught by Lee and to use the dicing tape as taught by Chen2 in the method of Chen in order to have the predictable result of using a known carrier which has matched coefficient of thermal expansion so delamination during processing is avoided and in order to have the predictable result of using a known method to reliably dice batch processed wafers, respectively.
Re claim 2: Chen in view of Chen2 teaches the method according to claim 1, wherein after disengaging the support substrate (62 of Chen as shown in fig. 13,14), the method further comprises cutting (184 of Chen2) the intermediate structure to obtain multiple pre-encapsulation structures.
Re claim 3: Chen in view of Lee and Chen2 teaches the method according to claim 1, further comprising: removing the cutting carrier (170 of Chen2 as shown in fig. 32,33), bonding functional chips (180 of Lee) to the bonding pads (70 of Chen), wherein the functional chips (200 of Chen) are electrically connected to the bonding pads (70 of Chen); forming a filler layer (chip bonding under chip 180 of Lee) at gaps between the functional chips (180 of Lee) and the bonding pads (182 of Lee); and forming an encapsulation layer (185 of Lee) over the bonding pads (182 of Lee), covering the functional chips (180 of Lee).
Re claim 4: Chen teaches the method according to claim 1, wherein before bonding the solder bumps (60) to the support substrate (62), the method further comprises: forming a protective layer (56) covering the solder bumps (60).
Re claim 5: Chen teaches the method according to claim 1,wherein forming the solder bumps (60) over the thinned organic dielectric layer (44) and the thinned conductive pillars (32) comprises: forming a polymer layer (polymer dielectric 46; e.g. paragraph 24) over the thinned organic dielectric layer (44), and forming openings (48) in the polymer layer (46), wherein the openings (48) at least partially expose the conductive pillars (32); forming a sub-bump metal layer (50) in the openings (48) over the conductive pillars (32); and forming the solder bumps (60) over the sub-bump metal layer (50), wherein the solder bumps (60) extend beyond the polymer layer (46).
Re claim 6: Chen teaches the method according to claim 1. wherein the rewiring layer (RL) comprises two or more (Examiner takes official notice that depending on the fan-out required, more than two metal layers would have been obvious) metal wiring layers (26) and two or more inorganic dielectric layers (24, 28), and wherein each of the wiring (26) and each of the inorganic dielectric layers (24, 28) is patterned.
Conclusion
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898