Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-12) in the reply filed on 12/23/2025 is acknowledged.
Claims 1-12 are elected for examination and claims 13-20 are withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US Pub. No. 2022/0271256 A1), hereafter referred to as Han, in view of Cho et al. (US Pub. No. 2019/0164998 A1), hereafter referred to as Cho.
As to claim 1, Han discloses a display device (fig 1, display device 1) comprising
a display panel (fig 1, 1) including a display area (DA) including a first area (MDA/DPA) and a second area (CA) having a higher transmittance than a transmittance of the first area ([0058]),
wherein the display panel includes:
a base layer (100) overlapping the display area (DA) and a non-display area (peripheral area);
a pixel (Pm) disposed on the base layer (100) in the display area (DA);
an inorganic layer (111; [0142]) overlapping the display area (DA) and the non-display area (peripheral area);
a plurality of insulating layers (112 and 115) arranged on the inorganic layer (111); and
an insulating pattern (insulating pattern of the insulating layer 113) overlapping the second area (CA) and disposed between the plurality of insulating layers (112 and 115),
a first groove is defined in the plurality of insulating layers, the insulating pattern, and a portion of the inorganic layer in the second area (fig 7, groove in 111, 112,113,115 in area CA).
Han does not disclose a non-display area including a third area which is bendable and adjacent to the display area, and a second groove is defined in the plurality of insulating layers and the inorganic layer in the third area.
Nonetheless, Cho discloses a display panel (fig 1A, DP) including a non-display area (NBA/BA) including a third area (BA) which is bendable and adjacent to a display area (fig 1A, DA), and a second groove is defined in a plurality of insulating layers and an inorganic layer in the third area (fig 4A, BA including CA with groove GV-1/GV-2 in insulating layers 10-40 and inorganic layer BRL/BFL [0075]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a bending area with groove in a non-display area of Han as taught by Cho since this allows for signal pads to be folded to a back side of the display panel.
As to claim 2, Han in view of Cho disclose the display device of claim 1 (paragraphs above).
Han further discloses wherein the first groove exposes the inorganic layer (fig 7, layer 111 is exposed in groove of region CA).
As to claim 3, Han in view of Cho disclose the display device of claim 1 (paragraphs above).
Cho further discloses wherein the second groove exposes an upper surface of a base layer (fig 4A, BL).
As to claim 4, Han in view of Cho disclose the display device of claim 1 (paragraphs above).
Han further discloses wherein the plurality of insulating layers entirely overlap the second area (112/115 second area), and
the insulating pattern overlaps only a portion of the second area (insulating pattern is only portion of 113 with the inclined surface and no other part of insulating layer 113 is considered to be the insulating pattern).
As to claim 5, Han in view of Cho disclose the display device of claim 1 (paragraphs above).
Han further discloses wherein the insulating pattern surrounds the first groove in a plan view (insulating pattern of 111 surrounds the groove shown in fig 7).
As to claim 6, Han in view of Cho disclose the display device of claim 1 (paragraphs above).
Han further discloses wherein the second area (fig 5A) includes:
a transmissive area (CA) corresponding to the first groove (groove formed in layers 111-115); and
a light emission area (Pa) adjacent to the transmissive area (CA).
As to claim 7, Han in view of Cho disclose the display device of claim 6 (paragraphs above).
Han further discloses wherein the pixel (Pm) includes: a light emission element (OLED) disposed in the first area (MDA) and the light emission area of the second area (OLED’ in CA); and
a transistor (TFT’) disposed in the first area (MDA/DPA).
As to claim 8, Han in view of Cho disclose the display device of claim 7 (paragraphs above).
Han further discloses wherein the light emission element disposed in the light emission area is electrically connected to the transistor disposed in the first area (OLED’ connected to transistor TFT’ in MDA/DPA).
As to claim 9, Han in view of Cho disclose the display device of claim 1 (paragraphs above).
Han further discloses a groove organic pattern (organic pattern 116 in groove shown in fig 7; [0134]) disposed to cover an inner surface of a portion of the plurality of insulating layers defining an upper portion of the first groove (116 on inner surface of layers 112 and 115) and to cover an inner surface of the insulating pattern (113) defining the upper portion of the first groove (shown in fig 7).
As to claim 10, Han in view of Cho disclose the display device of claim 1 (paragraphs above).
Han further discloses a groove organic pattern (organic pattern 116 in groove shown in fig 7; [0134]) disposed to cover an inner surface of each of the plurality of insulating layers (112/115), the insulating pattern (113) and the portion of the inorganic layer (111) defining the first groove (fig 7).
As to claim 11, Han in view of Cho disclose the display device of claim 7 (paragraphs above).
Han further discloses wherein the transistor includes a first transistor (TFT) and a second transistor (TFT’),
the first transistor includes:
a first semiconductor pattern including a first drain area (D1), a first active area (A1), and a first source area (S1); and
a first gate (CE1) overlapping the first active area (A1), and
the second transistor includes:
a second semiconductor pattern including a second drain area (left side of channel region of TFT’), a second active area (channel area), and a second source area (right side of the channel area);
a second gate (CE1’) overlapping the second active area (channel area); and
a gate insulating pattern (112) disposed between the second active area (channel area) and the second gate (CE1’).
As to claim 12, Han in view of Cho disclose the display device of claim 11 (paragraphs above).
Han further discloses wherein the gate insulating pattern includes a same material as a material of the insulating pattern ([0146]-[0148]; additionally, see Cho, layers BRL/BFL).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2022/0181400 A1 and US Pub. No. 2021/0359266 A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 1/9/2026