DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10, 11 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2020/0263309 to Tanaka et al.
Regarding Claim 1, Tanaka et al. teaches a semiconductor processing method comprising: providing a fluorine-containing precursor and a hydrogen-containing precursor (Paragraphs 26, 29 and 65) to a processing region (Fig 5) of a semiconductor processing chamber (1), wherein a substrate (W) is housed in the processing region, and wherein a layer of a silicon-containing material (Paragraph 25) is disposed on the substrate; forming plasma effluents (Paragraphs 4, 12, 23, 28-32, 65-70 and 75) of the fluorine-containing precursor and the hydrogen-containing precursor; and contacting the substrate with the plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor, wherein the contacting etches a feature in the layer of silicon-containing material, and wherein a substrate support pedestal temperature is maintained (Paragraphs 28 and 31-56) at less than or about -20 °C during the semiconductor processing method.
Regarding Claim 2, Tanaka et al. teaches (Paragraphs 26, 29 and 65) the fluorine-containing precursor comprises nitrogen trifluoride (NF₃), carbon tetrafluoride (CF4), hexafluorobutadiene (C4F6), or fluoromethane (CH₃F).
Regarding Claim 3, Tanaka et al. teaches (Paragraphs 26, 29 and 65) the hydrogen-containing precursor comprises diatomic hydrogen (H₂).
Regarding Claim 4, Tanaka et al. teaches (Paragraphs 4, 12, 25, 42) the silicon-containing material comprises silicon oxide.
Regarding Claim 5, Tanaka et al. teaches (Paragraphs 62, 65) the plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor forms a hydrogen fluoride (HF)-containing plasma.
Regarding Claim 6, Tanaka et al. teaches (Paragraph 46) the plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor are formed at a plasma power of greater than or about 750 W.
Regarding Claim 7, Tanaka et al. teaches (Paragraphs 30, 41, 56 and 57) applying a bias power while contacting the substrate with the plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor.
Regarding Claim 8, Tanaka et al. teaches (Paragraphs 30, 41, 56 and 57) the bias power is greater than or about 1,500 W.
Regarding Claim 10, Tanaka et al. teaches (Paragraphs 18, 25 and 27) the feature in the layer of oxygen-containing material is characterized by an aspect ratio of greater than or about 5:1.
Regarding Claim 11, Tanaka et al. teaches (Paragraphs 28, 31 and 61) the substrate support pedestal temperature is less than or about -60 °C.
Regarding Claim 18, Tanaka et al. teaches semiconductor processing method comprising: providing etchant precursors to a processing region (Fig 5) of a semiconductor processing chamber (1), wherein a substrate (W) is housed in the processing region, and wherein a layer of a silicon-containing material is disposed on the substrate (Paragraph 25); forming plasma effluents of the etchant precursors (Paragraphs 4, 12, 23, 28-32, 65-70 and 75), wherein the plasma effluents comprise a hydrogen fluoride (HF)-containing plasma (Paragraphs 62, 65); and contacting the substrate with the hydrogen fluoride (HF)-containing plasma, wherein the contacting etches a feature in the layer of silicon-containing material, and wherein a substrate support pedestal temperature is maintained (Paragraphs 28 and 31-56) at less than or about -40 °C during the semiconductor processing method.
Regarding Claim 19, Tanaka et al. teaches (Paragraphs 26, 29 and 65) the etchant precursors comprise one or more of nitrogen trifluoride (NF₃), carbon tetrafluoride (CF4), hexafluorobutadiene (C4F6), and fluoromethane (CH₃F).
Regarding Claim 20, Tanaka et al. teaches (Paragraphs 30, 41, 56 and 57) applying a bias power while contacting the substrate with the plasma effluents of the etchant precursors, wherein the bias power is greater than or about 1,250 W.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication 2020/0263309 to Tanaka et al.
Regarding Claims 9 and 13, as applied above to Claim 1, Tanaka et al. teaches the method of the invention substantially as claimed, but does not expressly teach the feature in the layer of oxygen-containing material is characterized by a critical dimension of less than or about 30 nm. However, Tanaka et al. teaches (Paragraph 25) high aspect ratio etching for memory devices such as 3D-NAND or DRAM. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform etching such that the feature in the layer of oxygen-containing material is characterized by a critical dimension of less than or about 30 nm in order to form a reduced dimension memory device with predictable results.
Regarding Claim 12, Tanaka et al. teaches the method of the invention substantially as claimed, but does not expressly teach the contacting etches the feature in the layer of oxygen-containing material at an etch rate of greater than or about 100 nm/min. However, Tanaka et al. teaches the etching rate may be optimized with control of result effective variables such as temperature (Figure 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to an etch rate of greater than or about 100 nm/min with predictable results. Further since the material, etching chemistry and process conditions are the same in Tanaka et al. and the Claimed invention, the same etching rate would reasonably be expected to be achieved or else is the result of essential limitations which have not been claimed.
Regarding Claim 14, Tanaka et al. teaches (Paragraphs 62, 65) the plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor forms a hydrogen fluoride (HF)-containing plasma.
Regarding Claim 15, Tanaka et al. teaches (Paragraph 25) the layer of the silicon-and-oxygen-containing material is a layer in a DRAM structure.
Regarding Claim 16, Tanaka et al. teaches (Paragraphs 28 and 31-56) a substrate support pedestal temperature is between about -100 °C about -20 °C.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over US Publication 2020/0263309 to Tanaka et al. in view of US Publication 2018/0182777 to Cui et al.
Regarding Claim 17, Tanaka et al. teaches the method of the invention substantially as claimed, but does not expressly teach a semiconductor processing chamber operating pressure is less than or about 2 Torr. However, pressures about 2 Torr are known in the art to be suitable for plasma etching high aspect ratio features. For example, Cui et al. teaches (Paragraphs 16 and 39) a semiconductor processing chamber operating pressure is less than or about 2 Torr for etching NAND flash memory features in semiconductor dielectric using a fluorine containing chemistry. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a semiconductor processing chamber operating pressure is less than or about 2 Torr with predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Publication 2017/0358460 to Tomura et al. teaches an etching process method is provided that includes outputting a first high frequency power of a first frequency from a first high frequency power supply, and outputting a second high frequency power of a second frequency, which is lower than the first high frequency, from a second high frequency power supply in an cryogenic temperature environment where a substrate temperature is controlled to be less than or equal to −35° C.; generating a plasma by adding a hydrocarbon gas containing at least 3 carbon atoms to an etching gas containing carbon, hydrogen, and fluorine; and etching a silicon oxide film or a laminated film made up of laminated layers of silicon-containing films having different compositions using the generated plasma.
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/ROBERTS P CULBERT/Primary Examiner, Art Unit 1716