DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 08/22/2023.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 08/22/2023. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1- 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Murashige et al. (US 2023/0130571)
Regarding claim 1, Murashige discloses a display device comprising:
a base layer 10 or 12 (see fig. 5);
a first insulation layer 30 or 22 or 10 disposed on the base layer 10/12;
a line layer 32 (comprising wires 32sl, 32se, 32ce, 32de, etc.) disposed on the first insulation layer 30, wherein the line layer 32 comprises at least one selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) (see para. 0062), and a line hole (between wires 32sl, 32se, 32ce, 32de, etc., in which portion of layer 34 is formed) is defined in the line layer 32;
a second insulation layer 34, 36 and/or 40 disposed on the line layer 32, wherein a line contact hole 36h/38h is defined in the second insulation layer 34/36/40;
a valley electrode 62fe disposed on the second insulation layer 34/36/40 and electrically connected with the line layer 32 (32de) through the line contact hole 36h/38h;
a third insulation layer 64/64ec disposed on the valley electrode 62fe, wherein a valley hole (in which sub-pixel Sp is located) is defined in the third insulation layer 64/64ec; and
an organic layer 66 disposed on the third insulation layer 64/64ec,
wherein the line hole is defined through at least a portion of the line layer 32, and
at least a portion of the organic layer 66 is disposed in the valley hole to contact the valley electrode 62fe.
Regarding claim 2, Murashige discloses the display device of claim 1, wherein the valley hole (in which sub-pixel Sp is located) overlaps the valley electrode 62fe on a plane. See fig. 5.
Regarding claim 3, Murashige discloses the display device of claim 1, wherein the line hole (between wires 32sl, 32se, 32ce, 32de, etc., in which portion of layer 34 is formed) is spaced apart from the line contact hole 36h/38h on a plane. See fig. 5.
Regarding claim 4, Murashige discloses the display device of claim 1, wherein at least a portion of the first insulation layer, the second insulation layer 34, and the third insulation layer is disposed in the line hole. See fig. 5.
Regarding claim 5, Murashige discloses the display device of claim 1, wherein the line hole is provided in plurality (between wires 32sl, 32se, 32ce, 32de, etc., in which portion of layer 34 is formed). See fig. 5.
Regarding claim 6, Murashige discloses the display device of claim 5, wherein the valley hole (in which sub-pixel Sp is located) extends in a first horizontal direction, and a plurality of line holes is symmetric in a second horizontal direction crossing the first horizontal direction with respect to the valley electrode. See fig. 5.
Regarding claim 7, Murashige discloses the display device of claim 1, wherein the line hole overlaps the valley electrode on a plane. See fig. 5.
Regarding claim 8, Murashige discloses the display device of claim 1, wherein the line hole is spaced apart from the valley electrode on a plane. See fig. 5.
Regarding claim 9, Murashige discloses the display device of claim 8, wherein the valley hole (in which sub-pixel Sp is located) extends in a first horizontal direction, and a distance from the valley electrode 62fe to the line hole in the first horizontal direction is less than a width of the valley electrode 62fe in the first horizontal direction on a plane. See fig. 5.
Regarding claim 10, Murashige discloses the display device of claim 1, wherein a first insulation hole 30h is defined in the first insulation layer 30, and the first insulation hole 30h is defined to correspond to the line hole on a plane. See fig. 5.
Regarding claim 11, Murashige discloses the display device of claim 1, wherein a second insulation hole 36h is defined in the second insulation layer 34/36, and the second insulation hole is defined to correspond to the line hole on a plane. See fig. 5.
Regarding claim 12, Murashige discloses the display device of claim 1, wherein each of the first insulation layer 30, the second insulation layer 34/36/40, and the third insulation layer 64 comprises at least one selected from an aluminum oxide, a titanium oxide, a silicon oxide, a silicon nitride, a silicon oxynitride, a zirconium oxide, and a hafnium oxide. See paras. 0060-0067.
Regarding claim 13, Murashige discloses the display device of claim 1, further comprising:
a plurality of lower insulation layers 26, 22, 10 disposed below the first insulation layer 30, wherein the plurality of lower insulation layers comprises a first lower insulation layer 26, a second lower insulation layer 22, and a third lower insulation layer 110, which are sequentially laminated on the base layer 12. See fig. 5. See also para. 0060, where the insulation layer 30 is described of monolayer or multilayer insulating layer. Should the insulating layer being of multilayer, the top layer may be considered as the claimed first insulating layer, and the lower layers are lower insulation layers sequentially laminated on the base layer 12.
Regarding claim 14, Murashige discloses the display device of claim 13, wherein a lower insulation hole 30h is defined in the third lower insulation layer (third lower layer in multilayer insulating layer 30; see para. 0060), and the line hole is defined to correspond to the lower insulation hole on a plane. See fig. 5.
Regarding claim 15, Murashige discloses the display device of claim 13, further comprising:
a first transistor (comprising semiconductor layer 24) disposed on the first lower insulation layer, wherein the first transistor comprises a silicon semiconductor pattern 24. See fig. 5.
Regarding claim 16, Murashige discloses the display device of claim 1, further comprising:
a second transistor (comprising semiconductor layer 24) disposed on the first insulation layer 22 or 10, wherein the second transistor comprises an oxide semiconductor pattern 24. See para. 0056.
Regarding claim 17, Murashige discloses the display device of claim 16, wherein the second transistor further comprises an oxide gate 28eg, and the oxide gate 28ge is disposed on the second insulation layer 26. See fig. 5.
Regarding claim 18, Murashige discloses the display device of claim 17, wherein a material included in the oxide gate 28eg is the same as a material included in the valley electrode 62fe. See paras. 0058-0060, 0084-0085.
Regarding claim 19, Murashige discloses the display device of claim 16, wherein the oxide semiconductor pattern comprises at least one selected from an indium-tin oxide (ITO), an indium- gallium-zinc oxide (IGZO), an zinc oxide (ZnO), an indium-zinc oxide (IZnO), a zinc- indium oxide (ZIO), an indium oxide (InO), a titanium oxide (TiO), an indium-zinc- tin oxide (IZTO), and a zinc-tin oxide (ZTO). See para. 0056.
Regarding claim 20, Murashige discloses a display device comprising:
a base layer 12 (see fig. 56);
a plurality of insulation layers 30, 34, 36, 40, 64 disposed on the base layer 12; and
a line layer 32 (comprising wires 32sl, 32se, 32ce, 32de, etc.) disposed between the plurality of insulation layers, wherein a line hole (between wires 32sl, 32se, 32ce, 32de, etc., in which portion of layer 34 is formed) is defined in the line layer, wherein the line layer 32 comprises at least one selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) (see para. 0062), the line hole is defined by an inner surface of the line layer 32, and a portion an insulation layer 34 among the plurality of insulation layers 30, 34, 36, 40, 64 is disposed in the line hole.
Conclusion
7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 October 15, 2025