DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. US 2021/0249415 A1 in view of Schloesser et al. US 2005/0001257 A1.
Regarding claims 1-6, Kang discloses:
A memory cell array (Figs. 16 and 18), comprising:
a plurality of memory levels stacked in a first direction (Fig. 16), each of the plurality of memory levels comprising:
an active region (115);
a cell transistor (120) above the active region in the first direction; and
a cell capacitor (180) having a bottom electrode layer (186) that is electrically connected to the active region.
Schloesser discloses a publication from a similar endeavor in which:
a cell transistor (52) having a single gate above the active region (3) in the first direction (Fig. 9).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a single gate architecture as shown by Schloesser within the similar DRAM memory device of Kang to perform the same function of controlling the memory cell within a stacked 3D memory structure.
(claim 2) Kang: para 0087; word lines at same row.
(claim 3) Kang: para 0087; active regions separated by insulators.
(claim 4) Kang: para 0138; polysilicon.
(claim 5) Schloesser: para 0067; epitaxially grown.
(claim 6) Kang: para 0086; vertical bit lines.
Allowable Subject Matter
Claims 7-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to teach or clearly suggest the limitations of claim 7 stating “
depositing a stacking mold comprising a plurality of unit stacks, each unit stack comprising a thicker channel layer, a thicker sacrificial layer over the thicker channel layer, a thinner channel layer over the thicker sacrificial layer, and a thinner sacrificial layer over the thinner channel layer stacked in a first direction; partially filling the first recesses and fully filling with the second recesses with a first insulator layer from the sidewalls of the transistor slit; and removing the first insulator layer on the sidewalls of the transistor slit and within the first recesses”; and of claim 13 stating “
depositing a stacking mold comprising a plurality of unit stacks, each unit stack comprising a thicker channel layer, a thicker sacrificial layer over the thicker channel layer, a thinner channel layer over the thicker sacrificial layer, and a thinner sacrificial layer over the thinner channel layer stacked in a first direction; forming first openings in the thicker sacrificial layers and second openings in thinner sacrificial layers from sidewalls of the capacitor slits; partially filling the first openings and fully filling the second openings with a spacer layer from the sidewalls of the capacitor slits; and removing the spacer layer on the sidewalls of the capacitor slits and within the first openings”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
I. Kim et al. US 2013/0099304 A1: shows sacrificial layers 22 (Figs. 2B/2C para 0044) having the same thickness between gate regions in the stacked structure.
II. Yoo et al. US 2013/0234234 A1: shows sacrificial layers 14 (Figs. 6/7 para 0036) having the same thickness between gate regions in the stacked structure.
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/ERROL V FERNANDES/Primary Examiner, AU 2893