Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/23/2023 and 07/17/2024 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 9-11, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”).
Regarding Claim 1. Ziadeh discloses A structure (#100, Figure 1 upper panel, Legacy package) comprising:
a photonics chip (#104, Figure 1 upper panel, die which is a photonics chip based [0030] indicating the system may be an optical package and [0016]-[0017] describing the connection of optical fibers);
a packaging substrate (#102, Figure 1 upper panel, substrate as part of legacy package);
a plurality of electrical connections (#106, Figure 1 upper panel, ball grid array which electrically couples #102 to #104 according to [0029]) disposed in a gap between the photonics chip and the packaging substrate (Figure 1 upper panel, #106s are disposed in a gap between #102 and #104); and
a first fillet (#112, Figure 1 upper panel, fillet) comprising an underfill material (#108, Figure 1 upper panel, epoxy interpreted as an underfill material according to [0016]), the first fillet disposed to overlap with a first portion of the photonics chip adjacent to the gap (Figure 1 upper panel, #112 overlaps with a portion of #104 along the dashed line #105),
the first fillet having a first width dimension (Figure 1 upper panel, #112 has a width in the left-right direction) and a first height dimension transverse to the first width dimension (Figure 1 upper panel, #112 has a height in the up-down direction transverse to the left-right direction), wherein a ratio of the first width dimension to the first height dimension is greater than or equal to 1.5 (Figure 1 upper panel, #112 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #112; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of greater than 1.5).
Regarding Claim 9. Ziadeh discloses The structure of claim 1 wherein the packaging substrate has a surface (Figure 1 upper panel, upper surface of #102), the photonics chip has a side surface (Figure 1 upper panel, side surface of #104 along the edge #105), and the first portion of the photonics chip is a first portion of the side surface that is adjacent to the surface of the packaging substrate (Figure 1 upper panel, #112 is overlapping a portion of the side surface of #104 along the edge #105 adjacent to the top surface of #102).
Regarding Claim 10. Ziadeh discloses The structure of claim 9 wherein the first width dimension of the first fillet extends in a first direction perpendicular to the side surface (Figure 1 upper panel, the width of #112 extends perpendicular to the side surface of #104 along the edge #105), and the first height dimension of the first fillet extends in a second direction parallel to the side surface (Figure 1 upper panel, the height of #112 extends parallel to the side surface of #104 along the edge #105).
Regarding Claim 11. Ziadeh discloses The structure of claim 9 wherein the surface of the packaging substrate includes a second portion disposed in the gap between the photonics chip and the packaging substrate (Figure 1 upper panel, #102’s top surface includes a portion to the left of #105 which is disposed in the gap between #102 and #104).
Regarding Claim 20. Ziadeh discloses A method ([0029]-[0030], #100, Figure 1 upper panel, Legacy package) comprising:
attaching ([0029], “attaching a die to a substrate”) a photonics chip (#104, Figure 1 upper panel, die which is a photonics chip based [0030] indicating the system may be an optical package and [0016]-[0017] describing the connection of optical fibers) to a packaging substrate (#102, Figure 1 upper panel, substrate as part of legacy package) by a plurality of electrical connections, wherein the plurality of electrical connections (#106, Figure 1 upper panel, ball grid array which electrically couples #102 to #104 according to [0029]) are disposed in a gap between the photonics chip and the packaging substrate (Figure 1 upper panel, #106s are disposed in a gap between #102 and #104); and
forming a fillet (#112, Figure 1 upper panel, fillet) comprising an underfill material (#108, Figure 1 upper panel, epoxy interpreted as an underfill material according to [0016]; formed during the application of the epoxy through an epoxy low process described in [0030]), wherein the fillet is disposed to overlap with a portion of the photonics chip adjacent to the gap (Figure 1 upper panel, #112 overlaps with a portion of #104 along the dashed line #105), the fillet has a width dimension (Figure 1 upper panel, #112 has a width in the left-right direction) and a height dimension transverse to the width dimension (Figure 1 upper panel, #112 has a height in the up-down direction transverse to the left-right direction), and a ratio of the width dimension to the height dimension is greater than or equal to 1.5 (Figure 1 upper panel, #112 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #112; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of greater than 1.5).
Claim(s) 1-5 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”).
Regarding Claim 1. Ziadeh discloses A structure (#150, Figure 1 lower panel, Legacy package) comprising:
a photonics chip (#154, Figure 1 lower panel, die which is a photonics chip based on the inclusion of coupled optical fibers, see [0031], and [0033] indicating the system may be a photonics package);
a packaging substrate (#152, Figure 1 lower panel, substrate as part of legacy package);
a plurality of electrical connections (#156, Figure 1 lower panel, ball grid array which electrically couples #152 to #154 according to [0031]) disposed in a gap between the photonics chip and the packaging substrate (Figure 1 lower panel, #156s are disposed in a gap between #152 and #154); and
a first fillet (#162, Figure 1 lower panel, fillet) comprising an underfill material (#158, Figure 1 lower panel, epoxy interpreted as an underfill material according to [0016]), the first fillet disposed to overlap with a first portion of the photonics chip adjacent to the gap (Figure 1 lower panel, #162 overlaps with a portion of #154 to the left of dashed line #153),
the first fillet having a first width dimension (Figure 1 lower panel, #162 has a width in the left-right direction) and a first height dimension transverse to the first width dimension (Figure 1 lower panel, #162 has a height in the up-down direction transverse to the left-right direction), wherein a ratio of the first width dimension to the first height dimension is greater than or equal to 1.5 (Figure 1 lower panel, #162 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #162; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of greater than 1.5).
Regarding Claim 2. Ziadeh discloses The structure of claim 1 wherein the ratio of the first width dimension to the first height dimension is less than or equal to 50 (Figure 1 lower panel, #162 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #162; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of less than 50).
Regarding Claim 3. Ziadeh discloses The structure of claim 1 wherein the packaging substrate has an edge (#153, Figure 1 lower panel, edge of #152), the photonics chip has a top surface (Figure 1 lower panel, bottom surface of #154 may be a top surface when viewed upside down), and the first portion of the photonics chip is a first portion of the top surface that is adjacent to the edge of the packaging substrate (Figure 1 lower panel, the portion of #154 which #162 is overlapping is a first portion of the bottom surface of #154 adjacent to the edge #153 of #152).
Regarding Claim 4. Ziadeh discloses The structure of claim 3 wherein the packaging substrate has a second height dimension at the edge (Figure 1 lower panel, vertical thickness of #152), the first portion of the top surface has a second width dimension (Figure 1 lower panel, left-right length of #154 to the right of #153), the first height dimension of the first fillet is less than the second height dimension (Figure 1 lower panel, all heights, in the up-down direction, of #162 are less than the thickness of #152), and the first width dimension of the first fillet is less than the second width dimension (Figure 1 lower panel, all widths, in the left-right direction, of #162 are less than the width of #154 which extends past #153).
Regarding Claim 5. Ziadeh discloses The structure of claim 3 wherein the first width dimension of the first fillet extends in a first direction parallel to the top surface (Figure 1 lower panel, the width of #162 extends in a left-right direction parallel to the bottom surface of #154), and the first height dimension of the first fillet extends in a second direction perpendicular to the top surface (Figure 1 lower panel, the height of #162 extends in an up-down direction perpendicular to the bottom surface of #154).
Regarding Claim 8. Ziadeh discloses The structure of claim 3 wherein the top surface of the photonics chip includes a second portion disposed in the gap between the photonics chip and the packaging substrate (Figure 1 lower panel, #154s bottom surface includes a portion to the left of #153 which is disposed in the gap between #154 and #152).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) as applied to claims 1-5 and 8 above.
Regarding Claim 13. Ziadeh discloses The structure of claim 1 (#150, Figure 1 lower panel, Legacy package).
Ziadeh does not discloses the structure further comprising: a second fillet comprising the underfill material, the second fillet disposed to overlap with a second portion of the photonics chip, the second fillet having a second width dimension and a second height dimension transverse to the second width dimension, and a ratio of the second width dimension to the second height dimension is greater than or equal to 1.5 in the embodiment provided in the lower panel of Figure 1.
However, Ziadeh further teaches an alternative structure embodiment (#100, Figure 1 upper panel, Legacy package) wherein the epoxy underfill material (#108) will spread to all four sides of the die (#104) such that fillets may be present on all four sides (see [0030]). The upper panel of Figure 1 comprises:
a second fillet (#112, Figure 1 upper panel, fillet) comprising the underfill material (#108, Figure 1, epoxy interpreted as an underfill material according to [0016]), the second fillet disposed to overlap with a second portion of the photonics chip (Figure 1 upper panel, #112 overlaps with a portion of #104 along the dashed line #105), the second fillet having a second width dimension (Figure 1 upper panel, #112 has a width in the left-right direction) and a second height dimension transverse to the second width dimension (Figure 1 upper panel, #112 has a height in the up-down direction transverse to the left-right direction), and a ratio of the second width dimension to the second height dimension is greater than or equal to 1.5 (Figure 1 upper panel, #112 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #112; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of greater than 1.5).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the two embodiments disclosed adjacent to each other in the prior art reference, Ziadeh, as doing so does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009). Furthermore, Ziadeh teaches that these fillets may vary in size and shape depending on the orientation of the package in [0033]. Incorporating the feature of a second fillet with a different structure and overlap pattern from the embodiment of the upper panel of Figure 1 into the embodiment of the lower panel of Figure 1 would “increase the surface area of the bond and provide structural adhesive in bracing for a die” as taught by Ziadeh in [0016].
Regarding Claim 14. Ziadeh discloses The structure of claim 13 wherein the packaging substrate has an edge (#153, Figure 1 lower panel, edge of #152), the photonics chip has a top surface (Figure 1 lower panel, bottom surface of #154 may be a top surface when viewed upside down), and the first portion of the photonics chip is a first portion of the top surface that is adjacent to the edge of the packaging substrate (Figure 1 lower panel, the portion of #154 which #162 is overlapping is a first portion of the bottom surface of #154 adjacent to the edge #153 of #152).
Regarding Claim 15. Ziadeh discloses The structure of claim 14 wherein the packaging substrate has a surface (Figure 1 upper panel, upper surface of #102), the photonics chip has a side surface (Figure 1 upper panel, side surface of #104 along the edge #105), and the second portion of the photonics chip is a portion of the side surface that is adjacent to the surface of the packaging substrate (Figure 1 upper panel, #112 is overlapping a portion of the side surface of #104 along the edge #105 adjacent to the top surface of #102).
Regarding Claim 16. Ziadeh discloses The structure of claim 14 wherein the first fillet is different from the second fillet ([0029]-[0033], Figure 1 upper and lower panels, the fillets #112 and #162 are different in their size, orientation, and functionality).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) as applied to claims 1-5 and 8 above, and further in view of “Effect of adhesive fillet geometry on bond strength between microelectronic components and composite circuit boards”; Akbari et al.; 04/2016; (“Akbari”).
Regarding Claim 6. Ziadeh discloses The structure of claim 5.
Ziadeh does not disclose that the first fillet extends in the second direction along the edge of the packaging substrate in the lower panel of Figure 1. However, Ziadeh teaches that these fillets may vary in size and shape depending on the manufacturing processes utilized (see [0033]) and that larger fillets are beneficial in their ability to increase bond surface area and provide bracing for the dies (see [0016]).
Akbari teaches the formation of a fillet which may extend up the side surface of a silicon substrate and along the side surface of an underlying PCB (see Figures 2 and 3). Akbari further teaches that the fillet structure and its extension to cover areas of the neighboring substrates may vary from no coverage of the overlying substrate (see Figure 13b of Akbari which is similar to the lower panel of Figure 1 of Ziadeh) to extensive coverage of the edge overlying substrate (see Figure 13d of Akbari) with a larger fillet resulting in lower stress (see page 6, right column, paragraph 2) and the strength of underlying solder joints increases significantly with the formation of a larger fillet (see abstract).
Therefore, the claim limitation of “the first fillet extends in the second direction along the edge of the packaging substrate” is interpreted by the examiner to be a routine optimization (see MPEP 2144.05.II). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider optimizing the fillet to form a larger fillet structure in the lower panel of Figure 1 of Ziadeh such that the fillet may extend in the second direction (up-down direction) along the edge of the packaging substrate (#153) as doing so would result in a larger fillet which optimizes strength of the underlying solder joints and reduces stress on the system allowing it to handle an increased failure load (see page 6, right column, paragraph 2 and abstract of Akbari).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) in view of “Effect of adhesive fillet geometry on bond strength between microelectronic components and composite circuit boards”; Akbari et al.; 04/2016; (“Akbari”) as applied to claim 6 above, and further in view of US 2022/0342150 A1; Karhade et al.; 10/2022; (“Karhade”).
Regarding Claim 7. Ziadeh in view of Akbari disclose The structure of claim 6 wherein the packaging substrate has a surface that adjoins the gap (Ziadeh, Figure 1 lower panel, #152 has an upper surface that adjoins the gap between #152 and #154).
Ziadeh in view of Akbari do not disclose the structure further comprising: a solder mask layer on the surface of the packaging substrate, wherein the first fillet extends above the solder mask layer.
However, Karhade teaches a structure (Figure 2) comprising a photonic integrated circuit chip (#102, PIC) coupled to a packaging substrate (#124, package support) with an underfill material (#132) filling a gap between the die and the substrate and surrounding electrical interconnects (#126), wherein the structure further comprises a solder mask layer (#134, solder resist) on the upper surface of the packaging substrate (#124).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the solder resist layer from Karhade in the device of Ziadeh in view of Akbari, wherein the underfill material extends down the side of the packaging substrate for the reasons detailed above in the rejection of claim 6 of forming a larger fillet, such that the first fillet extends above the solder mask layer, since the formation of the solder mask layer “prevents solder from melting and bridging adjacent contacts during solder reflow” (see [0069] of Karhade).
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) as applied to claims 1, 9-11, and 20 above, and further in view of US 2021/0066148 A1; Kim et al.; 03/2021; (“Kim”).
Regarding Claim 17. Ziadeh discloses The structure of claim 1
Ziadeh does not disclose the structure further comprising: a lid including a first portion that adjoins the photonics chip and a second portion that adjoins the packaging substrate.
Kim teaches a structure (#10, Figures 1A-1C, semiconductor package) comprising a semiconductor chip (#200, Figure 1B) coupled to a packaging substrate (#100, Figure 1B) by a plurality of electrical connections (#210, Figure 1B, connection terminals) and an underfill material (#230, Figure 1B, side encapsulation material including an underfill material according to [0092]) with triangular fillets disposed to overlap with an edge of the chip and an upper surface of the package substrate (Figure 1B), the structure further comprising a lid (#250, Figure 1B, heat sink) including a first portion that adjoins the chip (Figure 1B, central portion of #250 which is overlapping with #200) and a second portion that adjoins the packaging substrate (Figure 1B, thicker side portions which are directly adjoined to #100).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing lid/heat sink structure in Ziadeh, as was done in Kim, in order to act as a passive heat exchanger to optimize the temperature of the chip (see [0065] of Kim) and provide high thermal transfer efficiency and endurance to the package (see [0066] of Kim).
Regarding Claim 18. Ziadeh in view of Kim discloses The structure of claim 17 wherein the lid includes a third portion between the first portion and the second portion (Kim, Figure 1B, portion of #250 which connects the portion overlapping #200 to the thicker edge portion connected directly to #100), the third portion of the lid is spaced from the packaging substrate to define an open space, and the first fillet is disposed in the open space (Kim, Figure 1B, the connecting portion of #250 is spaced apart from #100 to define an open space in which a fillet of the underfill material #230 is located).
Regarding Claim 19. Ziadeh in view of Kim discloses The structure of claim 17 wherein the packaging substrate has an edge (Kim, Figure 1B, left and right edges of #100 in the x-direction), the photonics chip has a top surface (Kim, Figure 1B, bottom surface of #200 in the negative z-direction) and a bottom surface opposite to the top surface (Kim, Figure 1B, top surface of #200 in the positive z-direction), the first portion of the photonics chip is a first portion of the top surface of the photonics chip that is adjacent to the edge of the packaging substrate (Kim, Figure 1B, the portion of #200 which the fillet of #230 overlaps includes a portion of the bottom surface of #200 adjacent to the gap where the electrical connections #210 are located and adjacent to the edge of #100, noting here that “adjacent” does not require a particular separation distance), and the first portion of the of the lid is adjoined to the bottom surface of the photonics chip (Kim, Figure 1B, the central portion of #250 which is overlapping with #200 is indirectly adjoined to the top surface of #200 by thermal interface material #240).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) as applied to claims 1, 9-11, and 20 above, and further in view of US 2021/0066148 A1; Kim et al.; 03/2021; (“Kim”) and Effect of Underfill Fillet Height on Packaging Reliability in Flip Chip; Zhao et al.; 09/2022; (“Zhao”).
Regarding Claim 12. Ziadeh discloses The structure of claim 9.
Ziadeh does not disclose that the photonics chip comprises a substrate and a back-end-of-line stack on the substrate, and the first fillet is coextensive with the substrate over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns.
Kim teaches a structure (#10, Figures 1A-1C, semiconductor package) comprising a semiconductor chip (#200, Figure 1B) coupled to a packaging substrate (#100, Figure 1B) by a plurality of electrical connections (#210, Figure 1B, connection terminals) and an underfill material (#230, Figure 1B, side encapsulation material including an underfill material according to [0092]) with triangular fillets disposed to overlap with an edge of the chip and an upper surface of the package substrate (Figure 1B), wherein the chip (#200) comprises a substrate and a back-end-of-line stack on the substrate ([0084], “front side of the wafer W before the singulation of the semiconductor chips 200, and a back-end-of-line (BEOL) process including metallization for connecting the circuit devices of the semiconductor chips 200 to the connection terminals 210”, i.e. the base wafer diced into chips is the substrate and a BEOL stack is provided on top prior to singulation).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing a substrate and a BEOL stack as the chip/die in Ziadeh, as was done in Kim, in order to provide metallization structures for connection from the substrate, to the electrical connections in the gap, and finally to the package substrate (see [0084] and Figure 1B of Kim)
Ziadeh does not disclose that the first fillet is coextensive with the substrate over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns. However, Ziadeh teaches that these fillets may vary in size and shape depending on the manufacturing processes utilized (see [0033]) and that larger fillets are beneficial in their ability to increase bond surface area and provide bracing for the dies (see [0016]). Kim teaches in [0059] and Figure 1C that the fillet should have a height (#FH) which is at least 50% of the chip height (#CH) in order to ensure “the semiconductor chip 200 may be supported on the package substrate 100 with sufficient mechanical strength”.
Zhao teaches that the height of an underfill fillet on the overlying chip has extensive influence on the reliability of the package (see title). As can be observed in Figures 4, 5, and 6, the height/geometry of the fillet relative to the chip will have extensive influence on the stresses experienced by the package (see abstract, Figures 4-6, and conclusion). In particular, the following observations are made by Zhao:
The Tensile, Mises and Compressive stress on the edge solder balls increases with increasing fillet height percentages (Figure 4).
The Mises and Compressive stress on the chip edge also increases with increasing fillet height percentages but the Tensile stress decreases (Figure 5).
The Mises and Tensile stress on the top point of the fillet is maximized in the 50% range of the fillet height while Mises and Tensile stress at the bottom fillet point increases with increasing fillet height percentages (Figure 6).
The Mises and Tensile stress on the top point of the chip is maximized in the 100% range of the fillet height (Figure 7).
Therefore, the claim limitation of “the first fillet is coextensive with the substrate over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns” is interpreted by the examiner to be a routine optimization (see MPEP 2144.05.II) depending on the thickness of the photonics chip and permissible stresses on the package. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider optimizing the height of the first fillet in Ziadeh in view of Kim such that the fillet may be coextensive with the substrate over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns depending on the size of the chip as the overlap is well understood in view of both Kim and Zhao as extensively influencing the balancing of stresses experienced by the chip, fillet, and solder connections in the package (see abstract, Figures 4-7, and conclusion of Zhao; see [0059] of Kim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0298953 A1; Talebbeydokhti et al.; 09/2023 – Figure 2B discloses a die (#114-1) connected to a packaging substrate (#102) by a plurality of electrical connections (#120) and an underfill material (#160) which forms fillets on either side of the die and overlapping both the die and the package substrate.
US 2017/0288780 A1; Yim et al.; 10/2017 – Figure 3 discloses a die (#108) connected to a packaging substrate (#102) by a plurality of electrical connections (#210 and #302) and an underfill material (#303) which forms fillets overlapping both the die and the package substrate.
US 2014/0183760 A1; Liu et al.; 07/2014 – Figures 4A and 4B disclose a die (#404) connected to a packaging substrate (#402) by a plurality of electrical connections (#406) and an underfill material (#408) which forms fillets overlapping both the die and the package substrate. The reference further details how the shape/dimensions of the fillets (a-e in Figure 4A) may influence the resulting structures functionality ([0029]-[0032]).
US 2021/0057477 A1; Takagi et al.; 02/2021 – Figures 1 and 2 disclose a die (#20) connected to a packaging substrate (#11) by a plurality of electrical connections (#2) and an underfill material (#4) which forms fillets overlapping both the die and the package substrate. The reference further details how the shape/dimensions of the fillets (W1/W2 in Figure 1 and H1/H2 in Figure 2) may influence the resulting structures functionality ([0041]).
Impact of underfill fillet geometry on interfacial delamination in organic flip chip packages; Kacker et al.; 07/2006 – Provides extensive details about the optimization of underfill and fillet geometry (Figures 1 and 4) for the purposes of controlling stresses on the device (Figures 3 and 5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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/TYLER J WIEGAND/Examiner, Art Unit 2812