DETAILED ACTION
This action is responsive to the amendment received on 04/21/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 24 and 25 is/are objected to because of the following informalities where proposed corrections are bolded and underlined:
Claim 24 and 25, lines 1-2 of both claims, “coextensive with [[the]] a substrate of the photonics chip” as this is the first recitation in either line of claims of a substrate as part of the photonics chip.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 18, 19, 21, 22, and 28 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the second fillet is disposed in the open space" in lines 3-4 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 18 depends on claim 17 which in turn depends on claim 1. In this line of claims, there has been no previous recitation of a second fillet such that it is unclear if this is intended to be the first recitation of the second fillet and should be read as “a second fillet is disposed in the open space” or if this is intended to refer to the previously recited first fillet and should be read as "the [[second]] first fillet is disposed in the open space". Therefore, claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention and claim 19 is rejected at least for its dependence on claim 18. For the purposes of this examination, claim 18 will be interpreted to read as "the [[second]] first fillet is disposed in the open space".
Claims 21 and 22 are recited as dependent on claim 10 in the current amendment filed on 04/21/2026. However, in the same amendment, claim 10 has been cancelled. Thus claims 21 and 22 are indefinite as it is unclear what claim they are intended to be dependent on. Therefore, claims 21 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It appears that both claims 21 and 22 provide further details related to the lid structure which was first recited in claim 17. Therefore, for the purposes of this examination, claims 21 and 22 will be interpreted as dependent on claim 17.
Claim 28 recites the limitation “wherein the first fillet is larger than the first fillet” which is indefinite. It is unclear how a structure can be larger or smaller than itself. Therefore, claim 28 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, claim 28 will be interpreted to read as " wherein the [[first]] second fillet is larger than the first fillet ".
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 8, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”). An annotated version of the lower panel of Figure 1 is provided below and referenced in the following rejections.
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Regarding Claim 1. Ziadeh discloses A structure (#150, Figure 1 lower panel annotated, Legacy package which is interpreted here in the upside down view) comprising:
a photonics chip (#154, Figure 1 lower panel, die which is a photonics chip based [0031] indicating the system may be an optical package and [0016]-[0017] describing the connection of optical fibers) having a top surface (#TS, Figure 1 lower panel annotated, #154 has a top surface #TS which faces #152);
a packaging substrate (#152, Figure 1 lower panel, substrate as part of legacy package) having an edge (Figure 1 lower panel annotated, #152 has an edge of the structure #EDGE);
a plurality of electrical connections (#156, Figure 1 lower panel, ball grid array which electrically couples #152 to #154 according to [0031]) disposed in a gap between the photonics chip and the packaging substrate (Figure 1 lower panel, #156s are disposed in a gap between #152 and #154); and
a first fillet (#162, Figure 1 lower panel, fillet) comprising an underfill material (#158, Figure 1 lower panel, epoxy interpreted as an underfill material according to [0016]), the first fillet disposed to overlap with a first portion of the top surface of the photonics chip adjacent to the gap (Figure 1 lower panel annotated, #162 overlaps with a portion of #TS of #154 to the right of #153 and adjacent to the gap) and extending along the edge of the packaging substrate (Figure 1 lower panel annotated, #162 extends along the edge region of #152),
the first fillet having a width dimension (Figure 1 lower panel, #162 has a width in the left-right direction) extending parallel to the top surface of the photonics chip (Figure 1 lower panel annotated, the left-right widths of #162 extend parallel to #TS of #154) and a height dimension extending perpendicular to the top surface of the photonics chip (Figure 1 lower panel annotated, #162 has a height in the up-down direction which extends perpendicular to #TS of #154),
wherein a ratio of the width dimension of the first fillet to the height dimension of the first fillet is greater than or equal to 1.5 (Figure 1 lower panel, #162 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #162; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of greater than 1.5).
Regarding Claim 2. Ziadeh discloses The structure of claim 1 wherein the ratio of the width dimension of the first fillet to the height dimension of the first fillet is less than or equal to 50 (Figure 1 lower panel, #162 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #162; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of less than 50).
Regarding Claim 4. Ziadeh discloses The structure of claim 1 wherein the packaging substrate has a height dimension at the edge (Figure 1 lower panel, vertical thickness of #152), the first portion of the top surface has a width dimension (Figure 1 lower panel, left-right length of #154 to the right of #153), the height dimension of the first fillet is less than the height dimension of the packaging substrate (Figure 1 lower panel, all heights, in the up-down direction, of #162 are less than the thickness of #152), and the width dimension of the first fillet is less than the width dimension of the first portion of the photonics chip (Figure 1 lower panel, all widths, in the left-right direction, of #162 are less than the width of #154 which extends past #153).
Regarding Claim 8. Ziadeh discloses The structure of claim 1 wherein the top surface of the photonics chip includes a second portion disposed in the gap between the photonics chip and the packaging substrate (Figure 1 lower panel, #154s bottom surface includes a portion to the left of #153 which is disposed in the gap between #154 and #152).
Regarding Claim 20. Ziadeh discloses A method ([0029]-[0033], #150, Figure 1 lower panel annotated, Legacy package which is interpreted here in the upside down view) comprising:
attaching ([0029], “attaching a die to a substrate”) a photonics chip (#154, Figure 1 lower panel, die which is a photonics chip based [0031] indicating the system may be an optical package and [0016]-[0017] describing the connection of optical fibers) to a packaging substrate (#152, Figure 1 lower panel, substrate as part of legacy package) by a plurality of electrical connections, wherein the plurality of electrical connections (#156, Figure 1 lower panel, ball grid array which electrically couples #152 to #154 according to [0031]) are disposed in a gap between the photonics chip and the packaging substrate (Figure 1 lower panel, #156s are disposed in a gap between #152 and #154), the photonics chip has a top surface (#TS, Figure 1 lower panel annotated, #154 has a top surface #TS which faces #152), and the packaging substrate has an edge (Figure 1 lower panel annotated, #152 has an edge of the structure #EDGE); and
forming a fillet (#162, Figure 1 lower panel, fillet) comprising an underfill material (#158, Figure 1 lower panel, epoxy interpreted as an underfill material according to [0016]; formed during the application of the epoxy through an epoxy flow process described in [0032]), wherein the fillet is disposed to overlap with a portion of the top surface of the photonics chip adjacent to the gap (Figure 1 lower panel annotated, #162 overlaps with a portion of #TS of #154 to the right of #153 and adjacent to the gap), and extend along the edge of the packaging substrate (Figure 1 lower panel annotated, #162 extends along the edge region of #152),
the fillet has a width dimension (Figure 1 lower panel, #162 has a width in the left-right direction) extending parallel to the top surface of the photonics chip (Figure 1 lower panel annotated, the left-right widths of #162 extend parallel to #TS of #154) and a height dimension extending perpendicular to the top surface of the photonics chip (Figure 1 lower panel annotated, #162 has a height in the up-down direction which extends perpendicular to #TS of #154), and
a ratio of the width dimension to the height dimension is greater than or equal to 1.5 (Figure 1 lower panel, #162 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #162; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of greater than 1.5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”), as applied to claim 4 above, in view of US 2022/0342150 A1; Karhade et al.; 10/2022; (“Karhade”) and further in view of “Effect of adhesive fillet geometry on bond strength between microelectronic components and composite circuit boards”; Akbari et al.; 04/2016; (“Akbari”).
Regarding Claim 7. Ziadeh discloses The structure of claim 4 wherein the packaging substrate has a surface that adjoins the gap (Ziadeh, Figure 1 lower panel, #152 has an upper surface that adjoins the gap between #152 and #154).
Ziadeh does not disclose the structure further comprising: a solder mask layer on the surface of the packaging substrate, wherein the first fillet extends above the solder mask layer.
However, Karhade teaches a structure (Figure 2) comprising a photonic integrated circuit chip (#102, PIC) coupled to a packaging substrate (#124, package support) with an underfill material (#132) filling a gap between the die and the substrate and surrounding electrical interconnects (#126), wherein the structure further comprises a solder mask layer (#134, solder resist) on the upper surface of the packaging substrate (#124).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the solder resist layer from Karhade in the device of Ziadeh, since the formation of the solder mask layer “prevents solder from melting and bridging adjacent contacts during solder reflow” (see [0069] of Karhade).
Ziadeh in view of Karhade do not disclose the structure wherein the first fillet extends above the solder mask layer.
Akbari teaches the formation of a fillet which may extend up the side surface of a silicon substrate and along the side surface of an underlying PCB (see Figures 2 and 3). Akbari further teaches that the fillet structure and its extension to cover areas of the neighboring substrates may vary from no coverage of the overlying substrate (see Figure 13b of Akbari which is similar to the lower panel of Figure 1 of Ziadeh) to extensive coverage of the edge overlying substrate (see Figure 13d of Akbari) with a larger fillet resulting in lower stress (see page 6, right column, paragraph 2) and the strength of underlying solder joints increases significantly with the formation of a larger fillet (see abstract).
Therefore, the claim limitation of “the first fillet extends above the solder mask layer” is interpreted by the examiner to be a routine optimization (see MPEP 2144.05.II). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider optimizing the fillet to form a larger fillet structure in the lower panel of Figure 1 of Ziadeh such that the fillet may extend in the second direction (up-down direction) along the edge of the packaging substrate (#153), such that the first fillet extends above the solder mask layer, as doing so would result in a larger fillet which optimizes strength of the underlying solder joints and reduces stress on the system allowing it to handle an increased failure load (see page 6, right column, paragraph 2 and abstract of Akbari).
Regarding Claim 29. Ziadeh discloses The structure of claim 1 wherein the packaging substrate has a surface that adjoins the gap (Ziadeh, Figure 1 lower panel, #152 has an upper surface that adjoins the gap between #152 and #154).
Ziadeh does not disclose the structure further comprising: a solder mask layer on the surface of the packaging substrate, wherein the first fillet extends above the solder mask layer.
However, Karhade teaches a structure (Figure 2) comprising a photonic integrated circuit chip (#102, PIC) coupled to a packaging substrate (#124, package support) with an underfill material (#132) filling a gap between the die and the substrate and surrounding electrical interconnects (#126), wherein the structure further comprises a solder mask layer (#134, solder resist) on the upper surface of the packaging substrate (#124).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the solder resist layer from Karhade in the device of Ziadeh, since the formation of the solder mask layer “prevents solder from melting and bridging adjacent contacts during solder reflow” (see [0069] of Karhade).
Ziadeh in view of Karhade do not disclose the structure wherein the first fillet extends above the solder mask layer.
Akbari teaches the formation of a fillet which may extend up the side surface of a silicon substrate and along the side surface of an underlying PCB (see Figures 2 and 3). Akbari further teaches that the fillet structure and its extension to cover areas of the neighboring substrates may vary from no coverage of the overlying substrate (see Figure 13b of Akbari which is similar to the lower panel of Figure 1 of Ziadeh) to extensive coverage of the edge overlying substrate (see Figure 13d of Akbari) with a larger fillet resulting in lower stress (see page 6, right column, paragraph 2) and the strength of underlying solder joints increases significantly with the formation of a larger fillet (see abstract).
Therefore, the claim limitation of “the first fillet extends above the solder mask layer” is interpreted by the examiner to be a routine optimization (see MPEP 2144.05.II). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider optimizing the fillet to form a larger fillet structure in the lower panel of Figure 1 of Ziadeh such that the fillet may extend in the second direction (up-down direction) along the edge of the packaging substrate (#153), such that the first fillet extends above the solder mask layer, as doing so would result in a larger fillet which optimizes strength of the underlying solder joints and reduces stress on the system allowing it to handle an increased failure load (see page 6, right column, paragraph 2 and abstract of Akbari).
Claim(s) 13, 16, 23, and 26-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) as applied to claim 1 above.
Regarding Claim 13. Ziadeh discloses The structure of claim 1 (#150, Figure 1 lower panel, Legacy package), wherein the packaging substrate has a surface and the photonics chip has a side surface (Figure 1 lower panel, #152 has an upper surface and #154 has a side surface).
Ziadeh does not disclose, in the embodiment provided in the lower panel of Figure 1, the structure further comprising: a second fillet comprising the underfill material, the second fillet disposed to overlap with a portion of the side surface of the photonics chip that is adjacent to the surface of the packaging substrate, the second fillet having a width dimension extending in a direction perpendicular to the side surface of the photonics chip and a height dimension extending parallel to the side surface of the photonics chip, and a ratio of the width dimension of the second fillet to the height dimension of the second fillet is greater than or equal to 1.5.
However, Ziadeh further teaches an alternative structure embodiment (#100, Figure 1 upper panel, Legacy package) wherein the epoxy underfill material (#108) will spread to all four sides of the die (#104) such that fillets may be present on all four sides (see [0030]). The upper panel of Figure 1 comprises:
a second fillet (#112, Figure 1 upper panel, fillet) comprising the underfill material (#108, Figure 1, epoxy interpreted as an underfill material according to [0016]), the second fillet disposed to overlap with a portion of the side surface of the photonics chip that is adjacent to the surface of the packaging substrate (Figure 1 upper panel, #112 overlaps with a portion of the side surface of #104 along the dashed line #105 adjacent to the upper surface of #102), the second fillet having a width dimension extending in a direction perpendicular to the side surface of the photonics chip (Figure 1 upper panel, #112 has a width in the left-right direction that is perpendicular to the side surface of #104) and a height dimension extending parallel to the side surface of the photonics chip (Figure 1 upper panel, #112 has a height in the up-down direction that is parallel to the side surface of #104), and a ratio of the width dimension of the second fillet to the height dimension of the second fillet is greater than or equal to 1.5 (Figure 1 upper panel, #112 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #112; accordingly the ‘height’ and ‘width’ may be selected as necessary to meet the required ratio of greater than 1.5).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the two embodiments disclosed adjacent to each other in the prior art reference, Ziadeh, as doing so does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009). Furthermore, Ziadeh teaches that these fillets may vary in size and shape depending on the orientation of the package in [0033]. Incorporating the feature of a second fillet from the embodiment of the upper panel of Figure 1 into the embodiment of the lower panel of Figure 1 would “increase the surface area of the bond and provide structural adhesive in bracing for a die” as taught by Ziadeh in [0016].
Regarding Claim 16. Ziadeh discloses The structure of claim 13 wherein the first fillet is different from the second fillet ([0029]-[0033], Figure 1 upper and lower panels, the fillets #112 and #162 are different in their size, orientation, and overlap characteristics of the photonics chip and packaging die).
Regarding Claim 23. Ziadeh discloses The structure of claim 13 wherein the ratio of the width dimension of the second fillet to the height dimension of the second fillet is less than or equal to 50 (Figure 1 upper panel, #112 has a plurality of widths and heights along it’s triangular shape, as the claim does not require these dimensions to be the greatest dimensions of #112; accordingly the ‘height’ and ‘width’ may be selected as necessary along the shapes dimensions to meet the required ratio of less than 50).
Regarding Claim 26. Ziadeh discloses The structure of claim 13 wherein the second fillet is inverted relative to the first fillet ([0029]-[0033], Figure 1 upper and lower panels, the fillets #112 and #162 are inverted relative to one another based on the orientations and stacking structure of the photonics chip and packaging die).
Regarding Claim 27. Ziadeh discloses The structure of claim 13 wherein the second fillet is larger the first fillet ([0029]-[0033], Figure 1 upper and lower panels, the fillet in the upper panel, #112, which is the second fillet as described above, is larger than the first fillet, #162, shown in the lower panel at least in part due to the cut out of #162 which is occupied by a portion of #154 and the shorter vertical height of #162).
Regarding Claim 28. Ziadeh discloses The structure of claim 13 wherein the [[first]] second fillet is larger the first fillet ([0029]-[0033], Figure 1 upper and lower panels, the fillet in the upper panel, #112, which is the second fillet as described above, is larger than the first fillet, #162, shown in the lower panel at least in part due to the cut out of #162 which is occupied by a portion of #154 and the shorter vertical height of #162).
Claim(s) 17-19 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) as applied to claim 1 above, and further in view of US 2021/0066148 A1; Kim et al.; 03/2021; (“Kim”).
Regarding Claim 17. Ziadeh discloses The structure of claim 1.
Ziadeh does not disclose the structure further comprising: a lid including a first portion that adjoins the photonics chip and a second portion that adjoins the packaging substrate.
Kim teaches a structure (#10, Figures 1A-1C, semiconductor package) comprising a semiconductor chip (#200, Figure 1B) coupled to a packaging substrate (#100, Figure 1B) by a plurality of electrical connections (#210, Figure 1B, connection terminals) and an underfill material (#230, Figure 1B, side encapsulation material including an underfill material according to [0092]) with triangular fillets disposed to overlap with an edge of the chip and an upper surface of the package substrate (Figure 1B), the structure further comprising a lid (#250, Figure 1B, heat sink) including a first portion that adjoins the chip (Figure 1B, central portion of #250 which is overlapping with #200) and a second portion that adjoins the packaging substrate (Figure 1B, thicker side portions which are directly adjoined to #100).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing lid/heat sink structure in Ziadeh, as was done in Kim, in order to act as a passive heat exchanger to optimize the temperature of the chip (see [0065] of Kim) and provide high thermal transfer efficiency and endurance to the package (see [0066] of Kim).
Regarding Claim 18. Ziadeh in view of Kim discloses The structure of claim 17 wherein the lid includes a third portion between the first portion and the second portion (Kim, Figure 1B, portion of #250 which connects the portion overlapping #200 to the thicker edge portion connected directly to #100), the third portion of the lid is spaced from the packaging substrate to define an open space, and the [[second]] first fillet is disposed in the open space (Kim, Figure 1B, the connecting portion of #250 is spaced apart from #100 to define an open space in which a fillet of the underfill material #230 is located).
Regarding Claim 19. Ziadeh in view of Kim discloses The structure of claim 18 wherein the photonics chip has a bottom surface opposite to the top surface (Kim, Figure 1B, top surface of #200 in the positive z-direction), and the first portion of the of the lid is adjoined to the bottom surface of the photonics chip (Kim, Figure 1B, the central portion of #250 which is overlapping with #200 is indirectly adjoined to the top surface of #200 by thermal interface material #240).
Regarding Claim 21. Ziadeh in view of Kim discloses The structure of claim [[10]] 17 wherein the lid comprises an electrically-conductive and thermally-conductive material (Kim, #250, Figure 1B, [0066], the heat sink may comprise copper which is both an electrically and thermally conductive material).
Regarding Claim 22. Ziadeh in view of Kim discloses The structure of claim [[10]] 17 further comprising:
a layer of thermal interface material (Kim, #240, Figure 1B, thermal interface material) between the photonics chip and the first portion of the lid that adjoins the photonics chip (Kim, Figure 1B, #240 is located between #200 and the portion of the lid #250 which overlaps with and adjoins indirectly with #200 through #240).
Claim(s) 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) as applied to claims 13 and 23 above, and further in view of Effect of Underfill Fillet Height on Packaging Reliability in Flip Chip; Zhao et al.; 09/2022; (“Zhao”).
Regarding Claim 24. Ziadeh discloses The structure of claim 23.
Ziadeh does not disclose that the second fillet is coextensive with [[the]] a substrate of the photonics chip over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns. However, Ziadeh teaches that these fillets may vary in size and shape depending on the manufacturing processes utilized (see [0033]) and that larger fillets are beneficial in their ability to increase bond surface area and provide bracing for the dies (see [0016]).
Zhao teaches that the height of an underfill fillet on the overlying chip has extensive influence on the reliability of the package (see title). As can be observed in Figures 4, 5, and 6, the height/geometry of the fillet relative to the chip will have extensive influence on the stresses experienced by the package (see abstract, Figures 4-6, and conclusion). In particular, the following observations are made by Zhao:
The Tensile, Mises and Compressive stress on the edge solder balls increases with increasing fillet height percentages (Figure 4).
The Mises and Compressive stress on the chip edge also increases with increasing fillet height percentages but the Tensile stress decreases (Figure 5).
The Mises and Tensile stress on the top point of the fillet is maximized in the 50% range of the fillet height while Mises and Tensile stress at the bottom fillet point increases with increasing fillet height percentages (Figure 6).
The Mises and Tensile stress on the top point of the chip is maximized in the 100% range of the fillet height (Figure 7).
Therefore, the claim limitation of “the second fillet is coextensive with a substrate of the photonics chip over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns” is interpreted by the examiner to be a routine optimization (see MPEP 2144.05.II) depending on the thickness of the photonics chip and permissible stresses on the package. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider optimizing the height of the first fillet in Ziadeh such that the fillet may be coextensive with the substrate over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns depending on the size of the chip as the overlap is well understood in view of both Zhao as extensively influencing the balancing of stresses experienced by the chip, fillet, and solder connections in the package (see abstract, Figures 4-7, and conclusion of Zhao).
Regarding Claim 25. Ziadeh discloses The structure of claim 13.
Ziadeh does not disclose that the second fillet is coextensive with [[the]] a substrate of the photonics chip over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns. However, Ziadeh teaches that these fillets may vary in size and shape depending on the manufacturing processes utilized (see [0033]) and that larger fillets are beneficial in their ability to increase bond surface area and provide bracing for the dies (see [0016]).
Zhao teaches that the height of an underfill fillet on the overlying chip has extensive influence on the reliability of the package (see title). As can be observed in Figures 4, 5, and 6, the height/geometry of the fillet relative to the chip will have extensive influence on the stresses experienced by the package (see abstract, Figures 4-6, and conclusion). In particular, the following observations are made by Zhao:
The Tensile, Mises and Compressive stress on the edge solder balls increases with increasing fillet height percentages (Figure 4).
The Mises and Compressive stress on the chip edge also increases with increasing fillet height percentages but the Tensile stress decreases (Figure 5).
The Mises and Tensile stress on the top point of the fillet is maximized in the 50% range of the fillet height while Mises and Tensile stress at the bottom fillet point increases with increasing fillet height percentages (Figure 6).
The Mises and Tensile stress on the top point of the chip is maximized in the 100% range of the fillet height (Figure 7).
Therefore, the claim limitation of “the second fillet is coextensive with a substrate of the photonics chip over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns” is interpreted by the examiner to be a routine optimization (see MPEP 2144.05.II) depending on the thickness of the photonics chip and permissible stresses on the package. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider optimizing the height of the first fillet in Ziadeh such that the fillet may be coextensive with the substrate over a distance that is greater than or equal to 35 microns and less than or equal to 65 microns depending on the size of the chip as the overlap is well understood in view of both Zhao as extensively influencing the balancing of stresses experienced by the chip, fillet, and solder connections in the package (see abstract, Figures 4-7, and conclusion of Zhao).
Response to Arguments/Amendments
Applicant’s amendments to claims 1 and 20 and corresponding arguments, see pages 8-9 of the remarks, filed 04/21/2026, with respect to the 35 U.S.C. 102 rejections of claims 1 and 20, along with several of their respective dependent claims, have been fully considered but have not been found persuasive. Claims 1, 2, 4, 8, and 20 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”).
Applicant argues that the examiner is speculating regarding the ratio of the width dimension to the height dimension of the claimed first fillet. The examiner believes there has been a misinterpretation of how the examiner is reading the claims as being anticipated by Ziadeh which the examiner attempts to clarify below with both annotated figures and some additional explanation.
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The claim currently requires a width of the fillet which extends parallel to the top surface of the photonics chip but does not require the corresponding width to be the greatest, smallest, or any other characteristics of the selected width in particular. Similarly, the claim currently requires a height of the fillet which extends perpendicular to the top surface of the photonics chip but does not require the corresponding height to be the greatest, smallest, or any other characteristics of the selected width in particular. Because the fillet (#162) is a triangular shape, the shape comprises a plurality of widths such as the smallest width which goes to zero at the point of the fillet closest to #152 or the greatest width at the point of the fillet which is in contact with #154 (see Figure 1 annotated above showing three possible identified widths of #162). The same can be said of the heights of the triangular shape such that the shape comprises a plurality of heights such as the smallest height which goes to zero at the point of the fillet contacting #154 or the greatest height at the point of the fillet which is closest to #152 (see Figure 1 annotated above showing three possible identified heights of #162). In reading on the claim, any of these heights and/or widths may be selected as the height and the width of the shape since they are each heights and widths, respectively. Therefore, one may reasonably select any appropriate combination of a height and a width of the corresponding fillet such that the ratio of the selected width to the selected height is greater than or equal to 1.5 as required by the claim. For example, the width may be selected as the greatest width measurable of the fillet and the height may then be chosen accordingly, since the height goes to zero. One may just read the height as the smallest possible height measurable such that the ratio of the width to the height is greater than 1.5 as the height is near zero while the width is some maximum.
Applicant’s arguments regarding claim 7, see page 9 of the remarks, filed 04/21/2026, with respect to the 35 U.S.C. 103 rejections of claim 7, as being allowable at least for its dependence on claim 1 has not been found persuasive as claim 1 stands rejected as described above.
Applicant’s arguments regarding claims 17-19, see page 9 of the remarks, filed 04/21/2026, with respect to the 35 U.S.C. 103 rejections of claim 17-19, as being allowable at least for their dependence on claim 1 has not been found persuasive as claim 1 stands rejected as described above.
Applicant’s arguments regarding claims 13-16, see page 9 of the remarks, filed 04/21/2026, with respect to the 35 U.S.C. 103 rejections of claim 13-16, as being allowable at least for their dependence on claim 1 has not been found persuasive as claim 1 stands rejected as described above.
Applicant’s amendments to claim 13 and corresponding arguments, see pages 10-11 of the remarks, filed 04/21/2026, with respect to the 35 U.S.C. 103 rejection of claim 13, along with several of its respective dependent claims, have been fully considered but have not been found persuasive. Claims 13, 16, 23, and 26-28 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0196937 A1; Ziadeh et al.; 06/2022; (“Ziadeh”) as applied to claim 1 above.
Applicant first argues that the examiner is speculating on the shape and size of the different fillet types in Figure 1 of Ziadeh based on the orientation of the package. Examiner respectfully disagrees. The two different panels of Figure 1 clearly show two different non-identical fillet styles with different dimensions, shapes, and orientations relative to the packaging substrate and the photonics chip with the lower panel clearly showing a fillet extending along a photonics chip and on an edge of the packaging substrate while the upper panel shows a larger fillet with a different shape that is extends along the packaging substrate and is on an edge of the photonics chip.
Applicant’s second argument points to examiner’s reference to Boston Scientific v. Cordis (Fed. Cir. 2009) as part of the 35 U.S.C. 103 rejection of the claim, arguing that the examiner’s rejection cannot be sustained by mere conclusory statements and that there must be some articulated reasoning or rational. As stated in the 35 U.S.C. 103 rejection above, the combination of the two panels from Ziadeh does not require an inventive step and would be obvious since Ziadeh teaches that these fillets may vary in size and shape depending on the orientation of the package in [0033]. Incorporating the feature of a second fillet from the embodiment of the upper panel of Figure 1 into the embodiment of the lower panel of Figure 1 would “increase the surface area of the bond and provide structural adhesive in bracing for a die” as taught by Ziadeh in [0016]. Thus there is an articulated reasoning from Ziadeh to combine the two panels.
Applicant lastly argues that Ziadeh teaches that the fillets are undesirable based on [0030] of the reference such that they are not present in the final product as they are only a temporary configuration. Examiner respectfully disagrees with applicant’s interpretation of [0030] of the reference and its impact on the final product. [0030] of Ziadeh states that “later in the manufacturing process, the die 104 has to be etched down, this fillet 112 of epoxy will remain and may be higher than the etched height of the die 104 and cause die stacking problems, particularly if legacy package 100 is an optical package”, which is not interpreted by the examiner to provide any indication that the fillets need to be entirely removed. This only appears to state that the dimensions of the fillet should be carefully controlled so as not to be over extended and create issues in stacking. [0033] seems to suggest that, if additional clearing of the fillets due to over extension is required, this will add additional time, chemical, and cost requirements to the manufacturing process. The examiner respectfully disagrees that this means the fillets would not be considered obvious to one of ordinary skill in the art, only that the size, shapes, and orientations of these fillets must be a careful consideration based on their adhesive properties being increased by being larger but also creating scenarios in which they need to be etched back in the case that they are too large. The well-understood characteristics of these fillets’ dimensions, shapes, and orientations, and their impacts on package durability and stresses are further described in the rejections of claims 7, 24, 25, and 29 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TYLER J WIEGAND/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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