DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-9 and 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over FAN (US 20210335653) in view of ISOBAYASHI (US 20120319279).
Regarding claim 1, FAN discloses a semiconductor die structure, comprising:
a substrate (substrate 101, see fig 18-19, para 57);
a first supporting backbone (first backbone 111, see fig 18, para 63) disposed on and in contact with a top surface of the substrate (111 is in contact with the top surface of 101), wherein the first supporting backbone has a uniform width (111 has a uniform width, see fig 18), wherein the first supporting backbone and the substrate are made of different materials (100 can be Si and 111 can be SiN, see fig 18, para 57 and 63);
a first conductor block (the conductor block 113C which is directly on 111, see fig 18-19, para 67) disposed on the first supporting backbone;
an air gap structure (123 can be processed to air gap 130, see fig 19, para 82) disposed on and in contact with the top surface of the substrate (130 will be in contact with the top surface of 101, see fig 18-19) and in contact with the first supporting backbone and the first barrier layer of the first conductor block (130 is in contact with 111 and 113C, and thus all parts of 113C, see fig 18-19, para 82), wherein the first supporting backbone is surrounded by the air gap structure (111 will be surrounded by 130, see fig 18-19);
wherein the first supporting backbone is positioned between the substrate and the first conductor block (111 is between 113C and 101, see fig 18-19);
wherein the first supporting backbone is enclosed by the substrate, the first conductor block, and the air gap structure (111 is surrounded by 113C, 130 and 101, see fig 18-19);
wherein a width of the first supporting backbone is equal to a width of the first conductor block (111 and 113C have a same width, see fig 18-19);
wherein the first conductor block has a bottom portion extended from the first supporting backbone and surrounded by the air gap structure (a bottom part of 113 extends from the top of 111 to higher than 130, see fig 18-19), and a top portion protruded out of a top surface of the air gap structure (a bottom part of 113 extends from the top of 111 to higher than 130, see fig 18-19).
FAN fails to explicitly disclose a device comprising a first conductor block disposed on the first supporting backbone, comprising:
a first barrier layer; and
a first conductive layer, disposed in the first barrier layer, wherein a top surface of the first conductive layer is coplanar with a top surface of the first barrier layer; and
such that a top portion of the first barrier layer and a top portion of the first conductive layer are protruded out of the top surface of the air gap structure.
ISOBAYASHI teaches a device comprising a first conductor block (the left conductor block comprising 13 and 15, see fig 1, para 19 ) disposed on the first supporting backbone (13 and 15 are disposed on 21, see fig 1, para 15), comprising:
a first barrier layer (fig 1, 13, para 19); and
a first conductive layer (fig 1E 15, para 21), disposed in the first barrier layer, wherein a top surface of the first conductive layer is coplanar with a top surface of the first barrier layer (topmost surface of 13 and 15 are coplanar, see fig 1E); and
such that a top portion of the first barrier layer and a top portion of the first conductive layer are protruded out of the top surface of the air gap structure (top portions of 13 and 15 protrude from a top surface of 11 which is part of the air gap structure, see fig 1F, para 22).
FAN and ISOBAYASHI are analogous art because they both are directed towards semiconductor interconnect device structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI in order to prevent moisture absorption (see para 19).
Regarding claim 2, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 1.
FAN fails to explicitly disclose a device, wherein the first barrier layer has U-shaped cross sectional profile defining a bottom portion and two side portions,
wherein the bottom portion is in contact with the first supporting backbone and connects one of the side portions to another one of the side portions,
wherein a width of the bottom portion of the first barrier layer is equal to the width of the first supporting backbone;
wherein each of the side portions of the first barrier layer is sandwiched and in direct contact between the air gap structure and the first conductive layer.
ISOBAYASHI teaches a device, wherein the first barrier layer has U-shaped cross sectional profile defining a bottom portion and two side portions (13 has a bottom and two side portions, see fig 1E, para 21),
wherein the bottom portion is in contact with the first supporting backbone and connects one of the side portions to another one of the side portions (a bottom portion of 13 is in contact with 21, see fig 1E),
wherein a width of the bottom portion of the first barrier layer is equal to the width of the first supporting backbone (a portion of 21 has the same width as the bottom of 13, see fig 1I);
wherein each of the side portions of the first barrier layer is sandwiched and in direct contact between the air gap structure and the first conductive layer (the side portions of 13 are between and in direct contact with 15 and layer 17 of the air gap structure, see fig 1I).
FAN and ISOBAYASHI are analogous art because they both are directed towards semiconductor interconnect device structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI in order to prevent moisture absorption (see para 19).
Regarding claim 3, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 2.
FAN fails to explicitly disclose a device,
wherein a first thickness of the bottom portion is greater than a second thickness of the side portions,
wherein the first thickness of the bottom portion is defined as a vertical distance between the first supporting backbone and the first conductive layer,
wherein the second thickness of each of the side portions is defined as a horizontal distance between the air gap structure and the first conductive layer.
ISOBAYASHI teaches a device, wherein a first thickness of the bottom portion is greater than a second thickness of the side portions (the thickness of the bottom portion of 13 can be more than 2 nm, and the thickness of the top portion of 13 can be less than 2 nm, see fig 1C, para 19),
wherein the first thickness of the bottom portion is defined as a vertical distance between the first supporting backbone and the first conductive layer (the vertical thickness of the bottom of 13, see fig 1C),
wherein the second thickness of each of the side portions is defined as a horizontal distance between the air gap structure and the first conductive layer (the horizontal thickness of the upper parts of 13 on 12, see fig 1C, para 19).
FAN and ISOBAYASHI are analogous art because they both are directed towards semiconductor interconnect device structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI in order to prevent moisture absorption (see para 19).
Regarding claim 7, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 6.
FAN further discloses a device, further comprising:
a capping dielectric layer (fig 18-19, 125, para 78), disposed over the air gap structure (125 is over 130, see fig 18-19), wherein the capping dielectric layer surrounds the top portion of the first conductor block and the first hard mask (125 surrounds top portions of 113C and 113D, see fig 18), such that the top portion of the first barrier layer is surrounded by the capping dielectric layer (top portions of 113C are surrounded by 125, see fig 18).
Regarding claim 8, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 2.
FAN further discloses a device, further comprising:
second supporting backbone (fig 18, 119, para 72) disposed on and in contact with the top surface of the substrate, wherein the second supporting backbone has a uniform width (see fig 18);
a second conductor block (120, see fig 18-19, para 78) disposed on the second supporting backbone,
wherein the air gap structure is disposed between the first conductor block and the second conductor block (130 will be between 113C and 120, see fig 18),
wherein the second supporting backbone is positioned between the substrate and the second conductor block (119 is between 120 and 101, see fig 18);
wherein the second supporting backbone is enclosed by the substrate, the second conductor block, and the air gap structure (119 is surrounded by 101, 130 and 120, see fig 18);
wherein a width of the second supporting backbone is equal to a width of the second conductor block (119 and 120 have the same width, see fig 18);
wherein the second conductor block has a second bottom portion extended from the second supporting backbone and surrounded by the air gap structure, and a second top portion protruded out of the top surface of the air gap structure (a bottom portion of 120 is in contact with 119 and surrounded by 130, and a top portion of 120 protrudes from a top of 130, see fig 18-19).
Regarding claim 9, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 8.
FAN further discloses a device, further comprising:
a third conductor block disposed on the substrate (the conductor 113C between 111 and 119, see fig 18, para 67); and
a fourth conductor block disposed on the substrate (the conductor 120 between 111 and 119, see fig 18, para 73),
wherein the third conductor block and the fourth conductor block are disposed between the first conductor block and the second conductor block (the conductors 113C and 120 in the middle of fig 18 are between the 113C over 111 and the 120 over 119, see fig 18),
wherein the third conductor block and the fourth conductor block are not in contact with the first supporting backbone and the second supporting backbone (the middle 113C and 120 are not in direct contact with 111 and 119, see fig 18);
wherein bottom portions of the third conductor block and the fourth conductor block are surrounded by the air gap structure (the bottom portions of the middle 113C and 120 will be surrounded by 130, see fig 18-19);
wherein bottom surfaces of the third conductor block and the fourth conductor block are in direct contact with the air gap structure (the bottom portions of the middle 113C and 120 are in direct contact with 130, see fig 18-19).
Regarding claim 11, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 8.
FAN fails to explicitly disclose a device, wherein the second conductor block comprising:
a second barrier layer; and
a second conductive layer, disposed in the second barrier layer,
wherein a top surface of the second conductive layer is coplanar with a top surface of the second barrier layer;
wherein a top portion of the second barrier layer and a top portion of the second conductive layer are protruded out of the top surface of the air gap structure.
ISOBAYASHI teaches a device, wherein the second conductor block (the second from the right conductor comprising 13 and 15, see fig 1E) comprising:
a second barrier layer (fig 1, 13, para 19); and
a second conductive layer (fig 1E 15, para 21), disposed in the second barrier layer,
wherein a top surface of the second conductive layer is coplanar with a top surface of the second barrier layer (top surface of 13 and 15 are coplanar, see fig 1E);
wherein a top portion of the second barrier layer and a top portion of the second conductive layer are protruded out of the top surface of the air gap structure (top portions of 13 and 15 protrude from a top surface of 11 which is part of the air gap structure, see fig 1F, para 22).
FAN and ISOBAYASHI are analogous art because they both are directed towards semiconductor interconnect device structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI in order to prevent moisture absorption (see para 19).
Regarding claim 12, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 11.
FAN fails to explicitly disclose a device, wherein the second barrier layer has U-shaped cross sectional profile defining a bottom portion and two side portions,
wherein a width of the bottom portion of the second barrier layer is equal to the width of the second supporting backbone;
wherein the bottom portion of the second barrier layer is in contact with the second supporting backbone and connects one of the side portions of the second barrier layer to another one of the side portions of the second barrier layer.
ISOBAYASHI teaches a device, wherein the second barrier layer has U-shaped cross sectional profile defining a bottom portion and two side portions (13 has a bottom and two side portions, see fig 1E, para 21),
wherein a width of the bottom portion of the second barrier layer is equal to the width of the second supporting backbone (a portion of 21 has the same width as the bottom of 13, see fig 1I);
wherein the bottom portion of the second barrier layer is in contact with the second supporting backbone and connects one of the side portions of the second barrier layer to another one of the side portions of the second barrier layer (a bottom portion of 13 is in contact with 21 and connects the side parts of 13, see fig 1E).
FAN and ISOBAYASHI are analogous art because they both are directed towards semiconductor interconnect device structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI in order to prevent moisture absorption (see para 19).
Regarding claim 13, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 12.
FAN fails to explicitly disclose a device, wherein a third thickness of the bottom portion of the second barrier layer is greater than a fourth thickness of the side portions of the second barrier layer.
ISOBAYASHI teaches a device, wherein a third thickness of the bottom portion of the second barrier layer is greater than a fourth thickness of the side portions of the second barrier layer (the thickness of the bottom portion of 13 can be more than 2 nm, and the thickness of the top portion of 13 can be less than 2 nm, see fig 1C, para 19).
FAN and ISOBAYASHI are analogous art because they both are directed towards semiconductor interconnect device structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FAN with the conductor block comprising a barrier layer and a conductive layer of ISOBAYASHI in order to prevent moisture absorption (see para 19).
Regarding claim 14, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 12.
FAN further discloses a device, further comprising:
a second metal silicide (the silicide 120D over 120, see fig 18, para 75), disposed over the second conductor block,
wherein the second metal silicide is in contact with the second conductive layer and the side portions of the second barrier layer (120D is in contact with 120 and thus in at least indirect contact with every portion of fig 18);
wherein a width of the second metal silicide is equal to the width of the second supporting backbone and is equal to a width of the second barrier layer (widths of 120D, 120 and 119 are equal, see fig 18).
Regarding claim 15, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 14.
FAN further discloses a device, further comprising: a second hard mask (fig 18, 121, para 76), disposed over the second metal silicide,
wherein a width of the first hard mask is equal to the width of the first metal silicide (121 and 130D have a same width, see fig 18),
wherein the width of the second hard mask is equal to the width of the second barrier layer (widths of 121 and 120 are equal, see fig 18).
Regarding claim 16, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 1.
FAN further discloses a device, wherein the first supporting backbone comprises tungsten oxide, hafnium oxide, zirconium oxide, silicon mononitride (SiN), silicon carbide (SiC), or silicon carbonitride (SiCN) (111 can be SiCN, see para 63).
Regarding claim 17, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 1.
FAN further discloses a device, wherein the air gap structure comprises: an air gap (fig 19, 127, para 82); and a liner layer (fig 19, 129, para 82) enclosing the air gap,
wherein the top portion of the first conductor block is protruded out of a top surface of the liner layer of the air gap structure (113C protrudes from a top of 130, see fig 19).
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over FAN (US 20210335653) and ISOBAYASHI (US 20120319279) in view of BARK (US 20180261546).
Regarding claim 4, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 2
FAN further discloses a device, further comprising:
a first metal silicide (the 113D over 113C, see fig 18, para 67), disposed over the first conductor block,
wherein a width of the first metal silicide is equal to the width of the first supporting backbone and is equal to a width of the first barrier layer (widths of 113D 113C and 111 are equal, see fig 18).
FAN fails to explicitly disclose a device wherein the first metal silicide is in direct contact with the first conductive layer and the side portions of the first barrier layer at a top surface thereof.
BARK teaches a device wherein the first metal silicide is in direct contact with the first conductive layer and the side portions of the first barrier layer at a top surface thereof (234A and 236A are directly on top surfaces of 136 and 134, see fig 10, para 88-89).
FAN and ISOBAYASHI and BARK are analogous art because they both are directed towards semiconductor transistor device interconnect structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FAN and ISOBAYASHI with the metal silicide geometry of BARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FAN and ISOBAYASHI with the metal silicide geometry of BARK in order to suppress an increase in the leakage current (see BARK para 46).
Regarding claim 5, FAN, ISOBAYASHI and BARK disclose the semiconductor die structure of claim 4.
FAN further discloses a device, wherein the first metal silicide comprises cobalt (Co), copper (Cu), ruthenium (Ru), cobalt monosilicide (CoSi), or nickel mono-silicide (NiSi) (113D can be NiSi or CoSi, see fig 18, para 67).
Regarding claim 6, FAN, ISOBAYASHI and BARK disclose the semiconductor die structure of claim 4.
FAN further discloses a device, further comprising:
a first hard mask (fig 18, 115, para 68), disposed over the first metal silicide, wherein a width of the first hard mask is equal to the width of the first metal silicide (113D and 115 have a same width, see fig 18),
wherein the width of the first hard mask is equal to the width of the first barrier layer (115 and 113C have the same width, see fig 18).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over FAN (US 20210335653) and ISOBAYASHI (US 20120319279) in view of CHENG (US 11658062).
Regarding claim 10, FAN and ISOBAYASHI disclose the semiconductor die structure of claim 9.
FAN further discloses a device, wherein the third conductor block and the fourth conductor block are spaced apart from the substrate by the air gap structure (the middle 113C and 120 are spaced apart from 101 by 130, see fig 18-19),
wherein top portions of the third conductor block and the fourth conductor block are protruded out of the top surface of the air gap structure (top surfaces of the middle 113C and 120 protrude from the top of 130, see fig 18-19).
FAN fails to explicitly disclose a device wherein the first conductor block, the second conductor block, the third conductor block, and the fourth conductor block are equal in width.
CHENG teaches a device wherein the first conductor block, the second conductor block, the third conductor block, and the fourth conductor block are equal in width (the lines 151-1 to 4 have a width W, see fig 1A, para 37).
FAN, ISOBAYASHI and CHENG are analogous art because they both are directed towards semiconductor device interconnection structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FAN and ISOBAYASHI with the conductor width of CHENG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FAN and ISOBAYASHI with the conductor width of CHENG in order to improve reliability (see CHENG para 31).
Response to Arguments
Applicant's arguments filed 5/6/2026 have been fully considered but they are not persuasive.
The applicant argues that FAN does not, when combined with BIELEFELD disclose the limitations of claims 1 and 4. This may be true, but as detailed in the rejection above, FAN in combination with ISOBAYASHI discloses every element of claim 1, and FAN in combination with ISOBAYASHI and BARK discloses every element of claim 4.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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