DETAILED ACTION
This action is responsive to the application No. 18/237,195 filed on August 23, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species I, and modification B, corresponding to device claims 1, 2, 4, 7-13, and 15-19, in the reply filed on December 2, 2025, is acknowledged. Claims 3, 5, 6, 14, and 20 are withdrawn from consideration.
In addition, claims 9 and 18, drawn to non-elected species III (Fig. 4), wherein the thermal plug extends into the underlying handle substrate, are withdrawn from consideration.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Objections
Claims 11-13, 15-17, and 19 are objected to because of the following informalities:
In claim 11, line 5, “one active regions” should be changed to -- one active region --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites “a barrier layer”, however claim 11 already introduces “a barrier layer”, making it unclear if Applicant intends to introduce two different barrier layers or if claim 16 was supposed to recite the barrier layer, previously introduced in claim 11. For the purpose of Examination, it is assumed there is only one barrier layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7-8, 10-13, 15-17, and 19, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. (US 2019/0027426).
(Re Claim 1) Chu teaches a structure comprising (see Fig. 4 and ¶¶32-47):
a semiconductor substrate (layers 100-108);
a gate structure (114) over the semiconductor substrate;
a source region (112) on a first side of the gate structure;
a drain region (110) on a second side of the gate structure; and
a thermal plug (combination of 122 and 124, 124 is thermally conductive metal) extending from a top side of the semiconductor substrate into an active region (active region comprising layers 108-106) of the semiconductor substrate.
(Re Claim 2) further comprising ohmic contacts to the source region and the drain region (¶39: ohmic contacts).
(Re Claim 7) wherein the thermal plug comprises a metal material lined with a dielectric material (¶42: metal 124 and dielectric 122).
(Re Claim 8) wherein the semiconductor substrate comprises plural semiconductor materials comprising at least AlN, GaN, a superlattice material and an underlying semiconductor handle substrate (¶¶35-38, layers 100-108 include GaN, AlN, as claimed “a superlattice material” is any material that can be used in a superlattice, e.g. GaN, AlN, AlGaN, etc., all of which are present, the claim does not require a superlattice structure, i.e. alternating layers, substrate 100).
(Re Claim 10) wherein the thermal plug stops above the underlying semiconductor handle substrate, extending through the GaN and the superlattice material and stopping in the AlN (Fig. 4, 120 at far left stops above substrate 100 in layer 102 which may be AlN, 120 in center extends upwards and stops above substrate 100 in layer 104 which may also be AlN).
(Re Claim 11) Chu teaches a structure comprising (see Fig. 4 and ¶¶32-47):
a semiconductor substrate comprising a plurality of semiconductor materials (layers 100-106);
a barrier layer (108) over the plurality of semiconductor materials;
a gate structure (114) over the semiconductor substrate;
at least one active regions (e.g. layers 106-108) adjacent to the gate structure; and
a thermal plug extending (124 or combination of 122 and 124, 124 is thermally conductive metal) from a top side into the at least one active region adjacent to the gate structure (Fig. 4).
(Re Claim 12) wherein the at least one active region comprises a drain region (region of layers 108 and 106 in a region below/around 110).
(Re Claim 13) wherein the at least one active region comprises a source region (region of layers 108 and 106 in a region below/around 112).
(Re Claim 15) wherein the thermal plug is a metal material lined with an insulator material (¶42: metal 124 and dielectric 122).
(Re Claim 16) wherein the thermal plug extends through a barrier layer (Fig. 4).
(Re Claim 17) wherein the thermal plug extends above the barrier layer (above is met when Fig. 4 is rotated 90-180°, no directions with respect to the device are established, “above” depends on an orientation, the device may exist in any orientation).
(Re Claim 19) wherein the plurality of semiconductor materials comprises at least AlN, GaN, a superlattice material and an underlying semiconductor handle substrate (¶¶35-38, layers 100-108 include GaN, AlN, as claimed “a superlattice material” is any material that can be used in a superlattice, e.g. GaN, AlN, AlGaN, etc., all of which are present, the claim does not require a superlattice structure, i.e. alternating layers, substrate 100), and the thermal plug (124) extends, from the top side, into the AIN, the GaN and the superlattice material, and does not contact with the underlying semiconductor handle substrate (124 is separated from substrate 100 by layer 122).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. as applied above and further in view of Bothe et al. (US 2020/0395475).
(Re Claim 8) wherein the semiconductor substrate comprises plural semiconductor materials comprising at least AlN, GaN, a superlattice material and an underlying semiconductor handle substrate (¶¶35-38, layers 100-108 include GaN, AlN, substrate 100, superlattice discussed below).
(Re Claim 10) wherein the thermal plug stops above the underlying semiconductor handle substrate, extending through the GaN and the superlattice material and stopping in the AlN (Fig. 4, 120 at far left stops above substrate 100 in layer 102 which may be AlN, 120 in center extends upwards and stops above substrate 100 in layer 104 which may also be AlN).
(Re Claim 19) wherein the plurality of semiconductor materials comprises at least AlN, GaN, a superlattice material and an underlying semiconductor handle substrate (¶¶35-38, layers 100-108 include GaN, AlN, substrate 100, superlattice discussed below), and the thermal plug (124) extends, from the top side, into the AIN, the GaN and the superlattice material, and does not contact with the underlying semiconductor handle substrate (124 is separated from substrate 100 by layer 122).
Regarding the claimed “superlattice material” in claims 8, 10, and 19, while this limitation does not specifically require a superlattice structure, Chu does not disclose a superlattice structure. A PHOSITA desiring to make, use, and improve upon Chu’s HEMT device would be motivated to look to related art to teach alternatives which may lead to device performance improvements. Related art from Bothe teaches the channel may be formed as a superlattice structure, e.g. alternating layers of GaN/AlGaN, or the like (¶88). Superlattice channels in III-V HEMTs, such as AlGaN/GaN structures, offer superior performance over conventional bulk GaN channels by enabling higher charge carrier density (2DEG), improved vertical thermal dissipation, and better strain management to reduce dislocations. These structures significantly enhance RF linearity and breakdown voltage while mitigating short-channel effects, often with fewer fabrication steps than complex multi-channel alternatives. Therefore, a PHOSITA would find it obvious to form the GaN channel (layer 106) as a superlattice structure as discussed by Bothe for the advantages discussed above.
Claims 1, 2, 4, 7, 11-13, and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsurumi et al. (US 2011/0175142).
(Re Claim 1) Tsurumi teaches a structure comprising (see Fig. 1 and ¶¶29-41, 57):
a semiconductor substrate (11, 12, 13, 14);
a gate structure (23) over the semiconductor substrate;
a source region (region below source electrode 21) on a first side of the gate structure;
a drain region (region below drain electrode 22) on a second side of the gate structure; and
a thermal plug (33) extending from a top side of the semiconductor substrate into an active region (active layers 14, 13, 12) of the semiconductor substrate.
(Re Claim 2) further comprising ohmic contacts to the source region and the drain region (¶30).
(Re Claim 4) wherein the thermal plug is electrically isolated from a drain metal (Fig. 1 and ¶57).
(Re Claim 7) wherein the thermal plug comprises a metal material lined with a dielectric material (¶37: 33A/33B).
(Re Claim 11) Tsurumi teaches a structure comprising (see Fig. 1 and ¶¶29-41, 57):
a semiconductor substrate comprising a plurality of semiconductor materials (11, 12, 13);
a barrier layer (14 or 15 or 14+15) over the plurality of semiconductor materials;
a gate structure (23) over the semiconductor substrate;
at least one active regions (region(s) of layer 13/14) adjacent to the gate structure; and
a thermal plug (33) extending from a top side into the at least one active region adjacent to the gate structure (Fig. 1).
(Re Claim 12) wherein the at least one active region comprises a drain region (region below 22).
(Re Claim 13) wherein the at least one active region comprises a source region (region below 21).
(Re Claim 15) wherein the thermal plug is a metal material (33A) lined with an insulator material (33B, ¶37).
(Re Claim 16) wherein the thermal plug extends through a barrier layer (Fig. 1).
(Re Claim 17) wherein the thermal plug extends above the barrier layer (Fig. 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches semiconductor devices with conductive via/plug features extending through semiconductor layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898