DETAILED ACTION
This action is responsive to the amendment received May 7, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
The prior claim objection is withdrawn in view of amended claim 11.
Claim Rejections - 35 USC § 112
The prior §112 rejection is withdrawn in view of amended claim 11.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4, 7-8, 10-13, 15-17, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 11 recite “electrically isolated” rendering the claims indefinite because Applicant does not define the nature or degree of electrical isolation required, and in particular with respect to claim 1, isolated with respect to what exactly? It is further noted the device is a HEMT device, well-known for high frequency operation, and high frequency AC will passes through insulators, in addition parts can be insulated and still be capacitively coupled which would not be understood to be completely isolated. Also, a conductive feature may be locally isolated from another feature thereby forcing a current path around or through other parts of a device rather than directly into an adjacent element. The degree and type of isolation is unclear. There is no definition provided by Applicant and the only sentence in the specification regarding any isolation with respect to the thermal plug states the thermal plug is electrically isolated from the drain region, e.g. drain metal (¶24). The specification contains no other disclosures of general isolation or degree thereof. This sentence also confuses this issue as Applicant describes the drain region including the drain metal (¶24) and also conflates the drain region with the active region (¶17). It is unclear if the “active region” includes the drain metal. In light of the specification, the “active region” is not clear. Conventionally, the active region of a transistor corresponds to the channel of the transistor which is below the gate and between (but not including) the source/drain regions, while Applicant apparently uses “active region” to describe various features including a drain region and a drain metal, contrary to the customary meaning and without clearly redefining the term.
Claim 7 recites “the metal material”, lacking antecedence.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 7-8, 10-13, 15-17, and 19, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. (US 2019/0027426), of record.
(Re Claim 1) Chu teaches a structure comprising (see Fig. 4 and ¶¶32-47):
a semiconductor substrate (layers 100-108);
a gate structure (114) over the semiconductor substrate;
a source region (112) on a first side of the gate structure;
a drain region (110) on a second side of the gate structure; and
a thermal plug (combination of 122 and 124, 124 is thermally conductive metal) extending from a top side of the semiconductor substrate into an active region (active region comprising layers 108-106) of the semiconductor substrate, the thermal plug comprising a conductive material (124) lined with a dielectric material (122), the conductive material being electrically isolated (124 is electrically isolated from 100, 102, at lower left, at the sidewalls of the opening 120 and isolated from 112, 114, etc.).
(Re Claim 8) wherein the semiconductor substrate comprises plural semiconductor materials comprising at least AlN, GaN, a superlattice material and an underlying semiconductor handle substrate (¶¶35-38, layers 100-108 include GaN, AlN, as claimed “a superlattice material” is any material that can be used in a superlattice, e.g. GaN, AlN, AlGaN, etc., all of which are present, the claim does not require a superlattice structure, i.e. alternating layers, substrate 100).
(Re Claim 10) wherein the thermal plug stops above the underlying semiconductor handle substrate, extending through the GaN and the superlattice material and stopping in the AlN (Fig. 4, 120 at far left stops above substrate 100 in layer 102 which may be AlN, 120 in center extends upwards and stops above substrate 100 in layer 104 which may also be AlN).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. as applied above and further in view of Bothe et al. (US 2020/0395475), of record.
(Re Claim 8) wherein the semiconductor substrate comprises plural semiconductor materials comprising at least AlN, GaN, a superlattice material and an underlying semiconductor handle substrate (¶¶35-38, layers 100-108 include GaN, AlN, substrate 100, superlattice discussed below).
(Re Claim 10) wherein the thermal plug stops above the underlying semiconductor handle substrate, extending through the GaN and the superlattice material and stopping in the AlN (Fig. 4, 120 at far left stops above substrate 100 in layer 102 which may be AlN, 120 in center extends upwards and stops above substrate 100 in layer 104 which may also be AlN).
Claims 1, 2, 4, 11-13, and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsurumi et al. (US 2011/0175142), of record.
(Re Claim 1) Tsurumi teaches a structure comprising (see Fig. 1 and ¶¶29-41, 57):
a semiconductor substrate (11, 12, 13, 14);
a gate structure (23) over the semiconductor substrate;
a source region (region below source electrode 21) on a first side of the gate structure;
a drain region (region below drain electrode 22) on a second side of the gate structure; and
a thermal plug (33) extending from a top side of the semiconductor substrate into an active region (active layers 14, 13, 12) of the semiconductor substrate, the thermal plug comprising a conductive material (33A) lined with a dielectric material (33B), the conductive material being electrically isolated (33A is electrically isolated from the 2DEG, which is in the channel layer 13, ¶37, and at least locally, from the sidewalls of layers 13, 14, etc., and or 28, 27, etc. by the insulator 33B).
(Re Claim 2) further comprising ohmic contacts to the source region and the drain region, the thermal plug being electrically isolated from the ohmic contacts (if it is isolated from the 2DEG, ¶37, in the channel layer 13, then it must also be isolated from the S/D ohmic contacts that are connected to the 2DEG channel, ¶30).
(Re Claim 4) wherein the thermal plug is electrically isolated from a drain metal, and the dielectric material lines all sides of the conductive material (Fig. 1 and ¶57).
(Re Claim 11) Tsurumi teaches a structure comprising (see Fig. 1 and ¶¶29-41, 57):
a semiconductor substrate comprising a plurality of semiconductor materials (11, 12, 13);
a barrier layer (14 or 15 or 14+15) over the plurality of semiconductor materials;
a gate structure (23) over the semiconductor substrate;
at least one active regions (region(s) of layer 13/14) adjacent to the gate structure; and
a thermal plug (33) extending from a top side into the at least one active region adjacent to the gate structure, the thermal plug being electrically isolated from the at least one active region (Fig. 1, ¶37, isolated from the 2DEG channel).
(Re Claim 12) wherein the at least one active region comprises a drain region (region below 22).
(Re Claim 13) wherein the at least one active region comprises a source region (region below 21).
(Re Claim 15) wherein the thermal plug is a metal material (33A) fully lined on all sides with an insulator material (33B surrounding the sides, ¶37).
(Re Claim 16) wherein the thermal plug extends through the barrier layer (Fig. 1).
(Re Claim 17) wherein the thermal plug extends above the barrier layer (Fig. 1).
Claims 1, 7-8, 10-13, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kume et al. (US 2015/0060942), newly cited.
(Re Claim 1) Kume teaches a structure comprising (Fig. 12 and supporting text): a semiconductor substrate (SUB + SL + BUF, ¶¶50-52,83-89); a gate structure
(GE) over the semiconductor substrate; a source region (left side of device including SE) on a first side of the gate structure; a drain region (right side of device including DE) on a second side of the gate structure; and a thermal plug (MF) extending from a top side of the semiconductor substrate into an active region (SL and surrounding elements) of the semiconductor substrate, the thermal plug comprising a conductive material (MF) lined with a dielectric material (IF+ILD1), the conductive material being electrically isolated (Fig. 12).
(Re Claim 7) wherein the thermal plug comprises the metal material fully lined with the dielectric material, including a top surface which is lined with the dielectric material (IF+ILD1).
(Re Claim 8) wherein the semiconductor substrate comprises plural semiconductor materials comprising at least AlN, GaN, a superlattice material and an underlying semiconductor handle substrate (see ¶¶50-52,83-89).
(Re Claim 10) wherein the thermal plug stops above the underlying semiconductor handle substrate (SUB), extending through the GaN (SL) and the superlattice material (BUF) and stopping in the AlN (BUF, Fig. 12).
(Re Claim 11) Kume teaches a structure comprising (see Fig. 12 and supporting text): a semiconductor substrate comprising a plurality of semiconductor materials (SUB + SL1 + BUF, ¶¶50-52,83-89); a barrier layer (SL2) over the plurality of semiconductor materials; a gate structure (GE) over the semiconductor substrate; at least one active region adjacent to the gate structure (SL); and a thermal plug (MF) extending from a top side into the at least one active region adjacent to the gate structure, the thermal plug being electrically isolated from the at least one active region (Fig. 12, isolated: IF+ILD1).
(Re Claim 12) wherein the at least one active region comprises a drain region (right side including DE).
(Re Claim 13) wherein the at least one active region comprises a source region (left side including DE).
(Re Claim 15) wherein the thermal plug is a metal material (MF) fully lined on all sides with an insulator material (IF+ILD1).
(Re Claim 16) wherein the thermal plug extends through the barrier layer (Fig. 12).
(Re Claim 17) wherein the thermal plug extends above the barrier layer (Fig. 12).
(Re Claim 19) wherein the plurality of semiconductor materials comprises at least AlN, GaN, a superlattice material and an underlying semiconductor handle substrate (¶¶50-52,83-89), and the thermal plug extends, from the top side, into the AIN, the GaN and the superlattice material (layers BUF, SL1, SL2), and does not contact with the underlying semiconductor handle substrate (Fig. 12, MF does not contact SUB).
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kume et al. as applied above and further in view of Chu et al. (US 2019/0027426).
(Re Claim 2) further comprising contacts (SE/DE) to the source region and the drain region, the thermal plug (MF) being electrically isolated from the ohmic contacts (Fig. 12).
Kume is silent regarding ohmic contacts. A PHOSITA would be motivated to look to related art to teach further details of contacts, possible modifications and improvements thereof, where Kume is silent. Related art from Chu discloses forming ohmic contacts on the III-nitride HEMT device (¶39). Forming low-resistance ohmic source/drain (S/D) contacts to a III-nitride HEMT minimizes contact resistance and on-resistance, which maximizes device on-current, reduces power losses, and preserves high-frequency performance. A PHOSITA would find it obvious to form ohmic contacts for these known advantages in a HEMT device.
(Re Claim 4) wherein the thermal plug is electrically isolated from a drain metal and the dielectric material lines all sides of the conductive material (Fig. 12).
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant’s arguments regarding a feature cannot be “electrically isolated” if it is connected to any other conductive feature, are not commensurate with the claim language. The claim language does not require a particular or special degree of isolation with respect to other features, in fact claim 1 does not require isolation with respect to anything specifically. The thermal plug in claim 1 can be electrically isolated from parts of another transistor in another semiconductor device. A feature may be in contact with another conductive feature while still isolated from other conductive features. Also see §112 rejection above as the nature of the isolation and degree thereof are not clear, nor is the “active region” and corresponding isolation particularly clear in view of the specification, amended claims, and Applicant’s remarks. The rejections above have been updated in view of the amended claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related thermal plugs in semiconductor devices.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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