Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-26 are pending in this application.
Applicant elected without traverse Invention I (claims 1-15) in the reply filed on December 18, 2025.
Claims 16-23 remain withdrawn from further consideration.
Newly added claims 24-26 direct to the elected invention.
The Examiner notes that claims 1-15 and 24-26 are examined and claims 16-23 are withdrawn
Priority
Claims of priority to Taiwanese application TW 112128287, filed July 28, 2023, is acknowledged.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed April 8, 2026. Claims 1 and 5 are amended. Claims 16-23 remain withdrawn. Claims 24-26 are newly added. The Examiner notes that claims 1-15 and 24-26 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jong (US 2023/0260994 A1).
With respect to claim 1, Jong teaches in Fig. 5:
A semiconductor device, comprising:
a substrate (substrate 108) having a medium and high voltage device region (medium voltage device region 204 and high voltage device region 206);
a gate structure (gate electrodes 508 and/or 250),
wherein a portion of the gate structure is embedded in the medium and high voltage device region of the substrate (508 and 520 are embedded within 204 and 206);
an insulating layer (gate dielectric 510 and/or 518) disposed between the portion of the gate structure (208 and/or 520) and the substrate (108) and encompassing the portion of the gate structure (para. 51 “the gate dielectric 510 surrounding sidewalls of the gate electrode 508,” para. 52 “the gate dielectric 518 surrounding sidewalls of the gate electrode 520”); and two source/drain regions (S/D 212 which surrounds 508 or S/D 216 which surrounds 520) disposed in the substrate and respectively located at two sides of the gate structure (see Fig. 5).
With respect to claim 2, Jong further teaches:
wherein the insulating layer has a U-shaped profile (gate dielectrics 510 and 518 have a U-shaped cross section, see Fig. 5).
With respect to claim 3, Jong further teaches:
wherein a top surface of the insulating layer is aligned with a top surface of the substrate. (see Fig. 5)
With respect to claim 4, Jong further teaches:
wherein the insulating layer (510 or 518) comprises a first layer (horizontal portion along bottom of gate) and a second layer (slanted vertical portions on sidewalls of gate),
the first layer is disposed on a bottom surface of the gate structure,
and the second layer is disposed on a side surface of the gate structure (see Fig. 5).
With respect to claim 24, Jong further teaches:
wherein a depth of each of the two source/drain regions (212 or 216) in the substrate is greater than a depth of the gate structure (508 or 520) in the substrate (108) (see Fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-15, and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Jong (US 2023/0260994 A1) in view of Yang (US 2023/0154922 A1).
With respect to claim 5, Jong teaches:
A semiconductor device, comprising:
a substrate having a first region (low voltage device region 202) and a second region (medium voltage device region 204 and high voltage device region 206), wherein the first region is a low voltage device region, and the second region is a medium and high voltage device region;
a second gate structure (gate electrode 508) disposed in the second region (204 and 206), wherein a portion of the second gate structure is embedded in the substrate (508 is embedded in 108); and an insulating layer (gate dielectric 510) disposed between the portion of the second gate structure (508) and the substrate (108) and encompassing the portion of the second gate structure (para. 51 “with the gate dielectric 510 surrounding sidewalls of the gate electrode 508”).
Jong fails to teach:
a fin structure disposed in the first region;
a first insulating structure disposed in the first region and surrounding the fin structure, wherein a portion of the fin structure protrudes from the first insulating structure;
a first gate structure disposed in the first region and on the fin structure;
Yang teaches in Fig. 35:
a fin structure (semiconductor fins 32-LV’) disposed in the first region (low voltage device region 100-LV);
a first insulating structure (STI region 40 within region 100-LV) disposed in the first region (100-LV) and surrounding the fin structure (32-LV), wherein a portion of the fin structure protrudes from the first insulating structure (see Fig. 35, 32-LV’ protrudes above 40);
a first gate structure (gate electrode 116 within 100-LV) disposed in the first region (100-LV) and on the fin structure (32-LV’);
Claim 1 is rejected under the rationale “Combining Prior Art Elements According to Known Methods To Yield Predictable Results.” The Graham factual inquiries for this rationale are:
(1) a finding that the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference;
(2) a finding that one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately;
(3) a finding that one of ordinary skill in the art would have recognized that the results of the combination were predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Jong and Yang both teach devices that integrate low voltage, medium voltage, and high voltage transistors. Jong teaches all claimed elements related to the medium and high voltage regions in which the gate structure is embedded in the substrate and Yang teaches the claimed elements of the low voltage fin transistor. A person of ordinary skill in the art could have combined the medium and high voltage region transistors of Jong with the low voltage region transistor of Yang and each element would merely perform the same function that it does separately. The ordinary artisan would have recognized that integrating fin transistors into the low voltage region of Jong would have predictable results of allowing for flexibility of designing circuits with different operating voltages in a single device. As both Jong and Yang teach the integration of high and low voltage transistors together in the same device, the combination of known transistor architectures is an obvious design choice.
With respect to claim 6, Jong/Yang further teaches:
a second insulating structure (STI 220 within 206 of Jong, which is analogous to STI 40 within the medium and high voltage region 100-MV and 100-HV of Yang) disposed in the second region (204 of Jong, 100-MV/100-HV of Yang) and surrounding the second gate structure (208).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Jong in view of Yang as explained above.
With respect to claim 7, Yang further teaches:
wherein a height of the second insulating structure (height of 40 within 100-MV and 100-LV) is greater than a height of the first insulating structure (height of 40 between fins within 100-LV).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Jong in view of Yang as explained above.
With respect to claim 8, Yang teaches in Fig. 16 that the top surface of the fins is aligned with the top surface of the substrate in the high and medium voltage regions before the transistors of that region are formed. The transistor architecture in the medium and high voltage regions of Jong does not remove the top portions of the substrate in the high and medium voltage regions. Therefore, combining the teachings of Jong and Yang teaches:
wherein a top surface of the fin structure (32-LV of Yang)is aligned with a top surface of the substrate in the second region (top surface of source/drain region in 206 of Jong, which is formed in a mesa similar to that of region 100-HV of Yang but without removing all of the top surface of the substrate).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Jong in view of Yang as explained above.
With respect to claim 9, Yang further teaches:
wherein a top surface of the first gate structure (116 within 100-LV) is aligned with a top surface of the second gate structure (116 within 100-HV).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Jong in view of Yang as explained above.
With respect to claim 10, Jong/Yang does not teach:
wherein a bottom surface of the first insulating structure is aligned with a bottom surface of the insulating layer.
However, Jong/Yang differs from the invention as claimed only by a difference in shape and size of the first insulating structure. It would have been an obvious matter of design choice to design a bottom surface of the first insulating structure that is aligned with a bottom surface of the insulating layer, since such a modification would have involved a mere change in the size of component and the Examiner takes the position that changing the depth of an isolation structure is within the skills of the ordinary artisan and that changing the relative dimensions to meet the claim limitation would not lead to a functional difference to the prior art. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
With respect to claim 11, Jong further teaches:
wherein the insulating layer has a U-shaped profile (gate dielectrics 510 and 518 have a U-shaped cross section, see Fig. 5).
With respect to claim 12, Jong further teaches:
wherein a top surface of the insulating layer is aligned with a top surface of the substrate. (see Fig. 5)
With respect to claim 13, Jong/Yang further teaches:
wherein a structure of the first gate structure is different from a structure of the second gate structure (gate structures are different as they have different shapes, the first gate structure being a finFET gate structure, the second being embedded in the substrate),
or a material of the first gate structure is different from a material of the second gate structure.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Jong in view of Yang as explained above.
With respect to claim 14, Jong further teaches that it is known to make gate structures out of metal (para. [0050] “The metal gate electrode 502 may comprise tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), cobalt (Co), nickel (Ni) rubidium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN)”). It would be obvious to choose materials to meet the limitation:
wherein the first gate structure and the second gate structure comprise a metallic conductive material.
It would be obvious to further modify Jong/Yang with additional teachings of Jong to use metal gates because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 15, Jong further teaches that it is known to make gate structures out of non-metallic conductive material (para. [0055] “The gate electrodes 508 and 520 comprise polysilicon and have a thickness between approximately 700 angstroms and approximately 1000 angstroms.”):
wherein the first gate structure comprises a metallic conductive material, and the second gate structure comprises a non-metallic conductive material.
It would be obvious to further modify Jong/Yang with additional teachings of Jong to use non-metallic conductive gates because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 25, Jong further teaches:
further comprising: two source/drain regions (source/drain 212) disposed in the second region of the substrate (204) and respectively located at two sides of the second gate structure (508), wherein a depth of each of the two source/drain regions in the substrate is greater than a depth of the second gate structure in the substrate (see Fig. 5).
With respect to claim 26, the following limitation is a product by process limitation:
the first recess and the second recess are formed in the same process
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (MPEP 2113(I)).
The Examiner determines that the above limitation does not hold patentable weight, as there is no specific structure implied by the process.
Jong/Yang further teaches:
wherein the first insulating structure is disposed in a first recess formed in the first region of the substrate (para. [0029] of Yang “Trenches 36 are formed in semiconductor substrate 20 to separate the semiconductor strips 32.” The trenches are later filled with STI 40),
the insulating layer (510 if Jong) is disposed in a second recess formed in the second region of the substrate (para. [0074] “the high voltage gate structure 218 are recessed gate structures that are formed by etching the substrate 108 to form recesses, forming a gate dielectric 510 and 518 over the substrate 108”)
Jong/Yang does not teach:
and a bottom of the first recess is aligned with a bottom of the second recess.
However, Jong/Yang differs from the invention as claimed only by a difference in shape and size of the first insulating structure. It would have been an obvious matter of design choice to design a bottom surface of the first insulating structure that is aligned with a bottom surface of the insulating layer, since such a modification would have involved a mere change in the size of component and the Examiner takes the position that changing the depth of an isolation structure is within the skills of the ordinary artisan and that changing the relative dimensions to meet the claim limitation would not lead to a functional difference to the prior art. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 5 and their dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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