DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1 and 3-20 stand rejected under Section 102 in view of Kim. Claims 1 and 3-20 stand rejected under Section 103 in view of Kim and Xiang. Claim 2 stands rejected under Section 103 in view of Kim or Kim and Xiang and further in view of Yun. Claims 9, 10, 18, and 19 stand rejected under Section 103 in view of Kim and Xiang. Claims 7 and 16 stand rejected under Section 103 in view of Kim or Kim and Xiang and further in view of Zhang. Claims 4, 5, 13, and 14 stand rejected under Section 112(a) for lack of enablement for the full scope of the claims. Claims 11-19 stand rejected under Section 112(a) for lack of enablement. Claims 4, 5, 13, 14, and 20 stand rejected under Section 112(b). Claim 20 stands objected to for an informality.
Applicants amended claims 1 and 20, canceled claims 4, 5, and 11-19, and added new claim 21. Applicants argue that the application is in condition for allowance.
Turning first to claim objection: Applicants’ amendments address the previously noted claim objection and are accepted and entered. No new matter has been added. The previously noted claim objection is withdrawn.
Section 112(b) rejections: Applicants’ cancellation of claims 4, 5, 13, and 14 renders moot the Section 112(b) rejections of these claims. These rejections are withdrawn as moot. As for the Section 112(b) rejection of claim 20, applicants’ amendments address the previously noted Section 112(b) rejection and are accepted and entered. No new matter has been added. The previously noted Section 112(b) rejection of claim 20 is withdrawn.
Section 112(a) enablement and scope of enablement rejections: Applicants’ cancellation of claims 4, 5, and 11-19 renders moot the Section 112(a) rejections. These rejections are withdrawn as moot.
Section 102 rejections: Applicants’ amendments overcome the previously noted Section 102 rejections. These rejections are withdrawn.
Section 103 rejections: In the case of claims 1-3, 6-10, and 20, applicants’ amendments are either disclosed by the previously cited prior art, and/or are patentably insignificant shape variations over the prior art. Claim 21 is rejected using prior art that was identified in an earlier search, as discussed below.
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20, line 15: Change “physically” to “physical”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-10, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, U.S. Pat. Pub. No. 2019/0206995, Figures 1A-1C, 6A-16B.
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Regarding claim 1: Kim Figures 1A-1C and 6A-16B disclose a semiconductor device (100), comprising: a substrate (110); a channel region (CH) disposed in the substrate (110); a diffusion region (116, 116H) disposed in the substrate (110) on a side of the channel region (CH), wherein the diffusion region (116, 116H) comprises a lightly doped drain (LDD) region (116) (these regions are doped relatively lightly compared with the heavily doped regions (116H)) and a heavily doped region (116H) within the LDD region (116); a gate electrode disposed over the channel region, wherein the gate electrode (130) partially overlaps with the LDD region (116); a spacer (140) disposed on a sidewall of the gate electrode (130); a gate oxide layer (120GD and a portion of 120E2) disposed between the gate electrode (130) and the channel region (CH), between the gate electrode (130) and the LDD region (116), and between the spacer (140) and the LDD region (116); a gate oxide extension portion (remainder of 120E2) protruding from an edge of the spacer (140) and partially overlapping with the heavily doped region (116H); and a silicide layer (154) disposed on the heavily doped region (116H) not covered by the gate oxide extension portion (remainder of 120E2) and being spaced apart from the edge of the spacer (140). Kim specification ¶¶ 19-35, 67-104. Kim does not disclose wherein the gate oxide layer (120GD and the portion of 120E2) has only a single thickness between the gate electrode (130) and the channel region (CH), between the gate electrode (GE) and the LDD region (116), and between the spacer (140) and the LDD region (116). Instead, the thickness of the gate oxide layer between the gate electrode (130) and the channel region (CH) and between the gate electrode (GE) and the LDD region (116) is the same, with the gate oxide layer thickness between the spacer and the LDD region being smaller. However, the originally filed disclosure does not indicate that a uniform/single thickness in this location is patentably significant. Because the thickness is not patentably significant, the claim limitation is a patentably insignificant variation over the prior art, and thus, obvious.
Regarding claim 3, which depends from claim 1: Kim discloses that the gate oxide extension portion (120E2) is thinner than the gate oxide layer (120GD portion of 120GD/remainder of 120E2). Id. ¶¶ 77, 88. See also Kim Figure 1B.
Regarding claim 6, which depends from claim 1: Kim discloses the silicide layer (154) comprises nickel silicide or cobalt silicide. Id. ¶ 32 (cobalt silicide, nickel silicide, in list of silicides).
Regarding claim 7, which depends from claim 1: Kim discloses the gate electrode (130) comprises metal. See Kim specification ¶¶ 31, 32 (metal is portion of metal silicide (152) on gate electrode (130)).
Regarding claim 8, which depends from claim 1: Kim discloses the silicide layer (154) is contiguous with the gate oxide extension portion (120E2). See Kim Figure 1B.
Regarding claim 9, which depends from claim 1: Kim discloses the substrate is a silicon substrate (110) having a first conductivity type (through diffusion after annealing, after well (112) is implanted with p-type ions), and the channel region (CH) and the diffusion region (116) are disposed within an ion well (112) of the first conductivity type (p), wherein the heavily doped region (116H) and the LDD region (116) have a second conductivity type (n) opposite to the first conductivity type (p). Kim specification ¶¶ 22, 68-75, 93-96.
Regarding claim 10, which depends from claim 9: Kim discloses the first conductivity type is P type and the second conductivity type is N type. See id.
Regarding claim 20: Kim Figures 1A-1C and 6A-16B disclose a semiconductor device (100), comprising: a substrate (110); a channel region (CH) disposed in the substrate (110); a diffusion region (116, 116H) disposed in the substrate (110) on a side of the channel region (CH), wherein the diffusion region (116, 116H) comprises a lightly doped drain (LDD) region (116) (these regions are doped relatively lightly compared with the heavily doped regions (116H)) and a heavily doped region (116H) within the LDD region (116); a gate electrode (130) disposed over the channel region (CH), wherein the gate electrode (130) partially overlaps with the LDD region (116); a spacer (140) disposed on a sidewall of the gate electrode (130); a gate oxide layer (120GD, portion of 120E2) disposed between the gate electrode (130) and the channel region (CH), between the gate electrode (130) and the LDD region (116), and between the spacer (140) and the LDD region (116); and a silicide layer (154) disposed on the heavily doped region (116H) and being spaced apart from the edge of the spacer (140). Id. ¶¶ 19-35, 67-104. Kim does not disclose wherein the gate oxide layer (120GD, portion of 120E2) has an end sidewall surface that is vertically flush with an edge of the spacer (140), or that the silicide layer (154) is not in physically contact with the gate oxide layer (120GD, portion of 120E2). However, the originally filed disclosure does not indicate the patentable significance of the end sidewall surface of the gate oxide layer being vertically flush with an edge of the spacer or the silicide layer not being in physical contact with the gate oxide layer. Instead, the disclosure focuses on the silicide layer not being in physical contact with the spacer, and Kim discloses this separation between the spacer and the silicide layer. Because the claim requirements are not patentably significant, the limitations are patentably insignificant shape variations over the prior art. For these reasons, claim 20 is obvious.
Regarding claim 21: Kim Figure 1A-1C and 6A-16B disclose a semiconductor device (100), comprising: a substrate (110); a channel region (CH) disposed in the substrate (110); a diffusion region (116, 116H) disposed in the substrate (110) on a side of the channel region (CH), wherein the diffusion region (116, 116H) comprises a lightly doped drain (LDD) region (116) (these regions are doped relatively lightly compared with the heavily doped regions (116H)) and a heavily doped region (116H) within the LDD region (116); a gate electrode (130) disposed over the channel region (CH), wherein the gate electrode (130) partially overlaps with the LDD region (116); a spacer (140) disposed on a sidewall of the gate electrode (130); a gate oxide layer (120GD, portion of 120E2) disposed between the gate electrode (130) and the channel region (CH), between the gate electrode (GE) and the LDD region (116), and between the spacer (140) and the LDD region (116); a gate oxide extension portion (remainder of 120E2) protruding from an edge of the spacer (140) and partially overlapping with the heavily doped region (116H), and a silicide layer (154) disposed on the heavily doped region (116H) not covered by the gate oxide extension portion and being spaced apart from the edge of the spacer (140). Id. Kim does not disclose that the gate oxide extension portion (remainder of 120E2) has an asymmetric structure with respect to the gate electrode (130). However, the disclosure does not indicate the patentable significance of this feature. Instead, the feature results in a left-right asymmetric source/drain structure, which is not claimed in claim 21. Because the gate oxide extension portion having an asymmetric structure with respect to the gate electrode is a patentably insignificant shape variation, claim 21 is rejected as obvious.
Claims 1, 3, 6-10, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, and further in view of Xiang, U.S. Pat. Pub. No. 2021/0233924, Figures 1-8.
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Regarding claim 1: To the extent that Kim’s source/drain regions (116) are not considered LDD regions, although they have lower doping than highly doped regions (116H), Xiang, directed to similar subject matter, discloses that its source/drain regions (136) may include LDD regions. Xiang specification ¶ 30. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim to include the Xiang LDD regions because the modification would have involved the substitution of an equivalent known for the same purpose.
The rejections of claims 3 and 6-10 are incorporated by reference.
Regarding claim 20: To the extent that Kim’s source/drain regions (116) are not considered LDD regions, although they have lower doping than highly doped regions (116H), Xiang, directed to similar subject matter, discloses that its source/drain regions (136) may include LDD regions. Xiang specification ¶ 30. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim to include the Xiang LDD regions because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 21: To the extent that Kim’s source/drain regions (116) are not considered LDD regions, although they have lower doping than highly doped regions (116H), Xiang, directed to similar subject matter, discloses that its source/drain regions (136) may include LDD regions. Xiang specification ¶ 30. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim to include the Xiang LDD regions because the modification would have involved the substitution of an equivalent known for the same purpose.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim or Kim and Xiang, and further in view of Yun, U.S. Pat. Pub. No. 2020/0303508, Figure 1.
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Regarding claim 2, which depends from claim 1: Kim is silent as to the materials of its spacer (140).
Yun Figure 1, directed to similar material, discloses the gate spacer (SP1, SP2, SP3, SP4) can be silicon nitride. Yun specification ¶¶ 18, 29. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim or Kim and Xiang to use the Yun gate spacer material because the modification would have involved a selection of a known material based on its suitability for its intended use.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, and further in view of Xiang, or Kim and Xiang.
Regarding claim 9, which depends from claim 1: To the extent that the process of annealing, which occurs after implantation, would not be considered to be sufficient to change the Kim silicon substrate into a silicon substrate of a first conductivity, Xiang, directed to similar subject matter, uses a p-type (first conductivity) substrate (100) for implantation of various regions during transistor fabrication. Xiang specification ¶¶ 20-30. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim to use the Xiang substrate because the modification would have involved a selection of a known material based on its suitability for its intended use.
The rejection of claim 10 is incorporated by reference.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim or Kim and Xiang, and further in view of Zhang, U.S. Pat. Pub. No. 2013/0181287, Figure 1a, 2d-2f.
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Regarding claim 7, which depends from claim 1: To the extent that Kim does not disclose that the gate electrode comprises metal, Zhang, directed to similar subject matter, discloses a gate electrode that can be polysilicon or a metal. Zhang specification ¶¶ 59, 60. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim or Kim and Xiang to use the Zhang gate metal electrode because the modification would have involved a selection of a known material based on its suitability for its intended use.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Victoria K. Hall/Primary Examiner, Art Unit 2897