DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 23, 2026 has been entered.
Response to Arguments
Claims 1-10, 20, and 21 stand rejected under Section 103. Claim 20 stands objected to for an informality. Claims 4, 5, and 11-19 were previously canceled.
Applicants canceled claims 20 and 21, and argue that claim 1 is allowable over the prior art.
As a preliminary matter, the thinner gate oxide extension portion that protrudes from an edge of the spacer—a claim requirement that is supported by the originally filed disclosure—is not shown in any of the drawings. If this feature is patentably significant, then the feature must be shown in the drawings. A drawing objection is included, below.
Next, Section 103 rejections: Applicants make two arguments in support of their contention that the requirement for a single thickness between the gate electrode and the channel region, between the gate electrode and the LDD region, and between the spacer and the LDD region is patentably significant: uniform dielectric strength and process simplification. Amendment and Request for Continued Examination [hereinafter Amendment], at 7. In addition, applicants argue that by requiring the silicide layer to be spaced apart from the edge of the spacer by the thinner protruding extension portion, the claimed device prevents silicide encroachment and voids without sacrificing uniform dielectric thickness under the spacer. Id.
As to the last point, the Kim silicide layer (154) is spaced apart from the edge of the Kim spacer (140) in Kim Figure 1A. See Kim Figure 1B. Thus, Kim also prevents silicide encroachment and voids.
Regarding applicants’ argument with respect to uniform dielectric strength: the Kim gate oxide layer (120GD) and the Kim gate oxide extension portion (120E2) are made insulating film pattern (120P) which may include a silicon oxide film. Kim specification ¶ 29. Kim is silent as to the materials of the spacer, but a common spacer material is silicon oxide. See Chen, U.S. Pat. Pub. No. 2002/0192913, Figures 2A-2C, Chen specification ¶¶ 30 (gate oxide is silicon oxide), 41 (spacer is silicon oxide). If the materials of the gate oxide and spacer are the same, then the device would have uniform dielectric strength.
Regarding applicants’ argument with respect to process simplification: The claims are directed to a product, not a method. Therefore, unless there is a specific benefit that appears in the product because of the process that was used, the process by which a product is made has not patentable weight. The burden is on applicants to show that the process by which the product is made is patentably significant. A product-by-process claim is directed to the product per se, not the process by which the product is made. In re Hirao, 190 USPQ 15 at 17 n. 3 (CCPA 1976). See also In re Brown, 173 USPQ 685, 688 (CCPA 1972); In re Luck, 177 USPQ 523, 525 (CCPA 1973); In re Fessman, 180 USPQ 324, 325-26 (CCPA 1974); In re Avery, 186 USPQ 161, 166-67 (CCPA 1975); In re Wertheim, 191 USPQ 90, 103 (CCPA 1976); and In re Marosi, 218 USPQ 289, 292-93 (Fed. Cir. 1983), all of which make it clear that it is the patentability of the final product per se which must be determined in a product-by-process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product-by-process claims or not. Note that the applicant has the burden of proof in such cases, according to case law.
The Office notes that Kim discloses in its Figure 2 an embodiment in which the gate oxide layer (120GD) is a single thickness between the gate electrode (130) and the channel region (CH), between the gate electrode (130) and the LDD region (116), and between a portion of the spacer (140) and the LDD region (116).
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The Office also notes Watanabe, U.S. Pat. No. 6,200,846, Figures 1A-4C, which shows a gate insulating layer (5P or 5N) having a single thickness between the gate electrode (6b or 6c) and the channel region (4P or 4N), between the gate electrode (6b or 6c) and the LDD region (25P or 25N), and between the spacer (23b or 23c) and the LDD region (25P or 25N). Watanabe specification, col. 4, l. 28 – col. 8, l. 62.
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To the extent that Kim Figure 2’s gate oxide layer is insufficient to meet the claim limitation—that is, the claim limitation requires the single thickness to be along the entire interface of the spacer and the LDD region, then Kim notes that the position of step ST2 can be adjusted, and Watanabe discloses the formation of a gate insulation layer (5P or 5N) that has the claimed single thickness, as discussed above, and can be combined with Kim to render obvious claim 1 because the modification would have involved the substitution of an equivalent known for the same purpose.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the gate oxide extension portion that is thinner than the gate oxide layer of claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, U.S. Pat. Pub. No. 2019/0206995, Figures 1A-1C, 6A-16B, and 2, and further in view of Chen, U.S. Pat. Pub. No. 2002/0192913, Figures 2A-2C, and Watanabe, U.S. Pat. No. 6,200,846, Figures 1A-4C.
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Chen, Figures 2A-2C:
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Watanabe, Figures 1A-2B:
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Watanabe, Figures 3A-4C:
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Regarding claim 1: Kim Figures 1A-1C, 2, and 6A-16B disclose a semiconductor device (100), comprising: a substrate (110); a channel region (CH) disposed in the substrate (110); a diffusion region (116, 116H) disposed in the substrate (110) on a side of the channel region (CH), wherein the diffusion region (116, 116H) comprises a lightly doped drain (LDD) region (116) (these regions are doped relatively lightly compared with the heavily doped regions (116H)) and a heavily doped region (116H) within the LDD region (116); a gate electrode disposed over the channel region, wherein the gate electrode (130) partially overlaps with the LDD region (116); a spacer (140) disposed on a sidewall of the gate electrode (130); a gate oxide layer (120GD and a portion of 120E2) disposed between the gate electrode (130) and the channel region (CH), between the gate electrode (130) and the LDD region (116), and between the spacer (140) and the LDD region (116); a gate oxide extension portion (remainder of 120E2) protruding from an edge of the spacer (140) and partially overlapping with the heavily doped region (116H); and a silicide layer (154) disposed on the heavily doped region (116H) not covered by the gate oxide extension portion (remainder of 120E2) and being spaced apart from the edge of the spacer (140). Kim specification ¶¶ 19-35, 67-104. Kim does not disclose wherein the gate oxide layer (120GD and the portion of 120E2) has only a single thickness between the gate electrode (130) and the channel region (CH), between the gate electrode (GE) and the LDD region (116), and between the spacer (140) and the LDD region (116). Instead, the thickness of the gate oxide layer between the gate electrode (130) and the channel region (CH) and between the gate electrode (GE) and the LDD region (116) is the same, with the gate oxide layer thickness between the spacer and the LDD region being smaller. However, the originally filed disclosure does not indicate that a uniform/single thickness in this location is patentably significant. Because the thickness is not patentably significant, the claim limitation is a patentably insignificant variation over the prior art, and thus, obvious.
In the alternative, as discussed in the Response to Arguments section, Kim discloses the gate oxide layer (120GD and a portion of 120E) is a silicon oxide, but is silent as to the material of the spacer (140). Chen Figures 2A-2C, directed to similar subject matter, discloses that the gate insulation layer is silicon oxide and the spacer is silicon oxide. Chen specification ¶¶ 31, 40. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim to use the Chen SiO spacer because the modification would have involved a selection of a known material based on its suitability for its intended use. Once combined, the combination of the gate oxide layer and the spacer would result in the benefit that applicants say exist because the combined thickness of the gate oxide layer and the spacer would be the same in the Kim-Chen product as in applicants’ product.
In the alternative, as discussed in the Response to Arguments section, Kim Figure 2 discloses an embodiment in which the gate oxide layer (120GD and a portion of 120E) has the same thickness (at 120GD under spacer (140)) as a thickness of the gate oxide layer (120GD) between the gate electrode (140) and the channel (CH) and between the gate oxide layer (120GD) and the LDD region (116). Kim specification ¶¶ 36-39. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim Figures 1A-1C and 6A-16B to include the Kim Figure 2 design because the modification would have involved the substitution of an equivalent known for the same purpose.
Lastly, in the alternative, as discussed in the Response to Arguments section, if the claim is interpreted to require a same thickness throughout the entirety of the interface between the spacer and the LDD region, then Watanabe discloses a gate insulating layer (5P or 5N) having a single thickness between the gate electrode (6b or 6c) and the channel region (4P or 4N), between the gate electrode (6b or 6c) and the LDD region (25P or 25N), and between the spacer (23b or 23c) and the LDD region (25P or 25N). Watanabe specification, col. 4, l. 28 – col. 8, l. 62. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim Figures 1A-1C, 6A-16B, and 2 to include the Watanabe design because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 3, which depends from claim 1: Kim discloses that the gate oxide extension portion (120E2) is thinner than the gate oxide layer (120GD portion of 120GD/remainder of 120E2). Id. ¶¶ 77, 88. See also Kim Figures 1B, 2.
Regarding claim 6, which depends from claim 1: Kim discloses the silicide layer (154) comprises nickel silicide or cobalt silicide. Id. ¶ 32 (cobalt silicide, nickel silicide, in list of silicides).
Regarding claim 7, which depends from claim 1: Kim discloses the gate electrode (130) comprises metal. See Kim specification ¶¶ 31, 32 (metal is portion of metal silicide (152) on gate electrode (130)).
Regarding claim 8, which depends from claim 1: Kim discloses the silicide layer (154) is contiguous with the gate oxide extension portion (120E2). See Kim Figure 1B.
Regarding claim 9, which depends from claim 1: Kim discloses the substrate is a silicon substrate (110) having a first conductivity type (through diffusion after annealing, after well (112) is implanted with p-type ions), and the channel region (CH) and the diffusion region (116) are disposed within an ion well (112) of the first conductivity type (p), wherein the heavily doped region (116H) and the LDD region (116) have a second conductivity type (n) opposite to the first conductivity type (p). Kim specification ¶¶ 22, 68-75, 93-96.
Regarding claim 10, which depends from claim 9: Kim discloses the first conductivity type is P type and the second conductivity type is N type. See id.
Claims 1, 3, and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Chen, and Watanabe, and further in view of Xiang, U.S. Pat. Pub. No. 2021/0233924, Figures 1-8.
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Regarding claim 1: To the extent that Kim’s source/drain regions (116) are not considered LDD regions, although they have lower doping than highly doped regions (116H), Xiang, directed to similar subject matter, discloses that its source/drain regions (136) may include LDD regions. Xiang specification ¶ 30. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim or Kim, Chen, and Watanabe, to include the Xiang LDD regions because the modification would have involved the substitution of an equivalent known for the same purpose.
The rejections of claims 3 and 6-10 are incorporated by reference.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, or Kim, Chen, and Watanabe, or Kim and Xiang, and further in view of Yun, U.S. Pat. Pub. No. 2020/0303508, Figure 1.
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Regarding claim 2, which depends from claim 1: Kim is silent as to the materials of its spacer (140).
Yun Figure 1, directed to similar material, discloses the gate spacer (SP1, SP2, SP3, SP4) can be silicon nitride. Yun specification ¶¶ 18, 29. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim, or Kim, Chen, and Watanabe, or Kim and Xiang to use the Yun gate spacer material because the modification would have involved a selection of a known material based on its suitability for its intended use.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim or Kim, Chen, and Watanabe, or Kim and Xiang, and further in view of Zhang, U.S. Pat. Pub. No. 2013/0181287, Figure 1a, 2d-2f.
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Regarding claim 7, which depends from claim 1: To the extent that Kim does not disclose that the gate electrode comprises metal, Zhang, directed to similar subject matter, discloses a gate electrode that can be polysilicon or a metal. Zhang specification ¶¶ 59, 60. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim or Kim and Xiang to use the Zhang gate metal electrode because the modification would have involved a selection of a known material based on its suitability for its intended use.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim or Kim, Chen, and Watanabe, and further in view of Xiang, or Kim and Xiang.
Regarding claim 9, which depends from claim 1: To the extent that the process of annealing, which occurs after implantation, would not be considered to be sufficient to change the Kim silicon substrate into a silicon substrate of a first conductivity, Xiang, directed to similar subject matter, uses a p-type (first conductivity) substrate (100) for implantation of various regions during transistor fabrication. Xiang specification ¶¶ 20-30. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kim to use the Xiang substrate because the modification would have involved a selection of a known material based on its suitability for its intended use.
The rejection of claim 10 is incorporated by reference.
Conclusion
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/Victoria K. Hall/Primary Examiner, Art Unit 2897
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