The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse the embodiment of figure 24 in the reply filed on 03/03/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the source/drain regions must be shown with numerals in the recess or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (11,227,917) in view of Kim et al. (2020/0294995).Regarding claim 1, Chung et al. teach in figure 18C and related text a semiconductor device structure, comprising:
a source/drain (S/D) feature 262A, 262B disposed in a recess between two adjacent channel regions, wherein the S/D feature comprises an epitaxial layer 215/210 conformally deposited on an exposed surface of the recess;
a silicide layer 290 conformally disposed on the S/D feature 262A, 262B; and
a S/D contact 292 disposed on the silicide layer 290, wherein the S/D contact 292 has a first portion extending into the recess (since the recess extend to the top of the structure, see figure 13C), and the first portion has at least three surfaces being surrounded by the silicide layer and the S/D feature.
Chung et al. do not teach that the first portion of the S/D contact 292 has at least three surfaces being surrounded by the silicide layer and the S/D feature.
Kim et al. teach in figure 20 and related text a first portion of the S/D contact 150 penetrates the S/D feature 130, such that the first portion of the S/D contact 150 has at least three surfaces being surrounded by the S/D feature 130.
Chung et al. and Kim et al. are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chung et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a first portion of the S/D contact fully penetrates the S/D feature, as taught by Kim et al., such that the first portion of the S/D contact has at least three surfaces being surrounded by the S/D feature and to surround the first portion the silicide layer, in Chung et al.’s device, in order to improve the contact resistance of the device since it well-known in the art that silicide also reduces the contact resistance of the device.
Regarding claim 2, in the combined device, Chung et al. teach in figure 18C and related text that the S/D contact further comprises: a second portion (arbitrarily chosen) disposed over the first portion, wherein the second portion is extended between two adjacent gate structures 284.
Regarding claim 3, Chung et al. teach in figure 18C and related text that the epitaxial layer 262A has a top surface at an elevation that is equal to or greater than a top surface of at least one channel region 215.
Regarding claim 4, Chung et al. teach in figure 18C and related text that the S/D feature has a general U-shaped profile.
Regarding claim 5, in the combined device, the silicide layer has a general U-shaped profile.
Regarding claim 6, Chung et al. teach in figure 18C and related text that the epitaxial layer has n-type or p-type dopants distributed constantly or gradually along a thickness of the epitaxial bottom layer.
Regarding claim 7, Chung et al. teach in figure 18C and related text that the epitaxial layer is a semiconductor layer having an atomic percentage of germanium, but do not teach that the atomic percentage of germanium is in a range of about 40 at.% to about 60 at.%.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the atomic percentage of germanium in a range of about 40 at.% to about 60 at.%, in Chung et al.’s device, in order to optimize the device characteristics.
Regarding claim 8, Chung et al. teach in figure 18C and related text a plurality of semiconductor layers 205 (see figure 8D) stacked vertically over a substrate 202; a gate electrode layer 284 surrounding a portion of each semiconductor layer; a gate dielectric layer 282 disposed between the gate electrode layer and each semiconductor layer; a source/drain (S/D) epitaxial layer 262A, 262B in contact with each of the plurality of semiconductor layers; and a S/D contact 292 extending in a direction across a sidewall surface of each of the plurality of semiconductor layers.
Chung et al. do not teach that a bottom of the S/D contact is at an elevation below an interface defined by the substrate 202/261B and the gate dielectric layer 282.
Kim et al. teach in figure 20 and related text that the S/D contact 150 penetrates the S/D feature 130.
Chung et al. and Kim et al. are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chung et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the S/D contact to fully penetrate the S/D feature, as taught by Kim et al., such that a bottom of the S/D contact is at an elevation below an interface defined by the substrate 202/261B and the gate dielectric layer 282, in Chung et al.’s device, in order to improve the contact resistance of the device.
Regarding claim 9, in the combined device, Chung et al. teach in figure 18C and related text that a silicide layer (in the combined device) disposed between and in contact with the S/D contact and the S/D epitaxial layer.
Regarding claim 10, in the combined device, Chung et al. teach in figure 18D and related text that a contact etch stop layer (CESL) 270 disposed over the S/D epitaxial layer 260B; wherein a portion of the silicide layer is disposed between the S/D epitaxial layer and the CESL (since the silicide layer in the combined device surrounds the S/D epitaxial layer).
Regarding claims 11 and 12, the claimed limitations of a sacrificial layer disposed between and in contact with the CESL and the silicide layer, and wherein the sacrificial layer has a curved surface, and a portion of the S/D contact is extended into and in contact with the curved surface of the sacrificial layer these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
The formation of a sacrificial layer means that said layer is removed from the final structure and thus does not produce a different final structure.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding claim 13, in the combined device, Chung et al. teach in figure 18C and related text that the S/D epitaxial layer has a general U-shaped profile.
Regarding claim 14, in the combined device, Chung et al. teach in figure 18C and related text that the S/D contact 292 has a general T-shaped profile.
Regarding claim 15, in the combined device, Chung et al. teach in figure 18C and related text that the S/D epitaxial layer has an outer surface in contact with each of the plurality of semiconductor layers, and an inner surface formed with a wavy profile (since Chung et al. do not perform a CMP on the inner surface).
Regarding claim 16, in the combined device, Chung et al. teach in figure 18C and related text that a dielectric spacer 255 disposed between two adjacent semiconductor layers and in contact with the gate dielectric layer 282 and a portion of the S/D contact.
Regarding claim 21, Chung et al. teach in figure 18C and related text a plurality of semiconductor layers 205 (see figure 8D) stacked vertically over a substrate 202; a gate electrode layer 284 surrounding a portion of each semiconductor layer; a gate dielectric layer 282 disposed between the gate electrode layer and each semiconductor layer;
a source/drain (S/D) epitaxial feature 262A, 262B disposed adjacent the plurality of semiconductor layers, the S/D epitaxial feature comprising: an epitaxial bottom layer conformally disposed on exposed surfaces of the plurality of semiconductor layers and having a generally U-shaped profile; an etch stop layer 270 conformally disposed on and in direct contact with the epitaxial bottom layer 60B (see figure 18D); and a source/drain (S/D) contact disposed in a recess (since the recess extend to the top of the structure, see figure 13C).
Chung et al. do not teach that a bottom of the S/D contact is at an elevation below an interface between the substrate and the gate dielectric layer.
Kim et al. teach in figure 20 and related text that the S/D contact 150 penetrates the S/D feature 130.
Chung et al. and Kim et al. are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chung et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the S/D contact to fully penetrate the S/D feature , as taught by Kim et al., such that a bottom of the S/D contact is at an elevation below an interface between the substrate and the gate dielectric layer, in Chung et al.’s device, in order to improve the contact resistance of the device.
Regarding the claimed limitation of “a sacrificial layer disposed on and in direct contact with the etch stop layer and extending laterally beyond the epitaxial bottom layer to form a generally T- shaped profile; and a source/drain (S/D) contact disposed in a recess defined by removal of the sacrificial layer”, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
The formation of a sacrificial layer means that said layer is removed from the final structure and thus does not produce a different final structure.
Regarding claim 22, Chung et al. teach in figure 18C and related text that the recess has a curved surface, and the S/D contact extends into the recess and contacts (at least electrical contact) the curved surface.
Regarding claim 23, Chung et al. teach in figure 18C and related text a contact etch stop layer (CESL) 270 disposed over the S/D epitaxial layer 260B, wherein a portion of the etch stop layer (part of 270) is disposed between the epitaxial bottom layer and the CESL.
Regarding claim 24, Regarding the claimed limitation of “the sacrificial layer has a germanium concentration greater than a germanium concentration of the etch stop layer”, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
The formation of a sacrificial layer means that said layer is removed from the final structure and thus does not produce a different final structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
3/17/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800