DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/16/24, 10/1/24, 3/26/25 and 12/14/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 through 9 and 11 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim claims 1 through 9 and 11 of copending Application No. 18/140,085 in view of Kato (US 2012/0313094).
Patent application 18/140,185 claims 1 through 9 and 11 encompass each of claims 1 through 9 and 11 of application 18/140,085, However, 18/140,185 does not recite a plurality of die regions. Kato teaches a plurality of die regions (2a,2b,2c,2d) with a scribe line (3) disposed between the plurality of die regions (figure 1,2a) (paragraph 36)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to provide a plurality of die regions in order that multiple die can be made from a wafer using the dicing process on the scribe lines.
18/239,231
18/140,085
1. A semiconductor device, comprising: a plurality of die regions, disposed on a semiconductor wafer; a scribe line region, disposed between the plurality of die regions; and a plurality of circuit probing pads, disposed on a first top surface of each die region and a second top surface of the scribe line region.
1: A scribe line structure, comprising: a die region, disposed on a semiconductor wafer; a scribe line region, surrounding the die region to define a boundary between the die region and the scribe line region, and a safe margin between a center line of the scribe line region and the boundary; and one or more circuit probing pads, disposed on a first top surface of the die region and a second top surface of the scribe line region and disposed on the boundary to define a first portion of each circuit probing pad on the first top surface of the die region and a second portion of each circuit probing pad on the second top surface of the scribe line region, wherein the second portion of each circuit probing pad is disposed within the safe margin and is spaced apart from the center line of the scribe line region;
wherein the scribe line region further has a dicing path aligned with the center line of the scribe line region, wherein the dicing path is spaced apart from the second portions of the one or more circuit probing paths.
2. The semiconductor device of claim 1, wherein each die region comprises functional circuitry, and the scribe line region is a non-functional region.
2 : The scribe line structure of Claim 1, wherein the die region comprises functional circuitry, and the scribe line region is a non-functional region.
3. The semiconductor device of claim 2, wherein a portion of each circuit probing pad is electrically connected to the functional circuitry of each die region.
Claim 3: The scribe line structure of Claim 2, wherein the first portion of each circuit probing pad is electrically connected to the functional circuitry of the die region.
4. The semiconductor device of claim 3, wherein the functional circuitry of each die region is tested via a plurality of circuit probing needles electrically connected to external test equipment and placed on the one or more circuit probing pads.
5. The semiconductor device of claim 1, wherein a center of each circuit probing pad is disposed on a boundary between each die region and the scribe line region.
Claim 4: The scribe line structure of Claim 3, wherein the functional circuitry of the die region is tested via one or more circuit probing needles electrically connected to external test equipment and placed on the one or more circuit probing pads.
5: The scribe line structure of Claim 1, wherein a center of each circuit probing pad is disposed on and aligned with the boundary between the die region and the scribe line region.
6. The semiconductor device of claim 1, wherein a center of each circuit probing pad is disposed away from each die region with reference to a center line of the scribe line region.
6: The scribe line structure of Claim 1, wherein a center of each circuit probing pad is disposed away from the die region with reference to the center line of the scribe line region.
7. The semiconductor device of claim 1, wherein a center of each circuit probing pad is disposed closer to each die region with reference to a center line of the scribe line region.
7: The scribe line structure of Claim 1, wherein a center of each circuit probing pad is disposed closer to the die region with reference to the center line of the scribe line region.
8. The semiconductor device of claim 4, wherein a dicing process is performed on the semiconductor wafer along one or more dicing paths defined on the scribe line region, and a portion of each circuit probing pad is diced from the semiconductor wafer.
8: The scribe line structure of Claim 4, , wherein the semiconductor wafer is diced along the dicing path to dice the scribe line region from the die region and to form a diced portion of the scribe line region and a remaining portion of the scribe line region attached to the die region, wherein the second portion of each circuit probing pad is concurrently diced to form a remaining circuit probing pad remaining on the remaining portion of the scribe line region and the die region.
9. The semiconductor device of claim 8, wherein the die region and a remaining scribe-line structure are packaged into a semiconductor chip package.
9: The scribe line structure of Claim 8, wherein the die region and the remaining portion of the scribe line region with each remaining circuit probing pad are packaged into a semiconductor chip package.
11. The semiconductor device of claim 7, wherein each die region is electrically connected to a substrate via wire bonding.
11: The scribe line structure of Claim 1, wherein the die region is electrically connected to a substrate via wire bonding.
This is a provisional nonstatutory double patenting rejection.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: figure 3c comprises element: 3312, designating the space between the center (3311) of the pad (331) and the edge of the pad (331), however element 3312 is not present in the specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 through 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 6159826) in view of Kato (US 2012/0313094)
Regarding claim 1.
Kim teaches a semiconductor device, comprising: a […] die region (fig 5:32[column 3 lines 25-30]), disposed on a semiconductor wafer (fig 5:51[column 3 lines 25-50]); a scribe line region (fig 5:34{column 3 lines 25-30]),[…] disposed between the plurality of die regions; and a […] circuit probing pad (fig 5:56[column 3 lines 35-40]) , disposed on a first top surface of each die region (fig 5:32[column 3 lines 45-50]) and a second top surface of the scribe line region (fig 5:34[column 3 lines 45-50]).
Kim does not teach a plurality of die regions and a plurality of probing pads.
Kato teaches a semiconductor device, comprising: a plurality of die regions (fig 21b:2a,2b[0164]), disposed on a semiconductor wafer (fig 19:100[0164]); a scribe line region (fig 21b:3[0036]), disposed between the plurality of die regions (fig 21b:2a,2b[0164]); and a plurality of circuit probing pads (fig 21b:9a-9b[0161]), disposed on […] a second top surface of the scribe line region. (fig 19,21b:3[0163])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of die regions in order that multiple die can be taken from one wafer thereby improving production, and a plurality of pads will enabling more tests to be performed on more die.
Regarding claim 2, Kim in view of Kato teaches the semiconductor device of claim 1.
Kim teaches each die region (fig 5:32[column 3 lines 25-30]) comprises functional circuitry (fig 5:[column 3 lines 25-35]), and the scribe line region (fig 5:34[column 3 lines 25-30])is a non-functional region.
Regarding claim 3, Kim in view of Kato teaches the semiconductor device of claim 2.
Kim teaches a portion (fig 5:56a[column 3 lines 40-45]) of each circuit probing pad (fig 5:56[column 3 lines 35-44]) is electrically connected to the functional circuitry of each die region (fig 5:32[column 3 lines 25-30]).
Regarding claim 4, Kim in view of Kato teaches the semiconductor device of claim 3.
Kim teaches the functional circuitry of each die region (fig 5:32[column 3 lines 25-30]) is tested via a plurality of circuit probing needles (fig 5:60 [column 3 lines 50-55]) electrically connected to external test equipment and placed on the one or more circuit probing pads (fig 5:56[column 3 lines 335-40]).
The limitation must distinguish from the prior art in terms of structure rather than function, In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Regarding claim 5, Kim in view of Kato teaches the semiconductor device of claim 1.
Kim teaches a center of each circuit probing pad (fig 5:56[column 3 lines 25-30]) is disposed on a boundary between each die region (fig 5:32[column 3 lines 25-30]) and the scribe line region (fig 5:34[column 3 lines 25-30]).
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Regarding claim 6, Kim in view Kato teaches the semiconductor device of claim 1.
Kato teaches a center of each circuit probing pad (fig 21a:9a-9d[0162]) is disposed away from each die region (fig 21a:2a[0161]) with reference to a center line of the scribe line region (fig 21a:3[0161]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to move the pad center relative to the scribe line center and die region in order to optimize the dicing properties and test probe configuration.
Regarding claim 7, Kim in view of Kato teaches the semiconductor device of claim 1.
Kato teaches a center of each circuit probing pad (fig 21b:9a-9b[0164]) is disposed closer to each die region (fig 21b:2a[0164]) with reference to a center line of the scribe line region (fig 21b:4[0164]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to move the pad center relative to the scribe line center and die region in order to optimize the dicing properties and test probe configuration.
Regarding claim 8, Kim in view of Kato teaches semiconductor device of claim 4.
Kato teaches a dicing process (fig 6:S140:[0086]) is performed on the semiconductor wafer (fig 19:100[0035]) along one or more dicing paths (fig 21b:4[0164]) defined on the scribe line region (fig 21b:3[0036]), and a portion of each circuit probing pad (fig 21b:9a-9d[0164]) is diced from the semiconductor wafer (fig 19:100[0035]).
Note that a “product by process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and related case law cited therein which make it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe,
Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington. 411 F2d 1345, 1348, 162 USPQ 145, 147, (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir 1935).
Note that Applicant bears the burden of proof in such cases as the above case law makes clear.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 6159826) in view of Kato (US 2012/0313094) as applied to claim 8 and further in view of Uehling (US 2013/0299947)
Regarding claim 9, Kim in view of Kato teaches semiconductor device of claim 8.
Kim in view of Kato does not teach a chip package.
Uehling teaches the die region (fig 3:110[0012]) and a remaining scribe-line structure (fig 3:122[0012]) are packaged into a semiconductor chip package (fig 3:264[0019]).
It would have been obvious to one of ordinary skill in the art to provide the singulated die in a die package in order to protect the die and provide external connections in order to facilitate further assembly.
Regarding claim 10, Kim in view of Kato in view of Uehling teaches the semiconductor device of claim 9.
Kato teaches
the semiconductor chip […] further comprises a remaining circuit probing pad corresponding to each circuit probing pad (fig 21b:9a-9d[0164]) obtained after the dicing process (fig 6:s140[0086]).
Ueling teaches the semiconductor chip package (fig 3:264[0019]) […] after the dicing process (fig 3:212[0018]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 6159826) in view of Kato (US 2012/0313094) as applied to claim 7 and further in view of Uehling (US 2013/0299947)
Regarding claim 11, Kim in view of Kato teaches the semiconductor device of claim 7 above.
Kim in view of Kato does not teach wire bonding.
Uehling teaches each die region(fig 3:110[007]) is electrically connected to a substrate (fig 3:266[0019]) via wire bonding [fig 3[0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to wire bond the die to a substrate in order to facilitated the transmission of external power and signal to the internal structure of the die.
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 16, 2026