DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/10/2026 has been entered.
Claim Status
Previous rejection: claims 1 through 11 rejected.
Present rejection: claims 1 through 5 and 8 through 11 are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 5 and 9 through 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a center line of the scribe line region is between a center of each of the circuit probing pads and the corresponding die region” in lines 18 and 19.
This statement is unclear and ambiguous, it is unclear how the center line (123) of the scribe line region (d) can be between the center of the pad (3311) and the die region (110) when a portion of the pad is on the die region (fig 3b, paragraph 33)
The examiner will assume that the applicant intended the center of the pad to be between the center of the scribe line region and the corresponding die region, as is illustrated in the figures. The examiner suggests “a center of each of the circuit probing pads line of the scribe line region and the corresponding die region”
If the limitation is stated correctly then this limitation must be included in the figures.
Claims 2 through 5 and 8 through 11 are rejected as depending on and incorporating claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are interpreted based on the applicant’s disclosure, underlined limitations indicate the interpretation that the examiner is using.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Nakamura (US 5982042)
Regarding claim 1.
Nakamura teaches:
A semiconductor device (fig 11), comprising: a plurality of die regions (fig 11:1a; [column 4 line 50]), disposed on a semiconductor wafer (fig 11:1; [column 4 line 44]);
a scribe line region (fig 11:6; [column 4 line 47]), disposed between the plurality of die regions (fig 11:1a; [column 4 line 50]);
and a plurality of circuit probing pads (fig 11:2,7,3; [column 7 lines 5-15]), each of the circuit probing pads (fig 11:2,7,3; [column 7 lines 5-15]) having a first portion (fig 11:2; [column 7 lines 5-15]) and a second portion (fig 11:3; [column 7 lines 5-15]), wherein the first portion (fig 11:2; [column 7 lines 5-15]) is disposed on a first top surface (fig 2) of a corresponding die region (fig 11:1a; [column 4 line 50]) of the plurality of die regions (fig 11:1a; [column 4 line 50]), and the second portion (fig 11:3; [column 7 lines 5-15]) is disposed on a second top surface (fig 2) of the scribe line region (fig 11:6; [column 4 line 47]);
wherein an area of the first portion (fig 11:2; [column 7 lines 5-15]) is smaller than an area of the second portion (fig 11:3; [column 7 lines 5-15]);
.wherein a center (fig 11:7[column 7 lines 5-15]) of each of the circuit probing pads (fig 11:2,7,3; [column 7 lines 5-15]) is between a centerline of the scribe line region (fig 11:6; [column 4 line 47]) and the corresponding die region (fig 11:1a; [column 4 line 50]).
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Regarding claim 2.
Nakamura teaches the semiconductor device of Claim 1,
Nakamura teaches:
wherein each die region (fig 11:1a; [column 4 line 50])comprises functional circuitry (column 4 line 45), and the scribe line region (fig 11:6; [column 4 line 47]) is a non-functional region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 3, 4, 5, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 5982042) as applied to claim 1 and further in view of Kim (US 6159826)
Regarding claim 3.
Nakamura teaches the semiconductor device of Claim 2,
Nakamura teaches:
each circuit probing pad (fig 11:2,7,3; [column 7 lines 5-15]) is electrically connected to the corresponding die region (fig 11:1a; [column 4 line 50]).
Nakamura does not teach connection to the functional circuitry.
Kim teaches:
each circuit probing pad (fig 5:56; [column 3 lines 40-45])is electrically connected to the functional circuitry (fig 5:52; [column 3 lines 30-35]) of the corresponding die region (fig 5:32; [column 3 lines 30-35]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the pad to functional circuitry in order for voltage applied to the pad be conducted to the functions of the circuits.
Regarding claim 4.
Nakamura in view of Kim teaches the semiconductor device of Claim 3,
Nakamura teaches:
the functional circuitry of each die region (fig 1:1a; [column 4 lines 50-55])is tested via a plurality of probing needles (fig 1:4; [column 4 lines 60-65]) connected to external test equipment and placed on one or more of the circuit probing pads (fig 1:1a; [column 4 lines 50-55]).
Kim teaches:
the functional circuitry (fig 5:52; [column 3 lines 30-35]) of each die region (fig 5:32; [column 3 lines 30-35]) is tested via a plurality of circuit probing needles (fig 5:60; [column 3 lines 50-55]) electrically connected to external test equipment and placed on one or more of the circuit probing pads (fig 5:56; [column 3 lines 35-40]).
The recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. The limitation must distinguish from the prior art in terms of structure rather than function, In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Limitations directed towards the test equipment used to test the structure do not limit the claim.
Regarding claim 5.
Nakamura in view of Kim teaches the semiconductor device of Claim 3,
Kim teaches:
wherein the functional circuitry (fig 5:52; [column 3 lines 30-35]) is located under the circuit probing pads (fig 5:56; [column 3 lines 35-40]).
Regarding claim 8.
Nakamura in view of Kim teaches the semiconductor device of Claim 4,
Nakamura teaches:
a portion of each circuit probing pad (fig 23:2,3; [column 5 lines 35-45]) is configured to be diced out from the semiconductor wafer (fig 23:1; [column 5 lines 35-40]) through a dicing process performed on the semiconductor wafer (fig 23,24:1; [column 5 lines 35-40]) along one or more dicing paths defined on the scribe line region (fig 23,24:6; [column 5 lines 45-55]).
Claim(s) 9, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 5982042) in view of Kim (US 6159826) as applied to claim 8 and further in view of Uehling (US 2013/0299947)
Regarding claim 9
Nakamura in view of Kim teaches the semiconductor device of Claim 8,
Nakamura teaches:
the scribe line region (fig 23,24:6; [column 5 lines 45-55]) is configured to form a remaining scribe line structure (fig 24; [column 5 lines 45-55]) after the dicing process, and each die region (fig 24:1a; [column 5 lines 40-55]) is configured to be packaged with the remaining scribe line structure.
Nakumura in view of Kim does not teach a semiconductor chip package.
Uehling teaches:
wherein the die region (fig 3:110; [para 0019]) and the remaining portion of the scribe line region (fig 3:122; [para 0018])
are packaged into the semiconductor chip package (fig 3:264; [para 0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to package the die into a die package in order to protect the structure during subsequent use.
Regarding claim 10
Nakamura in view of Kim in view of Uehling teaches the semiconductor device of Claim 9,
Nakamura teaches:
each circuit probing pad (fig 23:2,3; [column 5 lines 35-45]) is configured to form a remaining circuit probing pad (fig 24:2,3a; [column 5 lines 40-55])after the dicing process (fig 24; [column 5 lines 40-55]), the remaining circuit probing pad (fig 24:2,3a; [column 5 lines 40-55]) comprises the first portion (fig 24:2; [column 5 lines 40-55]) and a remaining portion (fig 24:3a; [column 5 lines 40-55])of the second portion (fig 23,24:3; [column 5 lines 40-55]), and the remaining circuit probing pad (fig 24:2,3a; [column 5 lines 40-55])
Kim teaches:
the remaining circuit probing pad (fig 5:56; [column 3 lines 35-40]) is electrically connected to the functional circuitry (fig 5:52; [column 3 lines 30-35]).
Regarding claim 11.
Nakamura in view of Kim in view of Uehling teaches the semiconductor device of Claim 9,
Uehling teaches:
each die region (fig 3:110,112; [para 0018]) is configured to be electrically connected to a substrate in the semiconductor chip package via wire bonding (fig 3; [para 0019]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to wire bond the die to a substrate in order to conduct voltage from an external connector to the die and thereby enable packaging of the device for protection and further assembly.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the prior art does not teach, “wherein a center line of the scribe line region is between a center of each of the circuit probing pads and the corresponding die region.”
However, the applicant does not disclose this limitation nor is it clear how this would be possible. Rather, the applicant discloses a substantially different structure in figures 3a, 3b and paragraph 47.
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In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Additionally, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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