Prosecution Insights
Last updated: May 29, 2026
Application No. 18/239,283

CONTACTS IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME

Non-Final OA §112
Filed
Aug 29, 2023
Examiner
CHI, SUBERR L
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
543 granted / 645 resolved
+16.2% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
18 currently pending
Career history
666
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
69.7%
+29.7% vs TC avg
§102
15.0%
-25.0% vs TC avg
§112
11.6%
-28.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 645 resolved cases

Office Action

§112
DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election Applicant’s election of claims #1-12 and 21-28 in the reply filed on January 7, 2026 is acknowledged. Because the Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). IDS The IDS document(s) filed on September 12, 2023 and June 24, 2024 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure, the conductive feature contacting the shared contact” (claim 1); and “a shared contact extending through the semiconductor fin and connected to a back-side of the first gate electrode and a back-side of the source/drain region; a first gate contact extending through the semiconductor fin and connected to a back-side of the second gate electrode” (claim 8); and “a first conductive contact extending through the first semiconductor layer and electrically connected to the first source/drain region and the first gate structure” (claim 21) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections – 35 U.S.C. § 112(a) The following is a quotation of 35 U.S.C. § 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claims 21-28 are rejected under 35 U.S.C. § 112(a) or pre-AIA 35 U.S.C. § 112, first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. As to claim 21, the limitation “a first conductive contact extending through the first semiconductor layer and electrically connected to the first source/drain region and the first gate structure” (emphasis added) comprises new matter. Refer to the 35 U.S.C. § 112(b) rejection below. Claim Rejections – 35 U.S.C. § 112(b) The following is a quotation of 35 U.S.C. § 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-12 and 21-28 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention. As to claim 1, it is unclear how the “shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure, the conductive feature contacting the shared contact” (emphasis added). The definition of “through” is ‘in one side and out the other’. Here, the drawings do not show a shared contact extending in one side and out the other side of the semiconductor fin 66. As to claim 8, it is unclear how “a shared contact extending through the semiconductor fin and connected to a back-side of the first gate electrode and a back-side of the source/drain region; a first gate contact extending through the semiconductor fin and connected to a back- side of the second gate electrode” (emphasis added). The definition of “through” is ‘in one side and out the other’. Here, the drawings do not show a shared contact nor first gate contact extending in one side and out the other side of the semiconductor fin 66. As to claim 21, it is unclear how “a first conductive contact extending through the first semiconductor layer and electrically connected to the first source/drain region and the first gate structure” (emphasis added). The definition of “through” is ‘in one side and out the other’. Here, the drawings do not show a first conductive contact extending in one side and out the other side of the semiconductor layer 66. As to claims 1-3, it is unclear if “to be electrically connected” (emphasis added) states an intent or actual structure. No Prior Art Applied The Examiner was unable to find prior art applicable to the claims as presently written. As to claim 1, Wang et al. (U.S. Patent Publication No. 2021/0335709 A1), hereafter “Wang”, teaches in FIG. 28A a first interconnect structure 150, a second interconnect structure 140 comprising a conductive feature 142, and a device layer 130 between the first interconnect structure and the second interconnect structure, the device layer comprising: a semiconductor fin 54, a first gate structure 104 on the semiconductor fin, a source/drain region 92 adjacent the first gate structure, and a shared contact 158 extending through the semiconductor fin to be electrically connected to the source/drain region. However, Wang does not teach the shared contact electrically connected to the first gate structure nor the conductive feature contacting the shared contact. As to claim 8, Wang teaches in FIG. 28A a first gate electrode (left 104); a second gate electrode (middle 104); a source/drain region 92 besides the first gate electrode; and a semiconductor fin 54 on the source/drain region, the first gate electrode, and the second gate electrode; a shared contact 158 extending through the semiconductor fin and connected to a back-side of the first gate electrode and a back-side of the source/drain region; a first interconnect 150 on the shared contact, wherein the first interconnect structure comprises first conductive features 164, the first conductive features being electrically connected to the shared contact (via conductive line 160). However, Wang does not teach inter alia the first gate contact. As to claim 21, Wang teaches in FIG. 28A a first semiconductor layer 54; a first gate structure 104 on a first side of the first semiconductor layer; a first source/drain region 92 on the first side of the first semiconductor layer and beside the first gate structure; a first conductive contact 158 extending through the first semiconductor layer and electrically connected to the first source/drain region. However, Wang does not teach the first conductive contact electrically connected to the first gate structure because of the contact etch stop layer 94 and the first ILD 96. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUBERR L CHI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 29, 2023
Application Filed
Apr 06, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
87%
With Interview (+2.8%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 645 resolved cases by this examiner. Grant probability derived from career allowance rate.

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