DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested: “ELECTRONIC DEVICE HAVING POWER DELIVERY CIRCUIT CONNECTED TO INTERPOSERS.”
If Applicant does not agree with the suggested title above, Applicant must provide a new title that clearly reflects the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 9-11, 14, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US Pub. 2019/0148330; hereinafter “Chen”).
Regarding Claim 1, Chen discloses an electronic device, comprising: an interposer (140A, 140B) (page 5, paragraph 51; a redistribution structure may also serve as a spacer); and a first electronic component 120 (page 2, paragraph 20) disposed under the interposer (140A, 140B) (see fig. 11A) and comprising a logic circuit 121 (a semiconductor die 120 is an integrated circuit die; page 2, paragraph 20; and devices (not shown), such as transistors, diodes, capacitor, resistors, etc., may be formed in and/or on the semiconductor substrate 121; page 2, paragraph 21) and a power delivery circuit 122 (interconnect structures having metallization patterns (e.g., conductive lines 123 and vias 124); page 2, paragraph 21) disposed between the interposer (140A, 140B) and the logic circuit 121 (see fig. 11A), wherein the interposer (140A, 140B) and the power delivery circuit 122 are collectively configured to function as a power delivery structure to electrically connect the logic circuit 121 (the redistribution structures 140A, 140B include one or more layers of electrically conductive features (e.g., conductive lines 143, vias 145) that provide electrical routing paths; page 3, paragraph 27; accordingly, the redistribution structures, together with the interconnect structures 122, are collectively configured to function as a power delivery structure that electrically connects the logic circuit 121).
Regarding Claim 3, Chen discloses wherein a portion of an upper surface of the power delivery circuit 122 is exposed by the interposer (140A, 140B) (see figs. 11A and 11B).
Regarding Claim 4, Cheun discloses wherein the interposer (140A, 140B) is connected to the power delivery circuit 122 by a soldering material 148 (pages 5-6, paragraph 54).
Regarding Claim 5, Chen discloses wherein a quantity of conductive layers (143, 145) of the interposer (140A, 140B) (page 3, paragraph 27) is different from that of the power delivery circuit 122 (conductive lines 123 and vias 124; page 2, paragraph 21) (see fig. 11A).
Regarding Claim 9, Chen discloses an electronic device, comprising: a first electronic component 120 (page 2, paragraph 20) comprising a logic circuit 121 (a semiconductor die 120 is an integrated circuit die; page 2, paragraph 20; and devices (not shown), such as transistors, diodes, capacitor, resistors, etc., may be formed in and/or on the semiconductor substrate 121; page 2, paragraph 21) and a first power delivery circuit 122 (interconnect structures having metallization patterns (e.g., conductive lines 123 and vias 124); page 2, paragraph 21) electrically connected to the logic circuit 121 (see fig. 2); a first interposer 140A (page 5, paragraph 51; a redistribution structure may also serve as a spacer) disposed over the first electronic component 120 and electrically connected to the first power delivery circuit 122 (see fig. 11A); and a second interposer 140B disposed over the first electronic component 120 and electrically connected to the first power delivery circuit 122 (see fig. 11A), wherein the second interposer 140B is spaced apart from the first interposer 140A (see fig. 11A).
Regarding Claim 10, Chen discloses wherein the first power delivery circuit 122 is disposed between the logic circuit 121 and the first interposer 140A (see fig. 11A), and the first power delivery circuit 122 is disposed between the logic circuit 121 and the second interposer 140B (see fig. 11A).
Regarding Claim 11, Chen discloses wherein the first power delivery circuit 122 comprises a first portion (left portion where the first redistribution structure 140A is connected) electrically connected to the first interposer 140A and the logic circuit 121 and a second portion (right portion where the second redistribution structure 140B is connected) electrically connected to the second interposer 140B and the logic circuit 121 (see fig. 11A), and wherein the first portion (left portion) is spaced apart from the second portion (right portion) (see fig. 11A).
Regarding Claim 14, Chen discloses wherein the first interposer 140A comprises a second power delivery circuit (the redistribution structures 140A, 140B include one or more layers of electrically conductive features (e.g., conductive lines 143, vias 145); page 3, paragraph 27), the second interposer 140B comprises a third power delivery circuit (the redistribution structures 140A, 140B include one or more layers of electrically conductive features (e.g., conductive lines 143, vias 145); page 3, paragraph 27) (see fig. 11A), and a density of the second power delivery circuit is different from that of the third power delivery circuit (the electrically conductive features of the first redistribution structure 140A are connected to the die connectors 128 through three connectors, whereas the electrically conductive features of the second redistribution structure 140B are connected to the die connectors 128 through four connectors; see fig. 11A; because the second redistribution structure 140B utilizes a greater number of connectors, it provides high number of electrical connection paths, and this difference in the number of connection paths reflects a difference in connection density; see fig. 11A).
Regarding Claim 18, Chen discloses an electronic device, comprising: an electronic component 120 (page 2, paragraph 20) comprising a logic circuit 121 (a semiconductor die 120 is an integrated circuit die; page 2, paragraph 20; and devices (not shown), such as transistors, diodes, capacitor, resistors, etc., may be formed in and/or on the semiconductor substrate 121; page 2, paragraph 21) and a first power delivery circuit 122 (interconnect structures having metallization patterns (e.g., conductive lines 123 and vias 124); page 2, paragraph 21) electrically connected to the logic circuit 121 (see fig. 2); and an interposer (140A, 140B) (page 5, paragraph 51; a redistribution structure may also serve as a spacer) disposed over the electronic component 120 (see fig. 11A) and comprising a second power delivery circuit (the redistribution structures 140A, 140B include one or more layers of electrically conductive features (e.g., conductive lines 143, vias 145); page 3, paragraph 27) electrically connected to the first power delivery circuit 122 (see fig. 11A), wherein an upper surface of the first power delivery circuit 122 is without vertically overlapping the interposer (140A, 140B) (see fig. 11A).
Regarding Claim 20, Chen discloses wherein a portion of the logic circuit 121 is without vertically overlapping the interposer (140A, 140B) (see fig. 11A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding Claim 6, Chen discloses further comprising: a second electronic component 171 (page 5, paragraph 53) adjacent to the first electronic component 120 (see fig. 11A)
Chen fails to disclose explicitly wherein an elevation of an upper surface of the second electronic component is higher than an elevation of an upper surface of the first electronic component.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because determining optimum process conditions would have involved no more than routine experimentation using a limited number of result-effective variables. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Furthermore, having an elevation of the upper surface of the second electronic component higher than an elevation of the upper surface of the first electronic component, in order to improve overall electrical and thermal performance of the device.
Regarding Claim 12, Chen discloses wherein the logic circuit 121 comprises a first circuit region (left portion of the logic circuit 121) electrically connected to the first portion (left portion where the first redistribution structure 140A is connected) and a second circuit region (right portion of the logic circuit 121) electrically connected to the second portion (right portion where the second redistribution structure 140B is connected) (see fig. 11A).
Chen fails to disclose explicitly wherein a function of the first circuit region is different from a function of the second circuit region.
However, Chen discloses devices (not shown), such as transistors, diodes, capacitor, resistors, etc., of the integrated circuit die 120 may be formed in and/or on the semiconductor substrate 121 (page 2, paragraph 21), so a function of the first circuit region may be different from a function of the second circuit region because the types, arrangement, and interconnection of these semiconductor devices in each region can be configured to perform distinct electrical or logical operations, resulting in different functional roles within the integrated circuit.
Regarding Claim 19, Chen discloses wherein the electronic component 120 has a first surface (bottom surface) and a second surface (top surface) opposite to the first surface (bottom surface) (see fig. 11A), and the interposer (140A, 140B) is configured to provide the logic circuit 121 with a power through the second surface (top surface) (see fig. 11A).
Chen fails to disclose explicitly wherein the logic circuit is closer to the first surface than to the second surface.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because determining optimum process conditions would have involved no more than routine experimentation using a limited number of result-effective variables. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Furthermore, having logic circuit closer to the first surface than to the second surface, which provides power from the power delivery circuit, in order to minimize electrical resistance and parasitic effects between the logic circuit and the power delivery circuit, and thereby improve the overall performance and power efficiency of the electronic device.
Allowable Subject Matter
Claims 2, 7, 8, 13 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites an encapsulant encapsulating the interposer and the first electronic component, wherein a portion of the encapsulant is within a gap between the first electronic component and the interposer.
Claim 7 recites an encapsulant encapsulating the interposer, the first electronic component, and the second electronic component, wherein a distance between an upper surface of the encapsulant and the upper surface of the second electronic component is less than a distance between the upper surface of the encapsulant and the upper surface of the first electronic component.
Claim 13 recites a first circuit structure disposed over and electrically connected to the first interposer and the second interposer, wherein the first circuit structure covers a gap between the first interposer and the second interposer.
Claim 15 recites an encapsulant disposed between the first interposer and the second interposer, wherein the encapsulant encapsulates a lateral surface of the first electronic component.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claim 8, 16 and 17 variously depend from claim 7 or 13, so they are objected for the same reason.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. 2022/0344287 discloses an electronic device comprising a package 450 having an IC die 470 (a logic die) and another IC die 460 (a power management integrated circuit die) stacked on the IC die 470 (page 7, paragraph 63; fig. 22), and an interposer 402 is disposed on the package 450 (fig. 21).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 March 30, 2026