DETAILED ACTION
Claims 1-23 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of prior-filed applications under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 17/562,003 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
The examiner notes that applicant has cited NPL without providing relevant page numbers. While the NPL has been considered, please cite relevant page numbers for any NPL cited in the future, as required by 37 CFR 1.98(b)(5), to ensure consideration thereof.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
In paragraphs 1-3, applicant lists related applications. Patent numbers must be inserted for any application that has resulted in a patent. While none of the applications appear to have been patented at the time of drafting this Office Action, this note will serve as a reminder, until allowance of this application, to insert patent numbers as related applications issue.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 1, replace “processing comprising:” with --processing, the method comprising:-- so that the steps are explicitly tied to the method and not potentially to the task processing.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claim 4, “the memory block transfer control logic computes memory addresses”. The examiner has been unable to find sufficient structure disclosed in the specification for performing this computation. As such, broadest reasonable interpretation (BRI) is taken and 112(a)/(b) rejections appear below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 4, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the logic to perform the claimed function. The specification does not demonstrate that applicant has made an invention that achieves the claimed function(s) because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claims 1-2 and 20-23, the term “wide” is a relative term which renders the claims indefinite. The term is not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, the examiner is not clear on where the line is drawn between wide and not wide. For purposes of prior art examination, anything larger than 1 bit will be deemed wide. The examiner recommends deletion of “wide”.
Regarding claim 4, the claimed logic+function limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described above, the written description fails to disclose the corresponding structure(s), material(s), or act(s) for performing the entire claimed function(s) and to clearly link the structure(s), material(s), or act(s) to the function(s). Therefore, the claim(s) are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim(s) so that the claim limitation(s) will no longer be interpreted as a limitation(s) under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure(s), material(s), or act(s) perform the entire claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure(s), material(s), or act(s) disclosed therein to the function(s) recited in the claim(s), without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure(s), material(s), or act(s) and clearly links them to the function(s) so that one of ordinary skill in the art would recognize what structure(s), material(s), or act(s) perform the claimed function(s), applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure(s), material(s), or act(s) for performing the claimed function(s) and clearly links or associates the structure(s), material(s), or act(s) to the claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure(s), material(s), or act(s), which are implicitly or inherently set forth in the written description of the specification, perform the claimed function(s). For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 18, “the memory block transfer status”. The examiner recommends replacing with --a status of the memory block transfer--.
Claims 2-21 are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-18, and 20-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wentzlaff et al. (US 8,677,081, as cited by applicant).
Referring to claim 1, Wentzlaff has taught a processor-implemented method for task processing comprising:
accessing an array of compute elements (FIG.1, elements 102), wherein each compute element within the array of compute elements is known to a compiler (see column 3, line 64, to column 4, line 2. A compiler compiles code for the elements and, thus, the elements are known to the compiler) and is coupled to its neighboring compute elements within the array of compute elements (FIG.1);
providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler (again, see column 3, line 64, to column 4, line 2, and column 10, lines 10-13. A compiler will compile code to generate instructions, e.g. VLIW or variable-length (wide) instructions, for the array elements to execute over a number of cycles. From column 4, lines 16-19, the control could include causing context switches every N cycles. From column 4, lines 34-37, additional cycle control is discussed); and
executing a memory block transfer (from column 13, lines 56-67, a DMA engine can move/transfer memory data), wherein the memory block transfer is initiated by a control word from the stream of wide control words (from column 14, lines 8-11 and 44-54, control words will initiate memory transfer by setting address registers and other parameters, and starting the transfer (e.g. with Run-DMA-Engine (rde) instruction)), and wherein data for the memory block transfer is moved independently from the array of compute elements (from column 13, line 56, to column 14, line 16, the DMA is “an independent thread of control” that allows a tile processor (array element) to offload address computation and memory transfer (as is known with DMA)).
Referring to claim 2, Wentzlaff has taught the method of claim 1 wherein the control word from the stream of wide control words includes a source address (column 14, lines 8-14, “starting from address”), a target address (column 14, lines 8-14, “starting end address”), a block size (column 14, lines 8-14, “transaction length”), and a stride (column 14, lines 8-14, “stride”).
Referring to claim 3, Wentzlaff has taught the method of claim 2 further comprising using memory block transfer control logic (the DMA engine is the claimed logic).
Referring to claim 4, Wentzlaff has taught the method of claim 3 wherein the memory block transfer control logic computes memory addresses (column 14, lines 2-14).
Referring to claim 7, Wentzlaff has taught the method of claim 3 wherein the memory block transfer control logic is augmented by configuring one or more compute elements from the array of compute elements (again, from the various citations above, a compute element is configured to execute instructions to trigger the DMA engine. As such the DMA engine is augmented by configuring a compute element to operate the engine. Additionally, from column 14, lines 22-30, compute element cache would be configured to store data, which could then be transferred to another compute element cache. Thus, this configuration augments the DMA engine by allowing for low overhead cache transfer).
Referring to claim 8, Wentzlaff has taught the method of claim 7 wherein the configuring initializes compute element operation buffers within the one or more compute elements (again, for a cache transfer to occur, a cache (comprising lines that make up one or more operation buffers) must be initialized with some data to transfer).
Referring to claim 9, Wentzlaff has taught the method of claim 8 wherein the operation buffers comprise bunch buffers (caches are buffers that store bunches of data bits).
Referring to claim 10, Wentzlaff has taught the method of claim 1 wherein the memory block transfer comprises a load and/or store forwarding operation (column 14, lines 4-6).
Referring to claim 11, Wentzlaff has taught the method of claim 1 wherein the memory block transfer comprises a cache line move (column 14, lines 22-30).
Referring to claim 12, Wentzlaff has taught the method of claim 11 wherein the cache line move transfers data on unidirectional line transfer buses (from column 3, lines 8-11, there are multiple wires to support parallel channels in each direction. This means that if data is going from cache A to cache B, then it is transmitted on a unidirectional line going from A to B. If the data is going from cache B to cache A, then it is transmitted on a unidirectional line going from B to A).
Referring to claim 13, Wentzlaff has taught the method of claim 11 further comprising tagging data to enable cache line movement (again, from column 14, lines 8-14, 22-24, and 50-54, source and destination addresses need to be set. When this data is stored to the appropriate configuration register, it is tagged. For instance, when a compute element, writes data into a “start” register, this effectively tags the written data as “start address”. Data written to a stride register would be effectively tagging the data as “stride information”. Such is needed for cache line movement).
Referring to claim 14, Wentzlaff has taught the method of claim 13 wherein the tagging data is performed on data issuing from the array of compute elements (the data written to the configuration registers is data issuing from the array).
Referring to claim 15, Wentzlaff has taught the method of claim 1 further comprising notifying a control unit upon successful completion of the memory block transfer (column 14, lines 14-16).
Referring to claim 16, Wentzlaff has taught the method of claim 15 wherein successful completion of the memory block transfer occurs within an architectural cycle (column 4, lines 31-37, set forth data transfer between neighboring tiles in a single clock cycle. Alternatively, the total amount of time a DMA transfer takes may be considered a DMA architectural cycle, which is not necessarily limited to one clock cycle).
Referring to claim 17, Wentzlaff has taught the method of claim 16 wherein the architectural cycle includes a plurality of clock cycles (the operation described in column 14, lines 8-18 necessarily requires multiple clock cycles. That is, the DMA transfer will require different number of clock cycles depending on the amount of data to transfer. A larger transfer would time more clock cycles. Also, multiple clock cycles are implied by the interrupt/polling functionality. There would be no need to do either if all DMA transfers only took one clock cycle).
Referring to claim 18, Wentzlaff has taught the method of claim 15 wherein the notifying is accomplished by polling the memory block transfer status (column 14, lines 17-18).
Referring to claim 20, Wentzlaff has taught the method of claim 1 wherein the stream of wide control words comprises variable length control words generated by the compiler (column 10, lines 10-13).
Referring to claim 21, Wentzlaff has taught the method of claim 20 wherein the stream of wide, variable length, control words generated by the compiler provides direct, fine-grained control of the array of compute elements (column 4, lines 16-19).
Claim 22 is mostly rejected for similar reasoning as claim 1. Wentzlaff has further taught a computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform the claimed operations (all operations in the system of Wentzlaff would occur in response to executing program code. And, program code is necessarily stored in a computer-readable medium such as main memory, instruction cache, etc.).
Claim 23 is rejected for similar reasoning as claim 22, where one or more processors coupled to the memory correspond to the processors of the array, which access memory to execute instructions, which causes all claimed operations to occur, including accessing another array element’s data through the various interconnections shown in FIGs.1-2A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Wentzlaff in view of Moroo et al. (US 2011/0191638).
Referring to claim 5, Wentzlaff has taught the method of claim 3 but has not taught wherein the memory block transfer control logic is implemented outside of the array of compute elements. Wentzlaff has taught that the DMA engine is integrated within a tile that include a compute element, but it is not clear if the DMA engine is separate from (outside) the compute element. However, Moroo has taught a similar computing array (FIG.1), in which a DMA engine (FIG.4, 130, and paragraph 60) is outside of the compute element (FIG.4, 110 or 10). The examiner asserts that rearranging parts (i.e., rearranging the DMA engine to be outside of the array) is deemed a routine expedient, not a patentable distinction, particularly absent a demonstration by applicant of the criticality of the claimed location (see MPEP 2144.04, including section (VI)(C). Regardless of location, a compute element can configure its DMA engine to perform the desired memory transfer. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wentzlaff such that the memory block transfer control logic is implemented outside of the array of compute elements (by outside of the array of compute elements, this is interpreted to mean that a given DMA engine is external to a compute element).
Referring to claim 6, Wentzlaff, as modified, has taught the method of claim 5 wherein the memory block transfer control logic operates autonomously from the array of compute elements (see column 13, line 56, to column 14, line 16. Basically, a DMA engine is configured and started, and it runs independently from a corresponding compute element (this allows the compute element to continue with other tasks that do not depend on the result of the memory transfer).
Claims 13-14 are alternatively rejected under 35 U.S.C. 103 as being unpatentable over Wentzlaff in view of the examiner’s taking of Official Notice.
Referring to claim 13, Wentzlaff has taught the method of claim 11 but, under a second interpretation, has not taught tagging data to enable cache line movement. However, Official Notice is taken that it was well known in the art before applicant’s invention to store a tag with cached data so that it can be associated with and identified by an address. For instance, when a processor is to store data to memory, the data and the address to which the data will be stored in memory is provided. When a cache exists (as in the case of Wentzlaff), the data to be stored may be cached. In the cache line, a tag representing the store address is stored with the data so that the data can be located again in the future. Without the tag, the system would not be able to track which memory addresses are being cached. One of ordinary skill in the art would have recognized that such a tag would be necessary to allow for a cache move to occur in Wentzlaff, which provides start and address of data to move. Such a start address would be compared to the tag to determine the data to move. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wentzlaff to perform tagging data to enable cache line movement.
Referring to claim 14, Wentzlaff, as modified based on the second interpretation, has taught the method of claim 13 wherein the tagging data is performed on data issuing from the array of compute elements (data to be stored is data issuing from the array).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wentzlaff in view of Shimizu et al. (US 2002/0019913).
Referring to claim 19, Wentzlaff has taught the method of claim 1 but has not taught wherein data for the memory block transfer is non-cacheable. However, Shimizu has taught shared memory systems complicate DMA since addition coherency check latency is incurred. One way to avoid this is to restrict DMA to non-cacheable regions of main memory (see paragraphs 9-11). As a result, in order to not spend more latency than DMA saves in a system like Wentzlaff’s, with shared memory and cache coherence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wentzlaff such that data for the memory block transfer is non-cacheable.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Sikka (US 2022/0318171) has taught an array of connected processing elements with independent DMA based on stride.
Ellis (US 2014/0137082) has taught an array of processing elements (FIG.16) and an array of routers (FIGs.16-17), where each router include DMA capability (FIG.17, DMAW/DMAR).
Barry (WO 01/63438) has taught ManArray DSP 203 having an array of processing elements and an external DMA controller 201.
Arimilli (US 2010/0262735) has taught a command that can move a block of data between addresses in system memory, including as part of an atomic cache-line copy operation.
Lopes has taught “Coarse-Grained Reconfigurable Computing with the Versat Architecture”. Specifically, a row of functional units makes of a data engine that is connected to a DMA circuit. Code (e.g. FIG.9) is also taught to configure the DMA, run it, and wait for it to complete.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183