Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/30/2023, 03/31/2025, and 11/13/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-17 without traverse in the reply filed on 11/29/2025 is acknowledged. The Examiner further acknowledges that claim 21 pertains to the elected invention.
Newly submitted claims 22-23 are directed to an invention that is independent or distinct from the invention originally claimed for the following reason:
Claim 17 is directed to a cap layer that is pure silicon or doped silicon. This is a mutually exclusive feature to a cap layer which is a multilayer structure wherein the multilayer structure includes a first sublayer of a material that is chemically different than that of a second sublayer. This is because a pure silicon cap layer or a doped silicon cap layer can’t be multiple chemically different elements as the whole cap layer is silicon or doped silicon.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 22-23 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Objections
Claim 3 is objected to because of the following informalities:
Claim 3 recites, “The semiconductor device structure of The semiconductor device structure of claim 1”. The Examiner believes the Applicant intended to recite, “.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 12 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the term “substantially” which is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is not clear to the Examiner what is meant for two interfaces to be substantially aligned. The Examiner believes that Applicant intends to mean that the two interfaces lie on parallel lines which are spaced apart by a certain maximum distance. It is not clear what this maximum distance is.
Claim 12 recites the limitation "“wherein the first portion is disposed between and in contact with the gate dielectric layer and each of the inner spacers ". There is insufficient antecedent basis for this limitation in the claim because there is no prior mention of, “the first portion”. The Examiner did not find mention of a first portion in Applicant’s specification. The Examiner finds that the claim language of claim 12 is similar to that of claim 4. Therefore, the Examiner will interpret, “the first portion” of claim 12 to mean “a portion of the cap layer”.
Claim 14 recites the limitation " wherein the second portion of the cap layer is further in contact with the gate spacer ". There is insufficient antecedent basis for this limitation in the claim. There is no mention of a second portion in the specification. Therefore, the Examiner will interpret, “the second portion” as meaning, “ a second portion”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al KR20210132570A. Wu et al will be referenced to as Wu henceforth.
Regarding Claim 1,
Wu teaches:
“A semiconductor device structure (FIG. 16), comprising:
a plurality of semiconductor layers vertically stacked (channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers (second spacer material layer 234, [0025]), each being disposed between two adjacent semiconductor layers among the plurality of semiconductor layers (FIG. 16);
a source/drain feature in contact with each of the inner spacers (source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (gate electrode 254, [0031]: 254 laterally surrounds 2080.); and
a cap layer disposed between the source/drain feature and each of the plurality of the semiconductor layers (first spacer material layer 232, [0024]).”
Regarding Claim 2,
Wu teaches:
“The semiconductor device structure of claim 1, wherein each of the inner spacers has at least three surfaces in contact with the cap layer and one surface in contact with the source/drain feature (annotated FIG. 16 #1).”
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Regarding Claim 3,
Wu teaches:
“The semiconductor device structure of The semiconductor device structure of claim 1 further comprising:
a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers (gate dielectric layer 252, [0031], FIG. 16).”
Regarding Claim 4,
Wu teaches:
“The semiconductor device structure of claim 3, wherein a portion of the cap layer is disposed between and in contact with the gate dielectric layer and each of the inner spacers (FIG. 16).”
Regarding Claim 5,
Wu teaches:
“The semiconductor device structure of claim 3, further comprising:
a gate spacer in contact with the cap layer and portions of the gate dielectric layer (gate spacer layer 226, [0028], FIG. 10, FIGs. 15-16: FIG. 10 clearly labels 226 and shows that 222, which may appear to be labeling the same part, could not possibly be doing so.).”
Regarding Claim 6,
Wu teaches:
“The semiconductor device structure of claim 5, wherein a portion of the cap layer is disposed between and in contact with the gate spacer and each of the inner spacers (FIG. 16).”
Regarding Claim 7,
Wu teaches:
“The semiconductor device structure of claim 6, wherein a portion of the cap layer is further in contact with the source/drain feature (FIG. 16).”
Regarding Claim 8,
Wu teaches:
“The semiconductor device structure of claim 1, wherein a portion of at least one of the semiconductor layers and a portion of the cap layer define a first interface (annotated FIG. 16 #2), a portion of the inner spacer and a portion of the source/drain feature define a second interface (annotated FIG. 16 #2), and the first interface and the second interface are substantially aligned (annotated FIG. 16 #2).”
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Annotated FIG. 16 #2
Regarding Claim 9,
Wu teaches:
“The semiconductor device structure of claim 1, wherein a portion of at least one of the semiconductor layers and a portion of the cap layer define a first interface (annotated FIG. 16 #2), a portion of the inner spacer and a portion of the source/drain feature define a second interface (annotated FIG. 16 #2), and the first interface and the second interface are off set from each other (annotated FIG. 16 #2: the first interface is on an opposite side of the capping layer from the second interface. Therefore, the two interfaces are horizontally offset from each other.).”
Regarding Claim 10,
Wu teaches:
“A semiconductor device structure, comprising:
a plurality of semiconductor layers vertically stacked (channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers (second spacer material layer 234, [0025]), each being disposed between two adjacent semiconductor layers (FIG. 16);
a source/drain feature in contact with each of the inner spacers (source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (gate electrode 254, [0031]: 254 laterally surrounds 2080.); and
a cap layer separating each of the plurality of the semiconductor layers from the source/drain feature (first spacer material layer 232, [0024],FIG. 16), wherein a portion of at least one of the plurality of the semiconductor layers and a portion of the cap layer define a first interface (annotated FIG. 16 #2), and wherein a portion of the inner spacer and the source/drain feature define a second interface that is offset from the first interface (annotated FIG. 16 #2: the first interface is on an opposite side of the capping layer from the second interface. Therefore, the two interfaces are horizontally offset from each other.).”
Regarding Claim 11,
Wu teaches:
“The semiconductor device structure of claim 10, further comprising:
a gate dielectric layer disposed between the semiconductor layer and the gate electrode layer (gate dielectric layer 252, [0031], FIG. 16).”
Regarding Claim 12,
Wu teaches:
“The semiconductor device structure of claim 11, wherein the first portion is disposed between and in contact with the gate dielectric layer and each of the inner spacers (FIG. 16: The Examiner assumes that, “the first portion”, references a portion of the cap layer as in claim 4.).”
Regarding Claim 13,
Wu teaches:
“The semiconductor device structure of claim 11, wherein each of the inner spacers has a first side in contact with the cap layer and a second side in contact with the source/drain feature (annotated FIG. 16 #1).”
Regarding Claim 14,
Wu teaches:
“The semiconductor device structure of claim 11, further comprising:
a gate spacer in contact with portions of the gate dielectric layer (gate spacer layer 226, [0028], FIG. 10, FIGs. 15-16: FIG. 10 clearly labels 226 and shows that 222, which may appear to be labeling the same part, could not possibly be doing so.), wherein the second portion of the cap layer is further in contact with the gate spacer (FIG. 16: “the second portion” has no antecedent basis and therefore the Examiner interprets, “the second portion” to mean a portion.).”
Regarding Claim 15,
Wu teaches:
“The semiconductor device structure of claim 14, wherein a portion of the gate dielectric layer is disposed between and in contact with the gate spacer and the gate electrode layer (FIG. 16).”
Regarding Claim 16,
Wu teaches:
“The semiconductor device structure of claim 10, wherein a portion of the cap layer is extended into the source/drain feature (annotated FIG. 16 #3).”
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Regarding Claim 21,
Wu teaches:
“A semiconductor device structure (FIG. 16), comprising:
a plurality of semiconductor layers vertically stacked (channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers, each being disposed between two adjacent semiconductor layers (second spacer material layer 234, [0025]);
a source/drain feature in contact with each of the inner spacers (source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (gate electrode 254, [0031]: 254 laterally surrounds 2080.);
a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers (gate dielectric layer 252, [0031], FIG. 16); and
a cap layer in the form of a continuous layer and arranged to separate each of the semiconductor layers from contacting the inner spacers and the source/drain feature (first spacer material layer 232, [0024]).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claims 1-16 and 21 above, and further in view of Chang et al US 20210273098 A1. Chang et al will be referenced to as Chang henceforth.
Regarding Claim 17,
Wu teaches:
“The semiconductor device structure of claim 10,”
Wu doesn’t substantially teach:
“wherein the cap layer is a pure silicon or doped silicon”
However, Chang teaches:
“wherein the cap layer is a pure silicon or doped silicon (Chang: second inner spacers 190, [0057], FIG. 19)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Wu is modifiable in view of Chang.
This is because Wu teaches a cap layer made of SiN. Wu doesn’t substantively teach a cap layer made of boron-doped silicon. Chang teaches a cap layer made of SiN . Chang further teaches a cap layer made of boron-doped silicon. Because both Wu and Chang have a cap layer of SiN, one of ordinary skill in the art would have deemed it obvious to substitute the cap layer of SiN of Wu for the cap layer of boron-doped silicon of Chang for the predictable result of providing a cap layer which protects source or drain regions from damage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812