Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
The request for a continued prosecution application (CPA) under 37 CFR 1.53(d) filed on 07/27/2026 is acknowledged. A CPA may only be filed in a design application filed under 35 U.S.C. chapter 16. See 37 CFR 1.53(d)(1). Since a CPA of this application is not permitted under 37 CFR 1.53(d)(1), the improper request for a CPA is being treated as a request for continued examination of this application under 37 CFR 1.114.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-7 and 11-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 3,
Claim 3 recites the limitation, “further comprising: a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers”. The Examiner finds that this limitation is indefinite because this same limitation is included in claim 1. Because of this, it is not clear whether the Applicant is claiming a second gate dielectric layer, or if the Applicant is referencing the same gate dielectric layer. Because Applicant’s figures show a singularly labeled gate dielectric layer in any one figure, and because the above limitation is identical to the limitation in claim 1, the Examiner believes the Applicant is referencing the same dielectric layer and interprets the claim accordingly.
Regarding Claims 4-7, these claims depend upon claim 3 and are therefore rejected for the same reasons.
Regarding Claim 11,
Claim 11 recites the limitation, “further comprising: a gate dielectric layer disposed between the semiconductor layer and the gate electrode layer.”. The Examiner finds that this limitation is indefinite because this same limitation is included in claim 10. Because of this, it is not clear whether the Applicant is claiming a second gate dielectric layer, or if the Applicant is referencing the same gate dielectric layer. Because Applicant’s figures show a singular gate dielectric layer in any one figure, and because the above limitation is identical to the limitation in claim 10, the Examiner believes the Applicant is referencing the same dielectric layer.
Regarding Claims 11-15, these claims depend upon claim 10 and are therefore rejected for the same reasons.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 3 and 11 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
This is because claims 3 and 11 respectively contain an identical limitation found in claims 1 and 10 respectively. This limitation is, “further comprising: a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers”
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Regarding Claim 13, this claim doesn’t further limit a gate dielectric and is therefore also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-16, 21, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al KR20210132570Ain view of Ko et al US 20220344217 A1. Wu et al and Ko et al will be referenced to as Wu and Ko respectively henceforth.
Regarding Claim 1,
Wu teaches:
“A semiconductor device structure (FIG. 16), comprising:
a plurality of semiconductor layers vertically stacked (channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers (second spacer material layer 234, [0025]), each being disposed between two adjacent semiconductor layers among the plurality of semiconductor layers (FIG. 16);
a source/drain feature in contact with each of the inner spacers (source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (gate electrode 254, [0031]: 254 laterally surrounds 2080.);
a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers (gate dielectric layer 252, [0031], FIG. 16); and
a cap layer disposed between the source/drain feature and each of the plurality of the semiconductor layers (first spacer material layer 232, [0024])”
Wu doesn’t substantially teach:
“wherein a portion of the cap layer extends between the inner spacer and the gate dielectric layer”
However, Ko teaches:
“wherein a portion of the cap layer extends between the inner spacer and the gate dielectric layer (Ko: inner spacer 132, [0146], FIG. 3G)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Wu is modifiable in view of Ko by extending the cap layer into the gate dielectric (which Ko calls an inner spacer and dielectric mask layer respectively) into the device of Wu.
This is because Ko teaches that the gate dielectric and cap layer structure of Ko is more resistant to an etching process used to formed the gate structure between the channel layers which improves the yield and performance of the semiconductor device (Ko: [0146], FIG. 2T-1, FIG. 2U-1, FIG. 3G). One of ordinary skill in the art would recognize that such a benefit is applicable to the device of Wu because the device of Wu uses a same etching step (Wu: [0023], FIGs. 13-14).
Regarding Claim 2,
Wu/Ko teaches:
“The semiconductor device structure of claim 1, wherein each of the inner spacers has at least three surfaces in contact with the cap layer and one surface in contact with the source/drain feature (Wu: annotated FIG. 16 #1).”
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Regarding Claim 3,
Wu/Ko teaches:
“The semiconductor device structure of claim 1 further comprising:
a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers (Wu: gate dielectric layer 252, [0031], FIG. 16).”
Regarding Claim 4,
Wu/Ko teaches:
“The semiconductor device structure of claim 3, wherein a portion of the cap layer is disposed between and in contact with the gate dielectric layer and each of the inner spacers (Wu: FIG. 16).”
Regarding Claim 5,
Wu/Ko teaches:
“The semiconductor device structure of claim 3, further comprising:
a gate spacer in contact with the cap layer and portions of the gate dielectric layer (Wu: gate spacer layer 226, [0028], FIG. 10, FIGs. 15-16: FIG. 10 clearly labels 226 and shows that 222, which may appear to be labeling the same part, could not possibly be doing so.).”
Regarding Claim 6,
Wu/Ko teaches:
“The semiconductor device structure of claim 5, wherein a portion of the cap layer is disposed between and in contact with the gate spacer and each of the inner spacers (Wu: FIG. 16).”
Regarding Claim 7,
Wu/Ko teaches:
“The semiconductor device structure of claim 6, wherein a portion of the cap layer is further in contact with the source/drain feature (Wu: FIG. 16).”
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Regarding Claim 9,
Wu/Ko teaches:
“The semiconductor device structure of claim 1, wherein a portion of at least one of the semiconductor layers and a portion of the cap layer define a first interface (Wu: annotated FIG. 16 #2), a portion of the inner spacer and a portion of the source/drain feature define a second interface (Wu: annotated FIG. 16 #2), and the first interface and the second interface are offset from each other (Wu: annotated FIG. 16 #2: the first interface is on an opposite side of the capping layer from the second interface. Therefore, the two interfaces are horizontally offset from each other.).”
Regarding Claim 10,
Wu/Ko teaches:
“A semiconductor device structure, comprising:
a plurality of semiconductor layers vertically stacked (Wu: channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers (Wu: second spacer material layer 234, [0025]), each being disposed between two adjacent semiconductor layers (Wu: FIG. 16);
a source/drain feature in contact with each of the inner spacers (source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (Wu: gate electrode 254, [0031]: 254 laterally surrounds 2080.); and
a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers (Wu: gate dielectric layer 252, [0031], FIG. 16);
a cap layer separating each of the plurality of the semiconductor layers from the source/drain feature (Wu: first spacer material layer 232, [0024], FIG. 16), wherein a portion of at least one of the plurality of the semiconductor layers and a portion of the cap layer define a first interface (Wu: annotated FIG. 16 #2), and wherein a portion of the inner spacer and the source/drain feature define a second interface that is offset from the first interface, (Wu: annotated FIG. 16 #2: the first interface is on an opposite side of the capping layer from the second interface. Therefore, the two interfaces are horizontally offset from each other.) and wherein a portion of the cap layer extends between the inner spacer and the gate dielectric layer (Ko: inner spacer 132, [0146], FIG. 3G).”
Regarding Claim 11,
Wu/Ko teaches:
“The semiconductor device structure of claim 10, further comprising:
a gate dielectric layer disposed between the semiconductor layer and the gate electrode layer (Wu: gate dielectric layer 252, [0031], FIG. 16).”
Regarding Claim 12,
Wu/Ko teaches:
“The semiconductor device structure of claim 11, wherein a first portion of the cap layer is disposed between and in contact with the gate dielectric layer and each of the inner spacers (Wu: FIG. 16: The Examiner assumes that, “the first portion”, references a portion of the cap layer as in claim 4.).”
Regarding Claim 13,
Wu/Ko teaches:
“The semiconductor device structure of claim 11, wherein each of the inner spacers has a first side in contact with the cap layer and a second side in contact with the source/drain feature (Wu: annotated FIG. 16 #1).”
Regarding Claim 14,
Wu/Ko teaches:
“The semiconductor device structure of claim 11, further comprising:
a gate spacer in contact with portions of the gate dielectric layer (Wu: gate spacer layer 226, [0028], FIG. 10, FIGs. 15-16: FIG. 10 clearly labels 226 and shows that 222, which may appear to be labeling the same part, could not possibly be doing so.), wherein a second portion of the cap layer is further in contact with the gate spacer (Wu: FIG. 16).”
Regarding Claim 15,
Wu/Ko teaches:
“The semiconductor device structure of claim 14, wherein a portion of the gate dielectric layer is disposed between and in contact with the gate spacer and the gate electrode layer (Wu: FIG. 16).”
Regarding Claim 16,
Wu/Ko teaches:
“The semiconductor device structure of claim 10, wherein a portion of the cap layer is extended into the source/drain feature wherein the portion of the cap layer and the source/drain feature define a third interface, and the third interface and the second interface are not coplanar (Wu: annotated FIG. 16 #4).”
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Regarding Claim 21,
Wu/Ko teaches:
“A semiconductor device structure (Wu: FIG. 16), comprising:
a plurality of semiconductor layers vertically stacked (Wu: channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers, each being disposed between two adjacent semiconductor layers (Wu: second spacer material layer 234, [0025]);
a source/drain feature in contact with each of the inner spacers (Wu: source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (Wu: gate electrode 254, [0031]: 254 laterally surrounds 2080.);
a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers (Wu: gate dielectric layer 252, [0031], FIG. 16); and
a cap layer in the form of a continuous layer and arranged to separate each of the semiconductor layers from contacting the inner spacers and the source/drain feature, (Wu: first spacer material layer 232, [0024]) wherein a portion of the cap layer extends between the inner spacer and the gate dielectric layer (Ko: inner spacer 132, [0146], FIG. 3G).”
Regarding Claim 24,
Wu/Ko teaches:
“The semiconductor device structure of claim 21, wherein the cap layer is disposed on semiconductor surfaces of the plurality of semiconductor layers (Wu: FIG. 16).”
Regarding Claim 25,
Wu/Ko teaches:
“The semiconductor device structure of claim 21, wherein the cap layer is disposed directly on surfaces of the plurality of semiconductor layers and extends continuously along sidewalls of the plurality of semiconductor layers between the semiconductor layers and the source/drain feature (Wu: FIG. 16)”
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wu/Ko as applied to claims 1-7, 9-16 and 21, 24-25 above, and further in view of Chang et al US 20210273098 A1. Chang et al will be referenced to as Chang henceforth.
Regarding Claim 17,
Wu/Ko teaches:
“The semiconductor device structure of claim 10,”
Wu/Ko doesn’t substantially teach:
“wherein the cap layer is a pure silicon or doped silicon”
However, Chang teaches:
“wherein the cap layer is a pure silicon or doped silicon (Chang: second inner spacers 190, [0057], FIG. 19)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Wu is modifiable in view of Chang.
This is because Wu/Ko teaches a cap layer made of SiN. Wu doesn’t substantively teach a cap layer made of boron-doped silicon. Chang teaches a cap layer made of SiN . Chang further teaches a cap layer made of boron-doped silicon. Because both Wu/Ko and Chang have a cap layer of SiN, one of ordinary skill in the art would have deemed it obvious to substitute the cap layer of SiN of Wu/Ko for the cap layer of boron-doped silicon of Chang for the predictable result of providing a cap layer which protects source or drain regions from damage.
Response to Arguments
Applicant’s arguments, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Ko.
Conclusion
The prior art made of record and not relied upon US 20240347596 A1 is considered pertinent to applicant's disclosure. This is because US 20240347596 A1 has a similar gate dielectric, cap layer and insulating spacer structure as Applicant’s application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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