Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly amended claim 8 is directed to an invention that is independent or distinct from the invention originally claimed for the following reason:
Claim 8 is directed to a portion of an inner spacer and a portion of a source/drain feature defining a second interface in a horizontal plane. In Applicant’s originally presented invention, claim 2 states that the inner spacer and the source/drain feature share one interface. The only figures in which the inner spacer has a horizontal interface with the source/drain feature are the figures in which the inner spacer shares more than one interface with the source/drain feature. Therefore, the limitation of having one interface between an inner spacer and a source drain region and the limitation of having a portion of an inner spacer and a portion of a source/drain feature having an interface in a horizontal plane are mutually exclusive.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 8 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Objections
The Examiner’s claim objection has been withdrawn.
Claim Rejections - 35 USC § 112
The Applicant’s amendments to the claims have overcome the Examiner’s 112(b) rejections. Therefore, the Examiner’s 112(b) rejections are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9-16, 21, and 24-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al KR20210132570A. Wu et al will be referenced to as Wu henceforth.
Regarding Claim 1,
Wu teaches:
“A semiconductor device structure (FIG. 16), comprising:
a plurality of semiconductor layers vertically stacked (channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers (second spacer material layer 234, [0025]), each being disposed between two adjacent semiconductor layers among the plurality of semiconductor layers (FIG. 16);
a source/drain feature in contact with each of the inner spacers (source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (gate electrode 254, [0031]: 254 laterally surrounds 2080.); and
a cap layer disposed between the source/drain feature and each of the plurality of the semiconductor layers (first spacer material layer 232, [0024]).”
Regarding Claim 2,
Wu teaches:
“The semiconductor device structure of claim 1, wherein each of the inner spacers has at least three surfaces in contact with the cap layer and one surface in contact with the source/drain feature (annotated FIG. 16 #1).”
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Annotated FIG. 16 #1
Regarding Claim 3,
Wu teaches:
“The semiconductor device structure of claim 1 further comprising:
a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers (gate dielectric layer 252, [0031], FIG. 16).”
Regarding Claim 4,
Wu teaches:
“The semiconductor device structure of claim 3, wherein a portion of the cap layer is disposed between and in contact with the gate dielectric layer and each of the inner spacers (FIG. 16).”
Regarding Claim 5,
Wu teaches:
“The semiconductor device structure of claim 3, further comprising:
a gate spacer in contact with the cap layer and portions of the gate dielectric layer (gate spacer layer 226, [0028], FIG. 10, FIGs. 15-16: FIG. 10 clearly labels 226 and shows that 222, which may appear to be labeling the same part, could not possibly be doing so.).”
Regarding Claim 6,
Wu teaches:
“The semiconductor device structure of claim 5, wherein a portion of the cap layer is disposed between and in contact with the gate spacer and each of the inner spacers (FIG. 16).”
Regarding Claim 7,
Wu teaches:
“The semiconductor device structure of claim 6, wherein a portion of the cap layer is further in contact with the source/drain feature (FIG. 16).”
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Annotated FIG. 16 #2
Regarding Claim 9,
Wu teaches:
“The semiconductor device structure of claim 1, wherein a portion of at least one of the semiconductor layers and a portion of the cap layer define a first interface (annotated FIG. 16 #2), a portion of the inner spacer and a portion of the source/drain feature define a second interface (annotated FIG. 16 #2), and the first interface and the second interface are offset from each other (annotated FIG. 16 #2: the first interface is on an opposite side of the capping layer from the second interface. Therefore, the two interfaces are horizontally offset from each other.).”
Regarding Claim 10,
Wu teaches:
“A semiconductor device structure, comprising:
a plurality of semiconductor layers vertically stacked (channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers (second spacer material layer 234, [0025]), each being disposed between two adjacent semiconductor layers (FIG. 16);
a source/drain feature in contact with each of the inner spacers (source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (gate electrode 254, [0031]: 254 laterally surrounds 2080.); and
a cap layer separating each of the plurality of the semiconductor layers from the source/drain feature (first spacer material layer 232, [0024],FIG. 16), wherein a portion of at least one of the plurality of the semiconductor layers and a portion of the cap layer define a first interface (annotated FIG. 16 #2), and wherein a portion of the inner spacer and the source/drain feature define a second interface that is offset from the first interface (annotated FIG. 16 #2: the first interface is on an opposite side of the capping layer from the second interface. Therefore, the two interfaces are horizontally offset from each other.).”
Regarding Claim 11,
Wu teaches:
“The semiconductor device structure of claim 10, further comprising:
a gate dielectric layer disposed between the semiconductor layer and the gate electrode layer (gate dielectric layer 252, [0031], FIG. 16).”
Regarding Claim 12,
Wu teaches:
“The semiconductor device structure of claim 11, wherein a first portion of the cap layer is disposed between and in contact with the gate dielectric layer and each of the inner spacers (FIG. 16: The Examiner assumes that, “the first portion”, references a portion of the cap layer as in claim 4.).”
Regarding Claim 13,
Wu teaches:
“The semiconductor device structure of claim 11, wherein each of the inner spacers has a first side in contact with the cap layer and a second side in contact with the source/drain feature (annotated FIG. 16 #1).”
Regarding Claim 14,
Wu teaches:
“The semiconductor device structure of claim 11, further comprising:
a gate spacer in contact with portions of the gate dielectric layer (gate spacer layer 226, [0028], FIG. 10, FIGs. 15-16: FIG. 10 clearly labels 226 and shows that 222, which may appear to be labeling the same part, could not possibly be doing so.), wherein a second portion of the cap layer is further in contact with the gate spacer (FIG. 16: “the second portion” has no antecedent basis and therefore the Examiner interprets, “the second portion” to mean a portion.).”
Regarding Claim 15,
Wu teaches:
“The semiconductor device structure of claim 14, wherein a portion of the gate dielectric layer is disposed between and in contact with the gate spacer and the gate electrode layer (FIG. 16).”
Regarding Claim 16,
Wu teaches:
“The semiconductor device structure of claim 10, wherein a portion of the cap layer is extended into the source/drain feature wherein the portion of the cap layer and the source/drain feature define a third interface, and the third interface and the second interface are not coplanar (annotated FIG. 16 #4).”
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Regarding Claim 21,
Wu teaches:
“A semiconductor device structure (FIG. 16), comprising:
a plurality of semiconductor layers vertically stacked (channel member 2080, [0016], [0030]: channel layer 208 is made of silicon and 2080 is made of 208. Therefore, 2080 is also made of silicon.);
a plurality of inner spacers, each being disposed between two adjacent semiconductor layers (second spacer material layer 234, [0025]);
a source/drain feature in contact with each of the inner spacers (source/drain feature 242, [0027]);
a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers (gate electrode 254, [0031]: 254 laterally surrounds 2080.);
a gate dielectric layer disposed between the gate electrode layer and each of the plurality of the semiconductor layers (gate dielectric layer 252, [0031], FIG. 16); and
a cap layer in the form of a continuous layer and arranged to separate each of the semiconductor layers from contacting the inner spacers and the source/drain feature (first spacer material layer 232, [0024]).”
Regarding Claim 24,
Wu teaches:
“The semiconductor device structure of claim 21, wherein the cap layer is disposed on semiconductor surfaces of the plurality of semiconductor layers (FIG. 16).”
Regarding Claim 25,
Wu teaches:
“The semiconductor device structure of claim 21, wherein the cap layer is disposed directly on surfaces of the plurality of semiconductor layers and extends continuously along sidewalls of the plurality of semiconductor layers between the semiconductor layers and the source/drain feature (FIG. 16)”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claims 1-7, 9-16 and 21, 24-25 above, and further in view of Chang et al US 20210273098 A1. Chang et al will be referenced to as Chang henceforth.
Regarding Claim 17,
Wu teaches:
“The semiconductor device structure of claim 10,”
Wu doesn’t substantially teach:
“wherein the cap layer is a pure silicon or doped silicon”
However, Chang teaches:
“wherein the cap layer is a pure silicon or doped silicon (Chang: second inner spacers 190, [0057], FIG. 19)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Wu is modifiable in view of Chang.
This is because Wu teaches a cap layer made of SiN. Wu doesn’t substantively teach a cap layer made of boron-doped silicon. Chang teaches a cap layer made of SiN . Chang further teaches a cap layer made of boron-doped silicon. Because both Wu and Chang have a cap layer of SiN, one of ordinary skill in the art would have deemed it obvious to substitute the cap layer of SiN of Wu for the cap layer of boron-doped silicon of Chang for the predictable result of providing a cap layer which protects source or drain regions from damage.
Response to Arguments
Applicant substantively argues:
“A)Wu does not disclose a cap layer disposed between the source/drain feature and the semiconductor layers
Applicant respectfully submits that Wu does not disclose the claimed structure in which a cap layer is disposed between the source/drain feature and each of the plurality of semiconductor layers. Wu's first spacer material layers 232, 234 are introduced and processed for the purpose of forming inner spacer features, rather than functioning as a cap layer disposed between the semiconductor layers and the source/drain feature. Specifically, during formation of the inner spacer structures 240, the spacer material layers are etched back and removed from the semiconductor channel surfaces, such that "the etch-back process removes the first spacer material layer 232 and the second spacer material layer 234 on the channel layer 208, the substrate 202, and the gate spacer layer 226 to thereby form inner spacer feature 240." Because these spacer materials are removed from the channel surfaces, they do not remain between the semiconductor layers and the subsequently formed source/drain feature.”
The Examiner finds this argument is not fully persuasive. The Applicant references that during the formation of the inner spacer structure 240 the spacer material layers 232 and 234 are etched back and removed as described in Wu: [0026]. This process can be seen in FIGs. 9-10. Which are reproduced below for convenience:
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Applicant fails to mention that Wu [0026] further mentions, “As illustrated in FIG. 10, each inner spacer feature (240) includes an outer layer formed of a first spacer material layer (232) and an inner layer formed of a second spacer material layer (234). For convenience of reference, the outer layer shares the same reference number as the first spacer material layer (232), and the inner layer shares the same reference number as the second spacer material layer (234).” This quote comes after the recitation of the removal of 232 and 234. Wu only shows the partial etch of 232 and 234 across FIGs. 9-10 and states that 232 and 234 are portions of 240 which is present in FIG. 10. Therefore, one of ordinary skill in the art would reasonably conclude that 232 and 234 were only partially removed across FIGs. 9-10. Further support for the partial, and not complete, removal of 232 and 234 can be seen in Wu FIG. 16:
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Wu: FIG. 16: The Examiner has annotated the figure to clearly point out the inclusion of elements 232 and 234
As can be seen above, 232 is clearly shown to be a black line which continuously surrounds the channels 2080 and covers the sides of the gate dielectric 252. Further 232 clearly separates the source/drain feature 242 from the channels 2080. Lastly Wu: [0007] clearly states that the purpose of the inner spacers are to isolate the gate structure from the epitaxial source/drain. Such separation can’t occur if the inner spacers are fully removed.
Applicant further substantively argues:
“Wu's disclosure regarding the epitaxial growth process further confirms this understanding. Wu does not disclose that the epitaxial precursors interact with any intervening layer between the source/drain feature and the channel layer. To the contrary, Wu indicates that the epitaxial growth process uses precursors that interact with the semiconductor materials, including the channel layer 208 itself. This is consistent with the spacer material layers having been removed from the channel surfaces prior to epitaxial growth, leaving the semiconductor surfaces of the channel layers exposed. If the spacer material layers remained between the source/drain feature and the channel layer as alleged by the Examiner, Wu does not disclose how the epitaxial precursors would interact with the channel layer as described.”
The Examiner finds that this argument is not fully persuasive. Wu’s lack of disclosure of epitaxial precursors interacting with intervening layers between the source/drain feature and the channel layer does not preclude such interactions from occurring. The interaction of precursors with the channel layer and the source/drain features does not necessitate a lack of a cap layer between the source/drain features and the channel layer. For example, the precursors could be made of a material which permeates through the cap layer. A disclosure of how the epitaxial precursors interact with the channel layer is not determinative of whether or not a cap layer is between the source/drain features and the channel layer.
Applicant further substantively argues:
“(B)The Examiner's reliance on shading in the drawings is insufficient to establish anticipation In the Office Action and during the interview, the Examiner relied on a dark line shown in figures to conclude that a cap layer is present on the channel layers. Applicant respectfully submits that this interpretation is inconsistent with Wu's written description.
As indicated above, Wu expressly teaches that the spacer material layers are removed from the channel surfaces during the etch-back process used to form the inner spacers.
Because the written description explicitly states that these spacer layers are removed from the channel layer surfaces, the figures cannot reasonably be interpreted as showing those layers remaining on the channel layers.
While drawings in a reference may illustrate structural relationships, they do not necessarily define precise structural details or material layers where the written description teaches otherwise. See MPEP §2125; Hockerson-Halberstadt, Inc. v. Avia Group Int'l, 222 F.3d 951, 956 (Fed. Cir. 2000). In this case, the dark line shown in drawings is more reasonably interpreted as illustrating the profile or boundary of the channel layer rather than indicating the presence of a distinct material layer remaining on the channel surface. These findings align with the illustrated figures to describe the processes for forming and removing of the spacer material layers. Accordingly, the drawings relied by Examiner cannot override the explicit description indicating that the spacer materials are removed from the semiconductor channel surface.”
The Examiner finds that this argument is not fully persuasive. The Examiner believes that the dark line shown in FIGs. 9-10 and 16 are consistent with the written description for reasons stated above. Further, because a direct connection is made between 232 and the mentioned dark line in FIG. 16, the Examiner does not believe that it is reasonable to consider the dark line to be a boundary of the channel layer rather than a cap layer.
The Examiner does not find the Applicant’s arguments to be fully persuasive. Therefore, the Examiner’s rejection is maintained.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitation:
“wherein the cap layer extends within the gate dielectric”
It would overcome the current rejections for the independent claims. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights