DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claim 7 in the Applicant’s response dated 24 June 2026. The claim amendments have been addressed below.
The Examiner acknowledges the addition of new claims 21-30 in the Applicant’s response dated 24 June 2026. The new claims have been addressed below.
The Examiner acknowledges the cancellation of claims 1-6 and 17-20 in the Applicant’s response dated 24 June 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 28-30 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by Bone-Fong Wu et al. (US 2021/0336034 A1; hereinafter “Wu”).
Regarding Claim 28, Wu teaches a method, comprising:
forming a fin structure from a substrate (212, Fig. 3, para [0017] describes forming a fin-shaped structure 212 from a substrate 202), wherein the fin structure comprises a stack of semiconductor layers (204, Fig. 3, para [0017] describes a stack 204 of semiconductor layers) comprising alternating first (208, Fig. 3, para [0016] describes first semiconductor layers 208) and second semiconductor layers (206, Fig. 3, para [0016] describes second semiconductor layers 206);
removing the second semiconductor layers to form openings between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming spacer recesses 230 by at least partially removing the second semiconductor layers 206 forming openings 230 between vertically adjacent first semiconductor layers 208), wherein the openings extend through spaces between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming the spacer recesses 230 wherein the openings formed by the spacer recesses 230 would extend in a channel width (Y direction in Fig. 7) direction from one end of the gate stack 220 to the other and between vertically adjacent first semiconductor layers 208);
performing an atomic layer deposition process to form a seamless dielectric material in the openings (232, Fig. 8, para [0024] describes forming a spacer material layer 232 including silicon and oxygen through an ALD process in the openings 230).
further comprising removing edge portions of the seamless dielectric material to form cavities (232 and 249, Fig. 14, para [0030] describes removing inner edge portions of the seamless dielectric material 232 to form inter-member opening cavities 249).
Regarding Claim 29, Wu teaches the method of claim 28, further comprising depositing dielectric spacers in the cavities (240 and 252, Fig. 16, para [0031] describes forming a gate dielectric 252 in the cavities 249 wherein at least a portion of the gate dielectric layer 252 form a portion of inner dielectric spacer features 240 as describes in para [0033] and shown in Fig. 16).
Regarding Claim 30, Wu teaches the method of claim 29, further comprising forming a source/drain region adjacent the first semiconductor layers and the dielectric spacers (242, Fig. 15, para [0027] describes forming source/drain regions 242 adjacent to the first semiconductor layers 208/2080 and the dielectric spacers 240 and 252).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-16 and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Bone-Fong Wu et al. (US 2021/0336034 A1; hereinafter “Wu”) in view of Cheng-I Lin et al. (US 2020/0020569 A1; hereinafter “Lin”).
Regarding Claim 7, Wu teaches a method, comprising:
forming a fin structure from a substrate (212, Fig. 3, para [0017] describes forming a fin-shaped structure 212 from a substrate 202), wherein the fin structure comprises a stack of semiconductor layers (204, Fig. 3, para [0017] describes a stack 204 of semiconductor layers) comprising alternating first (208, Fig. 3, para [0016] describes first semiconductor layers 208) and second semiconductor layers (206, Fig. 3, para [0016] describes second semiconductor layers 206);
forming a sacrificial gate stack on a first portion of the fin structure (220, Fig. 5, para [0019] describes forming a dummy gate stack 220 over a first portion of the fin structure 212;
recessing a second portion of the fin structure (228, Fig. 6, para [0022] describes recessing second portions of the fin structure 212 to form source/drain trenches 228);
removing the second semiconductor layers disposed under the sacrificial gate stack to form openings between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming spacer recesses 230 by at least partially removing the second semiconductor layers 206 forming openings 230 between vertically adjacent first semiconductor layers 208), wherein the openings extend through spaces between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming the spacer recesses 230 wherein the openings formed by the spacer recesses 230 would extend in a channel width (Y direction in Fig. 7) direction from one end of the gate stack 220 to the other and between vertically adjacent first semiconductor layers 208); and
performing an atomic layer deposition process to form a seamless dielectric material in the openings (232, Fig. 8, para [0024] describes forming a spacer material layer 232 including silicon and oxygen through an ALD process in the openings 230).
Wu fails to explicitly teach the atomic layer deposition process, comprising: performing a first plurality of cycles, each cycle including flowing a first silicon-containing precursor into a processing chamber at a first flow rate for a first duration and flowing a first oxygen-containing precursor into the processing chamber at a second flow rate for a second duration; and then performing a second plurality of cycles, each cycle including flowing a second silicon-containing precursor different from the first silicon-containing precursor into the processing chamber at a third flow rate for a third duration and flowing a second oxygen-containing precursor into the processing chamber at a fourth flow rate for a fourth duration.
However, Lin teaches a method of forming a dielectric layer through by performing an atomic layer deposition process (401, Fig. 4A, para [0047] describes forming a silicon oxide dielectric liner 501 using a dielectric gap-filling process 807, 809, 811 and 813 further comprising an ALD process), comprising:
performing a first plurality of cycles (N4, para [0049] describes a set of cycles N4 wherein the number of cycles is between 1 and 20), each cycle including flowing a first silicon-containing precursor into a processing chamber at a first flow rate for a first duration (para [0049] describes flowing a second silicon precursor, herein representing a first silicon precursor, into a process chamber at a flow rate between 50 sccm and about 300 sccm for a duration between about 6 seconds and about 60 seconds) and flowing a first oxygen-containing precursor into the processing chamber at a second flow rate for a second duration (para [0049] describes flowing a first oxygen precursor in a process chamber at a flow rate between 10 sccm and about 100 sccm for a duration between about 6 seconds and about 60 seconds); and then
performing a second plurality of cycles (N6, para [0051] describes a set of cycles N6 wherein the number of cycles is between 1 and 5), each cycle including flowing a second silicon-containing precursor different from the first silicon-containing precursor into the processing chamber at a third flow rate for a third duration (para [0051] describes flowing a fourth silicon precursor, herein representing a second silicon precursor, that may be different from the first silicon precursor into the process chamber at a flow rate between 10 sccm and about 300 sccm for a duration between about 6 seconds and about 120 seconds) and flowing a second oxygen-containing precursor into the processing chamber at a fourth flow rate for a fourth duration (para [0051] describes flowing a second oxygen precursor in a process chamber at a flow rate between 10 sccm and about 100 sccm for a duration between about 6 seconds and about 120 seconds).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Wu with Lin to further disclose a method including an ALD processing method for forming a seamless dielectric layer that further comprises a first plurality of cycles including a first silicon-containing precursor and a first oxygen-containing precursor and a second plurality of cycles containing a second silicon-containing precursor and a second oxygen-containing precursor wherein each of the precursors have a flow rate and duration in order to provide the advantage of enabling an ALD deposition process to have variables which may be changed in order to provide a dielectric layer of a desired thickness in order to prevent or reduce oxidation of a substrate (Lin, para [0052]) and to further provide the well-known advantage of enabling a first plurality of cycles which may be deposited with a high selectivity and a final cycle which does not require a high selectivity to be performed at a higher flow rate and lower duration.
Regarding Claim 8, the combination of Wu and Lin teaches the method of claim 7, wherein the first flow rate and the second flow rate are substantially the same (para [0049] describes wherein the first flow rate for the first silicon-containing precursor may be between about 50 sccm and about 300 sccm and the second flow rate for the first oxygen-containing precursor may be between about 10 sccm and about 100 sccm wherein a flow rate of 50 sccm for the first flow rate and a flow rate of 50 sccm for the second flow rate would be within the defined ranges and would be substantially the same).
Regarding Claim 9, the combination of Wu and Lin teaches the method of claim 8, wherein the third flow rate and the first flow rate are substantially the same (para [0049] describes wherein the first flow rate for the first silicon-containing precursor may be between about 50 sccm and about 300 sccm and para [0051] describes wherein the third flow rate for the second silicon-containing precursor may be between about 10 sccm and about 300 sccm wherein a flow rate of 50 sccm for the first flow rate and a flow rate of 50 sccm for the third flow rate would be within the defined ranges and would be substantially the same).
Regarding Claim 10, the combination of Wu and Lin teaches the method of claim 9, wherein the fourth flow rate is substantially greater than the second flow rate (para [0049] describes wherein the second flow rate for the first oxygen-containing precursor may be between about 10 sccm and about 100 sccm and para [0051] describes wherein the fourth flow rate for the second oxygen-containing precursor may be between about 10 sccm and about 100 sccm wherein a flow rate of 50 sccm for the second flow rate and a flow rate of 60 sccm for the fourth flow rate would be within the defined ranges and the fourth flow rate would be substantially greater than the second flow rate).
Regarding Claim 11, the combination of Wu and Lin teaches the method of claim 7, wherein the first duration and the second duration are substantially the same (para [0049] describes wherein the first duration for the first silicon-containing precursor may be between about 6 second and 60 seconds and the second duration for the first oxygen-containing precursor may be between about 6 second and 60 seconds wherein a duration of 30 seconds for the first duration and a duration of 30 seconds for the second duration would be within the defined ranges and would be substantially the same).
Regarding Claim 12, the combination of Wu and Lin teaches the method of claim 11, wherein the third duration and the first duration are substantially the same (para [0049] describes wherein the first duration for the first silicon-containing precursor may be between about 6 second and 60 seconds and para [0051] describes wherein the third duration for the second silicon-containing precursor may be between about 6 second and 120 seconds wherein a duration of 30 seconds for the first duration and a duration of 30 seconds for the third duration would be within the defined ranges and would be substantially the same).
Regarding Claim 13, the combination of Wu and Lin teaches the method of claim 12, wherein the fourth duration is substantially greater than the second duration (para [0049] describes wherein the second duration for the first oxygen-containing precursor may be between about 6 second and 60 seconds and para [0051] describes wherein the fourth duration for the second oxygen-containing precursor may be between about 6 second and 120 seconds wherein a duration of 30 seconds for the second duration and a duration of 40 seconds for the fourth duration would be within the defined ranges and the fourth duration would be substantially greater than the second duration).
Regarding Claim 14, the combination of Wu and Lin teaches the method of claim 7, further comprising removing edge portions of the seamless dielectric material to form cavities (232, Fig. 14, para [0030] describes etching back seamless dielectric material layer 232 at an edge portion when forming inter-member openings 249).
Regarding Claim 15, the combination of Wu and Lin teaches the method of claim 14, further comprising depositing dielectric spacers in the cavities (252, Fig. 14, para [0031] describes depositing gate dielectric layer 252 in the cavities 249 wherein gate dielectric layer 252 spaces gate electrode later 254 from seamless dielectric material 232).
Regarding Claim 16, the combination of Wu and Lin teaches the method of claim 7, wherein the first plurality of cycles comprise a first number of cycles (N4, para [0049] describes a set of cycles N4 wherein the number of cycles is between 1 and 20, for example 6 cycles), and the second plurality of cycles comprise a second number of cycles substantially less than the first number of cycles (N6, para [0051] describes a set of cycles N6 wherein the number of cycles is between 1 and 5, for example 3 cycles wherein 3 cycles for the second number of cycles is substantially less than 6 cycles for the first number of cycles).
Regarding Claim 21, Wu teaches a method, comprising:
forming a fin structure from a substrate (212, Fig. 3, para [0017] describes forming a fin-shaped structure 212 from a substrate 202), wherein the fin structure comprises a stack of semiconductor layers (204, Fig. 3, para [0017] describes a stack 204 of semiconductor layers) comprising alternating first (208, Fig. 3, para [0016] describes first semiconductor layers 208) and second semiconductor layers (206, Fig. 3, para [0016] describes second semiconductor layers 206);
forming a sacrificial gate stack on a first portion of the fin structure (220, Fig. 5, para [0019] describes forming a dummy gate stack 220 over a first portion of the fin structure 212;
recessing a second portion of the fin structure (228, Fig. 6, para [0022] describes recessing second portions of the fin structure 212 to form source/drain trenches 228);
removing the second semiconductor layers disposed under the sacrificial gate stack to form openings between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming spacer recesses 230 by at least partially removing the second semiconductor layers 206 forming openings 230 between vertically adjacent first semiconductor layers 208), wherein the openings extend through spaces between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming the spacer recesses 230 wherein the openings formed by the spacer recesses 230 would extend in a channel width (Y direction in Fig. 7) direction from one end of the gate stack 220 to the other and between vertically adjacent first semiconductor layers 208); and
performing an atomic layer deposition process to form a seamless dielectric material in the openings (232, Fig. 8, para [0024] describes forming a spacer material layer 232 including silicon and oxygen through an ALD process in the openings 230).
Wu fails to explicitly teach the atomic layer deposition process, comprising: performing a first plurality of cycles; and then performing a second plurality of cycles.
However, Lin teaches a method of forming a dielectric layer through by performing an atomic layer deposition process (401, Fig. 4A, para [0047] describes forming a silicon oxide dielectric liner 501 using a dielectric gap-filling process 807, 809, 811 and 813 further comprising an ALD process), comprising:
performing a first plurality of cycles (N4, para [0049] describes a set of cycles N4 wherein the number of cycles is between 1 and 20); and then
performing a second plurality of cycles (N6, para [0051] describes a set of cycles N6 wherein the number of cycles is between 1 and 5).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Wu with Lin to further disclose a method including an ALD processing method for forming a seamless dielectric layer that further comprises a first plurality of cycles and then a second plurality of cycles in order to provide the advantage of enabling an ALD deposition process to have variables which may be changed in order to provide a dielectric layer of a desired thickness in order to prevent or reduce oxidation of a substrate (Lin, para [0052]) and to further provide the well-known advantage of enabling a first plurality of cycles which may be deposited with a high selectivity and a final cycle which does not require a high selectivity to be performed at a higher flow rate and lower duration.
Regarding Claim 22, the combination of Wu and Lin teaches the method of claim 21, wherein each cycle of the first plurality of cycles includes flowing a first silicon-containing precursor into a processing chamber (Lin, N4, para [0049] describes flowing a second silicon precursor, herein representing a first silicon precursor, into a process chamber during each of the first plurality of cycles N4) and flowing a first oxygen-containing precursor into the processing chamber (Lin, N4, para [0049] describes flowing a first oxygen precursor in a process chamber during each of the first plurality of cycles N4).
Regarding Claim 23, the combination of Wu and Lin teaches the wherein the first silicon-containing precursor a chemical structure of:
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101
108
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Greyscale
, wherein each R group includes at least two carbons (Lin, 1105, Fig. 11, para [0041] describes wherein the second silicon precursor, herein the first silicon precursor, may be chosen from the same candidate chemicals as the first silicon precursor as described in para [0040] wherein such a material includes SAM24 as depicted by 11-5 in Fig. 11 wherein a chemical structure of SAM24 includes two hydrogen bonded to silicon and further includes two R groups wherein each of the R groups further comprises four carbons bonded to a single nitrogen wherein a resulting chemical structure has an R group including at least two carbons bonded to a single silicon and two hydrogens bonded to the single silicon).
Regarding Claim 24, the combination of Wu and Lin teaches the method of claim 22, wherein the first oxygen-containing precursor comprises ozone (Lin, para [0041] describes wherein the first oxygen-containing precursor may comprise ozone (O3)).
Regarding Claim 25, the combination of Wu and Lin teaches the method of claim 22, wherein each cycle of the second plurality of cycles includes flowing a second silicon-containing precursor into the processing chamber (Lin, N6, para [0051] describes flowing a fourth silicon precursor, herein representing a second silicon precursor into the process chamber during each of the second plurality of cycles N6) and flowing a second oxygen-containing precursor into the processing chamber (Lin, N6, para [0051] describes flowing a second oxygen precursor in a process chamber during each of the second plurality of cycles N6).
Regarding Claim 26, the combination of Wu and Lin teaches the method of claim 25, wherein the second silicon-containing precursor is different from the first silicon-containing precursor (Lin, para [0051] describes wherein the fourth silicon precursor, herein representing the second silicon-containing precursor, may be different from the first silicon-containing precursor).
Regarding Claim 27, the combination of Wu and Lin teaches the method of claim 26, wherein the second oxygen-containing precursor is different from the first oxygen-containing precursor (Lin, para [0051] describes wherein the second oxygen-containing precursor may comprise a different chemical than the first oxygen-containing precursor).
Response to Arguments
Applicant's arguments filed 24 June 2026 have been fully considered but they are not persuasive.
The Applicant argues on page 6, lines 8-17 of the Applicant’s remarks that the prior art of record, Wu, either alone or in combination with the prior art of record, Lin, does not teach the limitations of amended claim 7 wherein the openings extend through spaces between vertically adjacent first semiconductor layers. The Examiner respectfully disagrees. As outlined in the rejection of claim 7 above, Wu teaches removing the second semiconductor layers to form openings between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming spacer recesses 230 by at least partially removing the second semiconductor layers 206 forming openings 230 between vertically adjacent first semiconductor layers 208), wherein the openings extend through spaces between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming the spacer recesses 230 wherein the openings formed by the spacer recesses 230 would extend in a channel width (Y direction in Fig. 7) direction from one end of the gate stack 220 to the other and between vertically adjacent first semiconductor layers 208). Furthermore, language introduced into amended claim 7 does not require the opening to remove an entirety of the first semiconductor layer to form a space along multiple directions. Wu teaches forming a space that remove a portion of the first semiconductor layers along an entire Y, or channel width, direction, thereby forming openings that extend through spaces in the Y, or channel width, direction between vertically adjacent first semiconductor layers. Therefore, amending claim 7 to require “wherein the openings extend through spaces between vertically adjacent first semiconductor layers” is not deemed to patentably distinguish the Applicant’s claimed method from the known method of Wu and Lin.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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