DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species B, claim 7-16 in the reply filed on 22 December 2025 is acknowledged. The traversal is on the grounds that merely identifying claims does not meet the burden to show a necessity of election of species wherein Applicant cites MPEP 806.04(e) to support that simply put, claims are not species. This is not found persuasive because the Examiner further elaborated in the restriction requirement how the species are independent and distinct from one another and the Applicant failed to point out the supposed errors of the election of species. Furthermore, the Examiner discussed how each of the methods are independent and distinct from one another as well as elaborating on how the methods would result in a serious search and/or examination burden for the patentably distinct species as set forth in the requirement. Additionally, should Applicant traverse on the ground that the species, or groupings of patentably indistinct species from which election is required, are not patentably distinct, Applicant is required to submit evidence or identify such evidence of record showing them to be obvious variants or clearly admit on the record that this is the case upon which the Applicant has not indicated in their traversal of the restriction requirement.
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-6 and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species (A and C), there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 22 December 2025.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 30 August 2023 and 11 August 2025 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bone-Fong Wu et al. (US 2021/0336034 A1; hereinafter “Wu”) in view of Cheng-I Lin et al. (US 2020/0020569 A1; hereinafter “Lin”).
Regarding Claim 7, Wu teaches a method, comprising:
forming a fin structure from a substrate (212, Fig. 3, para [0017] describes forming a fin-shaped structure 212 from a substrate 202), wherein the fin structure comprises a stack of semiconductor layers (204, Fig. 3, para [0017] describes a stack 204 of semiconductor layers) comprising alternating first (208, Fig. 3, para [0016] describes first semiconductor layers 208) and second semiconductor layers (206, Fig. 3, para [0016] describes second semiconductor layers 206);
forming a sacrificial gate stack on a first portion of the fin structure (220, Fig. 5, para [0019] describes forming a dummy gate stack 220 over a first portion of the fin structure 212;
recessing a second portion of the fin structure (228, Fig. 6, para [0022] describes recessing second portions of the fin structure 212 to form source/drain trenches 228);
removing the second semiconductor layers disposed under the sacrificial gate stack to form openings between vertically adjacent first semiconductor layers (230, Fig. 7, para [0023] describes forming spacer recesses 230 by at least partially removing the second semiconductor layers 206 forming openings 230 between vertically adjacent first semiconductor layers 208); and
performing an atomic layer deposition process to form a seamless dielectric material in the openings (232, Fig. 8, para [0024] describes forming a spacer material layer 232 including silicon and oxygen through an ALD process in the openings 230).
Wu fails to explicitly teach the atomic layer deposition process, comprising: performing a first plurality of cycles, each cycle including flowing a first silicon-containing precursor into a processing chamber at a first flow rate for a first duration and flowing a first oxygen-containing precursor into the processing chamber at a second flow rate for a second duration; and then performing a second plurality of cycles, each cycle including flowing a second silicon-containing precursor different from the first silicon-containing precursor into the processing chamber at a third flow rate for a third duration and flowing a second oxygen-containing precursor into the processing chamber at a fourth flow rate for a fourth duration.
However, Lin teaches a method of forming a dielectric layer through by performing an atomic layer deposition process (401, Fig. 4A, para [0047] describes forming a silicon oxide dielectric liner 501 using a dielectric gap-filling process 807, 809, 811 and 813 further comprising an ALD process), comprising:
performing a first plurality of cycles (N4, para [0049] describes a set of cycles N4 wherein the number of cycles is between 1 and 20), each cycle including flowing a first silicon-containing precursor into a processing chamber at a first flow rate for a first duration (para [0049] describes flowing a second silicon precursor, herein representing a first silicon precursor, into a process chamber at a flow rate between 50 sccm and about 300 sccm for a duration between about 6 seconds and about 60 seconds) and flowing a first oxygen-containing precursor into the processing chamber at a second flow rate for a second duration (para [0049] describes flowing a first oxygen precursor in a process chamber at a flow rate between 10 sccm and about 100 sccm for a duration between about 6 seconds and about 60 seconds); and then
performing a second plurality of cycles (N6, para [0051] describes a set of cycles N6 wherein the number of cycles is between 1 and 5), each cycle including flowing a second silicon-containing precursor different from the first silicon-containing precursor into the processing chamber at a third flow rate for a third duration (para [0051] describes flowing a fourth silicon precursor, herein representing a second silicon precursor, that may be different from the first silicon precursor into the process chamber at a flow rate between 10 sccm and about 300 sccm for a duration between about 6 seconds and about 120 seconds) and flowing a second oxygen-containing precursor into the processing chamber at a fourth flow rate for a fourth duration (para [0051] describes flowing a second oxygen precursor in a process chamber at a flow rate between 10 sccm and about 100 sccm for a duration between about 6 seconds and about 120 seconds).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Wu with Lin to further disclose a method including an ALD processing method for forming a seamless dielectric layer that further comprises a first plurality of cycles including a first silicon-containing precursor and a first oxygen-containing precursor and a second plurality of cycles containing a second silicon-containing precursor and a second oxygen-containing precursor wherein each of the precursors have a flow rate and duration in order to provide the advantage of enabling an ALD deposition process to have variables which may be changed in order to provide a dielectric layer of a desired thickness in order to prevent or reduce oxidation of a substrate (Lin, para [0052]) and to further provide the well-known advantage of enabling a first plurality of cycles which may be deposited with a high selectivity and a final cycle which does not require a high selectivity to be performed at a higher flow rate and lower duration.
Regarding Claim 8, the combination of Wu and Lin teaches the method of claim 7, wherein the first flow rate and the second flow rate are substantially the same (para [0049] describes wherein the first flow rate for the first silicon-containing precursor may be between about 50 sccm and about 300 sccm and the second flow rate for the first oxygen-containing precursor may be between about 10 sccm and about 100 sccm wherein a flow rate of 50 sccm for the first flow rate and a flow rate of 50 sccm for the second flow rate would be within the defined ranges and would be substantially the same).
Regarding Claim 9, the combination of Wu and Lin teaches the method of claim 8, wherein the third flow rate and the first flow rate are substantially the same (para [0049] describes wherein the first flow rate for the first silicon-containing precursor may be between about 50 sccm and about 300 sccm and para [0051] describes wherein the third flow rate for the second silicon-containing precursor may be between about 10 sccm and about 300 sccm wherein a flow rate of 50 sccm for the first flow rate and a flow rate of 50 sccm for the third flow rate would be within the defined ranges and would be substantially the same).
Regarding Claim 10, the combination of Wu and Lin teaches the method of claim 9, wherein the fourth flow rate is substantially greater than the second flow rate (para [0049] describes wherein the second flow rate for the first oxygen-containing precursor may be between about 10 sccm and about 100 sccm and para [0051] describes wherein the fourth flow rate for the second oxygen-containing precursor may be between about 10 sccm and about 100 sccm wherein a flow rate of 50 sccm for the second flow rate and a flow rate of 60 sccm for the fourth flow rate would be within the defined ranges and the fourth flow rate would be substantially greater than the second flow rate).
Regarding Claim 11, the combination of Wu and Lin teaches the method of claim 7, wherein the first duration and the second duration are substantially the same (para [0049] describes wherein the first duration for the first silicon-containing precursor may be between about 6 second and 60 seconds and the second duration for the first oxygen-containing precursor may be between about 6 second and 60 seconds wherein a duration of 30 seconds for the first duration and a duration of 30 seconds for the second duration would be within the defined ranges and would be substantially the same).
Regarding Claim 12, the combination of Wu and Lin teaches the method of claim 11, wherein the third duration and the first duration are substantially the same (para [0049] describes wherein the first duration for the first silicon-containing precursor may be between about 6 second and 60 seconds and para [0051] describes wherein the third duration for the second silicon-containing precursor may be between about 6 second and 120 seconds wherein a duration of 30 seconds for the first duration and a duration of 30 seconds for the third duration would be within the defined ranges and would be substantially the same).
Regarding Claim 13, the combination of Wu and Lin teaches the method of claim 12, wherein the fourth duration is substantially greater than the second duration (para [0049] describes wherein the second duration for the first oxygen-containing precursor may be between about 6 second and 60 seconds and para [0051] describes wherein the fourth duration for the second oxygen-containing precursor may be between about 6 second and 120 seconds wherein a duration of 30 seconds for the second duration and a duration of 40 seconds for the fourth duration would be within the defined ranges and the fourth duration would be substantially greater than the second duration).
Regarding Claim 14, the combination of Wu and Lin teaches the method of claim 7, further comprising removing edge portions of the seamless dielectric material to form cavities (232, Fig. 14, para [0030] describes etching back seamless dielectric material layer 232 at an edge portion when forming inter-member openings 249).
Regarding Claim 15, the combination of Wu and Lin teaches the method of claim 14, further comprising depositing dielectric spacers in the cavities (252, Fig. 14, para [0031] describes depositing gate dielectric layer 252 in the cavities 249 wherein gate dielectric layer 252 spaces gate electrode later 254 from seamless dielectric material 232).
Regarding Claim 16, the combination of Wu and Lin teaches the method of claim 7, wherein the first plurality of cycles comprise a first number of cycles (N4, para [0049] describes a set of cycles N4 wherein the number of cycles is between 1 and 20, for example 6 cycles), and the second plurality of cycles comprise a second number of cycles substantially less than the first number of cycles (N6, para [0051] describes a set of cycles N6 wherein the number of cycles is between 1 and 5, for example 3 cycles wherein 3 cycles for the second number of cycles is substantially less than 6 cycles for the first number of cycles).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898