DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 10/30/25.
Applicant’s election without traverse of Group I in the reply filed on 12/9/25 is acknowledged. Applicant has canceled nonelected claims 8-14. Added claims 21-27 are in the elected group.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Vias in semiconductor package
The abstract of the disclosure is objected to because it exceeds the permissible length of 150 words. See MPEP § 608.01(b)(I)(C).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, and 6-7 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2022/0157757 A1 (“Seok”).
Seok teaches, for example:
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Seok teaches:
1. A method of manufacturing a semiconductor device, the method comprising:
embedding a first semiconductor component (e.g. die 200, see para 26 and e.g. Fig. 12) in a first core substrate (e.g. comprising “molding portion” 310, see e.g. para 34 and Fig. 13);
embedding a second semiconductor component (e.g. “second die” 500, see e.g. para 54 and e.g. Fig. 21) in a second core substrate (e.g. comprising “second molding portion” 320, see e.g. para 53 and Fig. 21);
attaching the second core substrate to the first core substrate (see e.g. para 119-121, especially para 121 “DL2 may be bonded to the top surface of …. DL1”), wherein the attaching the second core substrate to the first core substrate forms a multi-layer core substrate; and
forming a first plurality of through vias (e.g. “penetration electrodes 350”, see e.g. para 35 and Fig. 25) extending through the multi-layer core substrate,
wherein the first plurality of through vias are electrically coupled to the first semiconductor component and to the second semiconductor component (see e.g. Fig. 26, wherein at least some vias 350 electrically contact DL1 through 400 and/or 220, and wherein other vias 350 contact DL2 through 100 and/or 640 and/or 540).
3. The method of claim 1, further comprising:
forming a first redistribution layer (e.g. 220) on a first side (e.g. bottom as shown in Fig. 26) of the first core substrate, wherein the first redistribution layer comprises first conductive features (vias or traces within 220), the first conductive features electrically coupling the first semiconductor component to one of the first plurality of through vias (see e.g. Fig. 26).
4. The method of claim 1, wherein the forming the first plurality of through vias comprises: forming a plurality of through holes through the multi-layer core substrate; and plating a conductive material along sidewalls of the plurality of through holes (see e.g. Figs. 24-25 and e.g. para 130-131; the plating fills the entire hole, including along the sidewalls, see e.g. Fig. 25).
6. The method of claim 1, further comprising: embedding a third semiconductor component (e.g. “third die 600”, see e.g. para 61-62) in a third core substrate (comprising e.g. 330); and attaching the third core substrate to the second core substrate on an opposite side of the second core substrate from the first core substrate (see e.g. Figs. 24 and 26 and e.g. para 67), wherein the third core substrate is part of the multi-layer core substrate (see e.g. Figs. 24 or 26).
7. The method of claim 1, wherein the first core substrate has a first thickness and the second core substrate has a second thickness different from the first thickness (the first core substrate can be interpreted as comprising e.g. 310, 320, 200, and 500, see e.g. Fig. 22; the second core substrate can be interpreted as comprising e.g. 330 and 600, which are attached thereto, see e.g. Fig. 23).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 15-17, 19, 21-22, and 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seok in view of US 2016/0343685 A1 (“Lin”).
Re claim 2, Seok teaches claim 1, but not wherein attaching the second core substrate to the first core substrate comprises: depositing a first resin film over the first core substrate; placing the second core substrate over the first resin film; and curing the first resin film.
Lin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Seok, wherein attaching the second core substrate to the first core substrate comprises: depositing a first resin film (e.g. 180, see e.g. para 47 and e.g. Fig. 3A) over the first core substrate (e.g. comprising 120A, 110A, and 130A); placing the second core substrate (comprising e.g. 120B, 110B, and 130B) over the first resin film; and curing the first resin film (while not explicitly taught to be cured, Lin teaches “bonding” by use of adhesive 180, see e.g. para 47; it is well-known and very obvious to one of ordinary skill in the art during bonding to cure the adhesive to make the bond strong; if curing does not occur, the two items are not well bonded and could fall apart).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Seok. The motivation to do so is that the combination produces the predictable results of attaching the first and second core substrates together via RDL-to-RDL bonding, which allows for the chips to have different sizes than each other (see e.g. para 6, 21).
Regarding the curing, it has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Seok teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
15. A method of manufacturing a semiconductor device, the method comprising:
forming a first substrate layer, wherein the first substrate layer comprises: a first semiconductor component (e.g. die 200, see para 26 and e.g. Fig. 12) embedded in a first core substrate (e.g. comprising “molding portion” 310, see e.g. para 34 and Fig. 13); a first redistribution layer (e.g. 220) of the first substrate layer formed over the first core substrate;
forming a second substrate layer, wherein the second substrate layer comprises: a second semiconductor component (e.g. “second die” 500, see e.g. para 54 and e.g. Fig. 21; could be interpreted as also comprising e.g. 600) embedded in a second core substrate (e.g. comprising “second molding portion” 320, see e.g. para 53 and Fig. 21; could be interpreted as also comprising 330); a first redistribution layer of the second substrate layer formed over the second core substrate; and
bonding the second substrate layer to the first substrate layer (see e.g. para 119-121, especially para 121 “DL2 may be bonded to the top surface of …. DL1”); and
forming a first through via (e.g. “penetration electrodes 350”, see e.g. para 35 and Fig. 25) extending through the first substrate layer and the second substrate layer,
wherein the first through via is electrically coupled to the first semiconductor component (see e.g. Fig. 26, wherein at least some vias 350 electrically contact DL1 through 400 and/or 220, and wherein other vias 350 contact DL2 through 100 and/or 640 and/or 540).
Seok does not teach: wherein the first substrate layer comprises a second redistribution layer of the first substrate layer formed on an opposite side of the first core substrate from the first redistribution layer of the first substrate layer; or wherein the second substrate layer comprises a second redistribution layer of the second substrate layer formed on an opposite side of the second core substrate from the first redistribution layer of the second substrate layer.
Lin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Seok wherein the first substrate layer comprises a second redistribution layer of the first substrate layer formed on an opposite side of the first core substrate from the first redistribution layer of the first substrate layer; or wherein the second substrate layer comprises a second redistribution layer of the second substrate layer formed on an opposite side of the second core substrate from the first redistribution layer of the second substrate layer (it would be obvious to form RDLs on both sides of each chip 200, 500, and 600 of Seok because Lin teaches bonding the chips together by RDL-to-RDL bonding).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Seok. The motivation to do so is that the combination produces the predictable results of attaching the first and second core substrates together via RDL-to-RDL bonding, which allows for the chips to have different sizes than each other (see e.g. para 6, 21).
Seok and Lin together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
16. The method of claim 15, further comprising:
forming a third substrate layer (comprising e.g. 330 and 600), wherein the third substrate layer comprises: a third semiconductor component (e.g. 600) embedded in a third core substrate (comprising e.g. 330); a first redistribution layer (e.g. 620) of the third substrate layer formed over the third core substrate; and a second redistribution layer of the third substrate layer formed on an opposite side of the third core substrate from the first redistribution layer of the third substrate layer (Lin would suggest to form RDLs on both sides of each chip 200, 500, and 600 of Seok because Lin teaches bonding the chips together by RDL-to-RDL bonding); and bonding the third substrate layer to the second substrate layer on an opposite side from the first substrate layer (see Fig. 23; see Lin Fig. 3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Seok. The motivation to do so is that the combination produces the predictable results of attaching the first and second core substrates together via RDL-to-RDL bonding, which allows for the chips to have different sizes than each other (see e.g. para 6, 21).
17. The method of claim 16, further comprising forming a second through via (other 350s) extending through the first substrate layer, the second substrate layer, and the third substrate layer, wherein the second through via is electrically coupled to the second semiconductor component (see e.g. Fig. 26).
19. The method of claim 15, further comprising forming a local through core substrate via through the first core substrate (see e.g. 240).
Seok teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
21. A method of forming a device, the method comprising:
providing a first semiconductor component (e.g. die 200, see para 26 and e.g. Fig. 12) embedded in a first core substrate (e.g. comprising “molding portion” 310, see e.g. para 34 and Fig. 13);
forming a first redistribution layer (e.g. 220) on a first side (e.g. bottom as shown in Fig. 26) of the first core substrate;
providing a second semiconductor component (e.g. “second die” 500, see e.g. para 54 and e.g. Fig. 21) embedded in a second core substrate (e.g. comprising “second molding portion” 320, see e.g. para 53 and Fig. 21);
Seok does not explicitly teach:
forming a second redistribution layer on a second side of the first core substrate opposite the first side;
depositing a first resin film over the second redistribution layer;
bonding a third redistribution layer on a third side of the second core substrate to the second redistribution layer by the first resin film;
forming a fourth redistribution layer on a fourth side of the second core substrate opposite the third side; and
forming a through hole via extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer.
Lin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Seok:
forming a second redistribution layer on a second side of the first core substrate opposite the first side (e.g. forming a RDL such as Lin’s 130A on the top side of 110A, which would be equivalent to Seok’s 200);
depositing a first resin film (e.g. Lin’s 180) over the second redistribution layer;
bonding a third redistribution layer (e.g. Lin’s 130B, which is equivalent to e.g. Seok’s 520) on a third side of the second core substrate to the second redistribution layer by the first resin film;
forming a fourth redistribution layer on a fourth side of the second core substrate opposite the third side (it would be obvious to form RDLs on both sides of each chip 200, 500, and 600 of Seok because Lin teaches bonding the chips together by RDL-to-RDL bonding); and
forming a through hole via (Seok’s 350) extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer (Seok’s 350 extends from the very top of the layers DL1, DL2, and DL3 to the very bottom thereof; thus, in combination with Lin, it would extend through all of the layers thereof, including the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Seok. The motivation to do so is that the combination produces the predictable results of attaching the first and second core substrates together via RDL-to-RDL bonding, which allows for the chips to have different sizes than each other (see e.g. para 6, 21).
Seok and Lin together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
22. The method of claim 21, further comprising: depositing a second resin film over the fourth redistribution layer; providing a third semiconductor component embedded in a third core substrate; bonding a fifth redistribution layer on a fifth side of the third core substrate to the fourth redistribution layer by the second resin film; and forming a sixth redistribution layer on a sixth side of the third core substrate opposite the fifth side (Seok has three layers DL1, DL2, and DL3, and it would have been obvious to connect each two chips thereof together by RDL-to-RDL bonding; each RDL-to-RDL bonding would thus have a resin film therebetween).
25. The method of claim 21, wherein the first core substrate has a first thickness and the second core substrate has a second thickness different from the first thickness (the first core substrate could comprise e.g. 310 and 320 while the second core substrate comprises e.g. 330; or the first core substrate could comprise e.g. 310 while the second core substrate comprises e.g. 320 and 330).
Furthermore, Applicant has not disclosed that the claimed size difference is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984);
To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
26. The method of claim 21 further comprising providing a fourth semiconductor component (e.g. 500) embedded within the second core substrate.
27. The method of claim 21, wherein the first semiconductor component is an integrated passive device, an active chip (see e.g. para 26), an integrated voltage regulator, or a multilayer ceramic capacitor.
Allowable Subject Matter
Claim(s) 5, 18, 20, and 23-24 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 5, 18, 20, 23, or 24, including:
5. The method of claim 1, further comprising bonding a semiconductor chip over a top surface of the multi-layer core substrate,
wherein the semiconductor chip forms a die shadow power domain projection over the multi-layer core substrate,
wherein the multi-layer core substrate has a component density within the die shadow power domain projection of 4 or more components per square millimeter.
18. The method of claim 15, wherein embedding the first semiconductor component in the first core substrate comprises:
drilling a first hole through the first core substrate;
attaching a polyimide film tape to one side of the first core substrate;
performing a pick and place for the first semiconductor component onto the polyimide film tape in the first hole; and
removing the polyimide film tape.
20. The method of claim 15, wherein forming the first redistribution layer of the first substrate layer comprises:
depositing a first dielectric material over the first core substrate through a film lamination process;
curing the first dielectric material forming a first dielectric layer;
forming a blind via opening through a laser process; and
forming the blind via by plating a conductive material into the blind via opening.
23. The method of claim 22, further comprising:
forming a first redistribution build up structure over the sixth redistribution layer;
bonding a semiconductor chip to the first redistribution build up structure opposite the sixth redistribution layer;
forming a second redistribution build up structure under the first redistribution layer; and
bonding a substrate to the second redistribution build up structure by external connectors.
24. The method of claim 23, further comprising provisioning the semiconductor chip so that the semiconductor chip has a die shadow projection through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, the fourth redistribution layer, the fifth redistribution layer, the third core substrate and the sixth redistribution layer,
wherein a component density exists within the die shadow projection, the component density being 4 or more components per square millimeter.
The other claims each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896