DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0157757 A1 (“Seok”) in view of US 2016/0343685 A1 (“Lin”).
Seok teaches, for example:
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Seok teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
15. A method of manufacturing a semiconductor device, the method comprising:
forming a first substrate layer, wherein the first substrate layer comprises: a first semiconductor component (e.g. die 200, see para 26 and e.g. Fig. 12) embedded in a first core substrate (e.g. comprising “molding portion” 310, see e.g. para 34 and Fig. 13); a first redistribution layer (e.g. 220) of the first substrate layer formed over the first core substrate;
forming a second substrate layer, wherein the second substrate layer comprises: a second semiconductor component (e.g. “second die” 500, see e.g. para 54 and e.g. Fig. 21; could be interpreted as also comprising e.g. 600) embedded in a second core substrate (e.g. comprising “second molding portion” 320, see e.g. para 53 and Fig. 21; could be interpreted as also comprising 330); a first redistribution layer of the second substrate layer formed over the second core substrate; and
bonding the second substrate layer to the first substrate layer (see e.g. para 119-121, especially para 121 “DL2 may be bonded to the top surface of …. DL1”); and
forming a first through via (e.g. “penetration electrodes 350”, see e.g. para 35 and Fig. 25) extending through the first substrate layer and the second substrate layer,
wherein the first through via is electrically coupled to the first semiconductor component (see e.g. Fig. 26, wherein at least some vias 350 electrically contact DL1 through 400 and/or 220, and wherein other vias 350 contact DL2 through 100 and/or 640 and/or 540).
Seok does not teach: wherein the first substrate layer comprises a second redistribution layer of the first substrate layer formed on an opposite side of the first core substrate from the first redistribution layer of the first substrate layer; or wherein the second substrate layer comprises a second redistribution layer of the second substrate layer formed on an opposite side of the second core substrate from the first redistribution layer of the second substrate layer.
Lin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Seok wherein the first substrate layer comprises a second redistribution layer of the first substrate layer formed on an opposite side of the first core substrate from the first redistribution layer of the first substrate layer; or wherein the second substrate layer comprises a second redistribution layer of the second substrate layer formed on an opposite side of the second core substrate from the first redistribution layer of the second substrate layer (it would be obvious to form RDLs on both sides of each chip 200, 500, and 600 of Seok because Lin teaches bonding the chips together by RDL-to-RDL bonding).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Seok. The motivation to do so is that the combination produces the predictable results of attaching the first and second core substrates together via RDL-to-RDL bonding, which allows for the chips to have different sizes than each other (see e.g. para 6, 21).
Seok and Lin together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
16. The method of claim 15, further comprising:
forming a third substrate layer (comprising e.g. 330 and 600), wherein the third substrate layer comprises: a third semiconductor component (e.g. 600) embedded in a third core substrate (comprising e.g. 330); a first redistribution layer (e.g. 620) of the third substrate layer formed over the third core substrate; and a second redistribution layer of the third substrate layer formed on an opposite side of the third core substrate from the first redistribution layer of the third substrate layer (Lin would suggest to form RDLs on both sides of each chip 200, 500, and 600 of Seok because Lin teaches bonding the chips together by RDL-to-RDL bonding); and bonding the third substrate layer to the second substrate layer on an opposite side from the first substrate layer (see Fig. 23; see Lin Fig. 3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Seok. The motivation to do so is that the combination produces the predictable results of attaching the first and second core substrates together via RDL-to-RDL bonding, which allows for the chips to have different sizes than each other (see e.g. para 6, 21).
17. The method of claim 16, wherein the step of bonding the second substrate layer to the first substrate layer includes bringing the first redistribution layer of the first substrate layer and the first redistribution layer of the second substrate layer in a face-to-face orientation so the first redistribution layer of the first substrate layer faces the first redistribution layer of the second substrate layer after the bonding (see e.g. Lin’s Fig. 3A wherein the RDLs are in a face-to-face arrangement).
19. The method of claim 15, further comprising forming a local through core substrate via through the first core substrate (see e.g. 240).
Claim(s) 1, 3, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0102309 A1 (“Lee”) in view of US 2021/0233897 A1 (“Jang”).
Lee teaches, for example, the structure shown in Fig. 1, which is manufactured by the method shown in Figs. 5-39:
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Lee teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A method of manufacturing a semiconductor device, the method comprising:
provisioning a first core substrate (e.g. comprising 100 and 120, as shown in e.g. Fig. 5) having a hole therein; and
placing a first semiconductor component (e.g. 200, see e.g. Fig. 6) in the hole in the first core substrate.
Lee does not explicitly teach:
provisioning a second core substrate having a second hole therein;
placing a second semiconductor component in the hole in the second core substrate;
attaching the second core substrate to the first core substrate, wherein the attaching the second core substrate to the first core substrate forms a multi-layer core substrate; and
forming a first plurality of through vias extending through the multi-layer core substrate, wherein the first plurality of through vias are electrically coupled to the first semiconductor component and to the second semiconductor component.
However, Lee teaches a similar method:
attaching a second core substrate having a semiconductor component in a hole (see chips 620 and 630 in package 600, Fig. 40) therein to the first core substrate, wherein the attaching the second core substrate to the first core substrate forms a multi-layer core substrate (see Fig. 40); and
forming a first plurality of through vias (e.g. 123, 125) extending through the multi-layer core substrate (they extend at least partly through the multi-layer core substrate of Fig. 40), wherein the first plurality of through vias are electrically coupled to the first semiconductor component (e.g. 200) and to the second semiconductor component (e.g. 630) (see Fig. 40, wherein the vias 123 and 125 connect via 302 to 200 and connect via 376, 350, 650, 610, and 640 to 630).
Jang teaches, for example:
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Jang teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Lee:
provisioning a second core substrate (e.g. 230 for 200-2 in Fig. 3) having a second hole therein;
placing a second semiconductor component (e.g. 210 in 200-2 in Fig. 3) in the hole in the second core substrate;
attaching the second core substrate to the first core substrate (see e.g. Fig. 4), wherein the attaching the second core substrate to the first core substrate forms a multi-layer core substrate (see e.g. Fig. 4); and
forming a first plurality of through vias extending through the multi-layer core substrate (see e.g. Fig. 4, wherein through-electrodes SV and FV are labeled in the lowest package 200-1 but is shown in 200-2 through 200-4), wherein the first plurality of through vias are electrically coupled to the first semiconductor component and to the second semiconductor component (see e.g. Fig. 4, wherein RCLs on the bottom of each 210 connect to each SV, FV).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Jang to the invention of Lee, specifically changing the type of package 600 added to the top of the package of Fig. 1 with a stack of identical or very similar devices (Jang, Figs. 3-4).
The motivation to do so is that Lee discloses that the type of package stacked onto the device of Fig. 1 in Fig. 40 is merely one example thereof, and that other packages having a different number of chips and a different “mounting manner” could be used (see para 163), and the combination produces the predictable results of stacking similar/identical packages in a way that may allow for reduced package size (see e.g. para 2-4, 39, 40).
Lee and Jang together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
3. The method of claim 1, further comprising:
forming a first redistribution layer on a first side of the first core substrate, wherein the first redistribution layer comprises first conductive features, the first conductive features electrically coupling the first semiconductor component to one of the first plurality of through vias (see Lee, e.g. Fig. 39, having RDLs 300 and 350 on opposite sides of the first core substrate).
6. The method of claim 1, further comprising: embedding a third semiconductor component in a third core substrate; and attaching the third core substrate to the second core substrate on an opposite side of the second core substrate from the first core substrate, wherein the third core substrate is part of the multi-layer core substrate (see Jang’s Figs. 3-4; arguments essentially the same as discussed in claim 1, except that it is also obvious to have more layers of packages 200-1 through 200-4 because of the additional chips housed therein).
7. The method of claim 1, wherein the first core substrate has a first thickness and the second core substrate has a second thickness different from the first thickness (this is obvious, because Jang discloses that the chips may have thicknesses in the range of 20-40 micrometers in para 31; if one chip has a different thickness than another, than the core substrate in Lee’s Fig. 5 would need to be thicker for the thicker chip than for the thinner chip).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0102309 A1 (“Lee”) in view of US 2021/0233897 A1 (“Jang”) and US 2016/0343685 A1 (“Lin”).
Lee and Jang teach claim 1, but not wherein attaching the second core substrate to the first core substrate comprises: depositing a first resin film over the first core substrate; placing the second core substrate over the first resin film; and curing the first resin film.
Lin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Seok, wherein attaching the second core substrate to the first core substrate comprises: depositing a first resin film (e.g. 180, see e.g. para 47 and e.g. Fig. 3A) over the first core substrate (e.g. comprising 120A, 110A, and 130A); placing the second core substrate (comprising e.g. 120B, 110B, and 130B) over the first resin film; and curing the first resin film (while not explicitly taught to be cured, Lin teaches “bonding” by use of adhesive 180, see e.g. para 47; it is well-known and very obvious to one of ordinary skill in the art during bonding to cure the adhesive to make the bond strong; if curing does not occur, the two items are not well bonded and could fall apart).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Lee and Jang.
The motivation to do so is that the combination produces the predictable results of attaching the first and second core substrates together via RDL-to-RDL bonding, which allows for the chips to have different sizes than each other (see e.g. para 6, 21).
Regarding the curing, it has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0102309 A1 (“Lee”) in view of US 2021/0233897 A1 (“Jang”) and US 2022/0157757 A1 (“Seok”).
Re claim 4, Lee and Jang teach claim 1, but not wherein the forming the first plurality of through vias comprises: forming a plurality of through holes through the multi-layer core substrate; and plating a conductive material along sidewalls of the plurality of through holes.
Seok teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Lee and Jang wherein the forming the first plurality of through vias comprises: forming a plurality of through holes through the multi-layer core substrate; and plating a conductive material along sidewalls of the plurality of through holes (see e.g. Figs. 24-25 and e.g. para 130-131; the plating fills the entire hole, including along the sidewalls, see e.g. Fig. 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Seok to the invention of Lee and Jang. The motivation to do so is that the combination produces the predictable results of forming the vias through well-known processes such as electroplating using a seed material (para 131) and planarizing (see e.g. para 132), which can have benefits of adequately forming a metallic via (see e.g. para 130) having a planar surface (e.g. para 132).
Claim(s) 21-23 and 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0102309 A1 (“Lee”) in view of US 2021/0233897 A1 (“Jang”), US 2016/0343685 A1 (“Lin”), and US 2022/0157757 A1 (“Seok”).
Lee teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
21. A method of forming a device, the method comprising:
providing a first semiconductor component (e.g. 200, see e.g. Fig. 6) embedded in a first core substrate (e.g. comprising 100 and 120, as shown in e.g. Fig. 5);
forming a first redistribution layer (comprising, e.g. 310, 312, and other parts of 300, see e.g. Figs. 7-9) on a first outermost side (top, as shown in Fig. 8) of the first core substrate; and
forming a second redistribution layer (comprising e.g. 360, 382, 380, 390, see e.g. Figs. 14-23) on a second side of the first core substrate opposite the outermost first side.
Lee does not explicitly teach:
providing a second semiconductor component embedded in a second core substrate;
bonding a third redistribution layer on a third side of the second core substrate to the second redistribution layer by the first resin film;
forming a fourth redistribution layer on a fourth side of the second core substrate opposite the third side.
Jang teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Lee:
providing a second semiconductor component (Jang: e.g. 210 in 200-2 in Fig. 3) embedded in a second core substrate (Jang: e.g. 230 for 200-2 in Fig. 3);
bonding a third redistribution layer on a third side of the second core substrate to the second redistribution layer (Jang: see e.g. Fig. 4, wherein stacked almost identical chips are attached; using the chip of Fig. 1 of Lee, this would attach a third RDL on the second core substrate to the second RDL); and
forming a fourth redistribution layer on a fourth side of the second core substrate opposite the third side (Jang: see e.g. Fig. 4, wherein stacked almost identical chips are attached; using the chip of Fig. 1 of Lee, this would necessitate the fourth RDL on the fourth side of the second core substrate).
Lee and Jang do not explicitly teach:
depositing a first resin film over the second redistribution layer;
and [bonding a third redistribution layer on a third side of the second core substrate to the second redistribution layer] by the first resin film;
Lin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Lee and Jang,
depositing a first resin film (e.g. 180, see e.g. para 47 and e.g. Fig. 3A) over the second redistribution layer (e.g. comprising 120A, 110A, and 130A); and
[bonding a third redistribution layer on a third side of the second core substrate to the second redistribution layer by the first resin film] (“bonding” by use of adhesive 180, see e.g. para 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lin to the invention of Lee and Jang.
The motivation to do so is that the combination produces the predictable results of attaching the first and second core substrates together via RDL-to-RDL bonding, which allows for the chips to have different sizes than each other (see e.g. para 6, 21).
Lee, Jang, and Lin do not explicitly teach forming a through hole via extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer.
Seok teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Lee, Jang, and Lin forming a through hole via (Seok’s 350, see e.g. Fig. 6) extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer (Seok’s RDL extends from the very top of the topmost core substrate to the very bottom of the lowest core substrate, so in combination, would meet the claimed limitations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Seok to the invention of Lee, Jang, and Lin. The motivation to do so is that the combination produces the predictable results of allowing a penetration electrode having a seed layer extend through the various layers from the top to the bottom.
Lee, Jang, Lin, and Seok together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
22. The method of claim 21, further comprising:
depositing a second resin film over the fourth redistribution layer;
providing a third semiconductor component embedded in a third core substrate;
bonding a fifth redistribution layer on a fifth side of the third core substrate to the fourth redistribution layer by the second resin film; and
forming a sixth redistribution layer on a sixth side of the third core substrate opposite the fifth side (the device of Jang has four core substrates so in combination would require these limitations).
23. The method of claim 22, further comprising:
forming a first redistribution build up structure over the sixth redistribution layer;
bonding a semiconductor chip to the first redistribution build up structure opposite the sixth redistribution layer;
forming a second redistribution build up structure under the first redistribution layer; and
bonding a substrate to the second redistribution build up structure by external connectors (the device of Jang has four core substrates so in combination would require these limitations).
25. The method of claim 21, wherein the first core substrate has a first thickness and the second core substrate has a second thickness different from the first thickness (this is obvious, because Jang discloses that the chips may have thicknesses in the range of 20-40 micrometers in para 31; if one chip has a different thickness than another, than the core substrate in Lee’s Fig. 5 would need to be thicker for the thicker chip than for the thinner chip).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
26. The method of claim 21 further comprising providing a fourth semiconductor component embedded within the second core substrate (the device of Jang has four core substrates so in combination would require these limitations).
27. The method of claim 21, wherein the first semiconductor component is an integrated passive device, an active chip (“semiconductor chip”), an integrated voltage regulator, or a multilayer ceramic capacitor.
Allowable Subject Matter
Claim(s) 5, 18, 20, and 24 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 5, 18, 20, 23, or 24, including:
5. The method of claim 1, further comprising bonding a semiconductor chip over a top surface of the multi-layer core substrate,
wherein the semiconductor chip forms a die shadow power domain projection over the multi-layer core substrate,
wherein the multi-layer core substrate has a component density within the die shadow power domain projection of 4 or more components per square millimeter.
18. The method of claim 15, wherein embedding the first semiconductor component in the first core substrate comprises:
drilling a first hole through the first core substrate;
attaching a polyimide film tape to one side of the first core substrate;
performing a pick and place for the first semiconductor component onto the polyimide film tape in the first hole; and
removing the polyimide film tape.
20. The method of claim 15, wherein forming the first redistribution layer of the first substrate layer comprises:
depositing a first dielectric material over the first core substrate through a film lamination process;
curing the first dielectric material forming a first dielectric layer;
forming a blind via opening through a laser process; and
forming the blind via by plating a conductive material into the blind via opening.
24. The method of claim 23, further comprising provisioning the semiconductor chip so that the semiconductor chip has a die shadow projection through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, the fourth redistribution layer, the fifth redistribution layer, the third core substrate and the sixth redistribution layer,
wherein a component density exists within the die shadow projection, the component density being 4 or more components per square millimeter.
The other claims each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are either not persuasive (as per claim 15), or moot in view of the new ground(s) of rejection (as per claim 1 and 21).
Regarding claim 15, Applicant argues (5/27/26 remarks, pages 12-13) “the asserted first redistribution layer 220 is not ‘formed over’ the asserted first core substrate 310”. However, the claim does not specify and order to the formation of elements. In Fig. 13, it is clear that 220 is higher than, and thus over, at least some of 310. The claim does not require that the first redistribution layer is formed over the entirety of the first core substrate. Thus, the rejection is deemed proper and maintained.
Claims 1 and 21 have new grounds of rejection to respond to their claim amendments.
Conclusion
Conclusion / Finality
Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
US 2020/0411445 A1 (“Chen”) teaches stacking of encapsulated chips (see e.g. cover figure).
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
Prosecution Insights