DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 3 as being unpatentable over Huang (PG Pub. No. US 2021/0280560 A1) in view of Furuya et al. (PG Pub. No. US 2007/0222078 A1).
Regarding claim 1, Huang teaches a semiconductor device (¶ 0079: 10F), comprising:
a substrate (¶ 0043: composite structure 100 including a wafer portion);
a bottom dielectric layer (¶¶ 0055-0056: insulating layers 201, 209 and/or 211) positioned on the substrate (fig. 6: 201/209/211 positioned on 100);
an interconnector structure (¶ 0055: conductive layer 207) positioned on the bottom dielectric layer (fig. 6: 207 positioned on 201/209/211);
a top glue layer (¶¶ 0062, 0078: layer 219, including material with an adhesive property) conformally positioned on the bottom dielectric layer dielectric and surrounding the interconnector structure (fig. 6: 219 conformally positioned at least indirectly on 201/209/211 and surrounds 207); and
a top dielectric layer (¶ 0079: 315) positioned surrounding the top glue layer (fig. 6: 315 positioned surrounding at least a portion of 219);
wherein a top surface of the top glue layer and a top surface of the interconnector structure are substantially coplanar (fig. 6: top surfaces of 219 and 207 are substantially coplanar),
wherein the top dielectric layer is porous (¶ 0079: 315 is a porous layer).
Huang fails to teach a top surface of the top dielectric layer is substantially coplanar with the top surface of the top glue layer and the top surface of the interconnector structure.
Furuya teaches a semiconductor device (fig. 1) including a top surface of a top dielectric layer (¶ 0029: 114, similar to 315 of Huang) substantially coplanar with a top surface of an insulating layer (¶ 0030: 128, similar to top glue 219 of Huang) and a top surface of an interconnector structure (¶ 0030: 134, similar to 207 of Huang).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device elements of Huang with the planarity of Furuya, as a means to minimize the resistance of the interconnect and prevent the wiring capacity from decreasing (Furuya, ¶ 0054).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Furuya as applied to claim 1, and further in view of Yu et al. (PG Pub. No. US 2008/0171431 A1).
Regarding claim 2, Huang in view of Furuya teaches the semiconductor device of claim 1, comprising a bottom dielectric layer (Huang, 201).
Huang in view of Furuya does not teach wherein the bottom dielectric layer is porous.
Yu teaches a semiconductor device (fig. 4) including a bottom dielectric layer (¶¶ 0041: 110’, similar to 201, 109 and/or 211 of Huang), wherein the bottom dielectric layer is porous (¶ 0043: 110’ comprises porous material).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the bottom dielectric layer of Huang in view of Furuya with porous material, as a means to optimize dielectric constant (Yu, ¶ 0010) and corresponding properties such as inter-metal layer capacitance (Yu, ¶ 0008).
Regarding claim 3, Huang in view of Furuya and Yu teaches the semiconductor device of claim 2, comprising a porosity of the top dielectric layer (Huang, ¶ 0079: porosity of 315 less than porosity of 219) and a porosity of the bottom dielectric layer (Yu, ¶ 0043: 110’ comprises porous dielectric material).
Huang in view of Furuya and Yu as applied to claim 2 above does not teach wherein a porosity of the top dielectric layer is greater than a porosity of the bottom dielectric layer.
However, Yu does teach top and bottom porous dielectric layers (¶ 0041: 120’ and 110’), wherein a porosity of the top dielectric layer is greater than a porosity of the bottom dielectric layer (¶¶ 0013, 0053: 120’ has porosity of about 25% to about 35%, 110’ has porosity from about 20% to about 25%).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the porosity of the upper dielectric layer of Huang in view of Furuya and Yu to be greater than that of the bottom dielectric layer, as a means to adjust etch selectivity (Yu, ¶ 0045), improving physical and chemical strength in the dielectric layers, providing more controllable etching rate and layer adhesion, and/or reduced inter-metal layer capacitance (Yu, ¶ 0008).
Regarding claim 4, Huang in view of Furuya and Yu teaches the semiconductor device of claim 3, wherein the porosity of the bottom dielectric layer is greater than a porosity of the top glue layer (Yu, ¶¶ 0041, 0043 & Huang, ¶ 0078: 110’ of Yu fully cured with <10% porogen remaining, glue layer 219 of Huang has porosity of 25% to 50%),
wherein the top glue layer has a vertical portion in contact with a side surface of the interconnector structure (Huang, fig. 6: 219 has vertical portion in contact with side surface of 207) and horizontal portion in contact with a top surface of the bottom dielectric layer (Huang, fig. 6: 219 has horizontal portion in contact with top surface of 211), wherein the top surface of the top glue layer at the vertical portion is coplanar with the top surface of the top dielectric layer (Furuya, fig. 1: top surface of 128, corresponding to 219 of Huang, is coplanar with the top surface of 114, corresponding to 315 of Huang).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Furuya and Yu as applied to claim 1, and further in view of Lii et al. (PG Pub. No. US 2012/0100717 A1).
Regarding claim 5, Huang in view of Furuya and Yu teaches the semiconductor device of claim 4, further comprising a top glue layer (Huang, 219), a bottom dielectric layer (Huang, 201 and/or Yu, 110’) and a substrate (Huang, 100 and/or Yu, 100).
Huang in view of Furuya and Yu does not teach the semiconductor device further comprising a bottom glue layer positioned between the substrate and the bottom dielectric layer, wherein the bottom glue layer and the top glue layer comprise the same material, wherein a thickness of the top glue layer is greater than a thickness of the bottom glue layer.
Lii teaches a semiconductor device (fig. 1L: 1000) including a bottom glue layer (¶ 0010: 1004, including adhesive dielectric material such as silicon carbide dioxide) positioned between a substrate and a bottom dielectric layer (fig. 1L & ¶ 0010: 1004 positioned between substrate 1002 and dielectric layer 1008), wherein the bottom glue layer and a top glue layer (¶ 0010: layer 1010, comprising adhesive dielectric material such as silicon dioxide) comprise the same material (¶ 0010: both 1004 and 1010 comprise silicon).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Huang in view of Furuya and Yu with a bottom glue layer, as a means to protect the substrate when forming a via hole (1014 of Lii, 20 of Yu and/or 629 of Huang).
Lii further teaches the bottom glue layer is suitable for providing an etch stop function (Lii, ¶ 0010), and the top glue layer provides a polish stop function (Lii, ¶ 0021: excess 1030/1032 removed by CMP).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the glue layer thicknesses of Huang in view of Furuya, Yu and Lii, as a means to provide respective thicknesses suitable to provide an etch stop and a polish stop.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, the general conditions of top and bottom glue layer thickness is disclosed by Lii, such that meeting the limitation “wherein a thickness of the top glue layer is greater than a thickness of the bottom glue layer” is a matter of routine skill.
Allowable Subject Matter
Claims 6-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: . The prior art fails to teach or clearly suggest the limitations stating:
“wherein the interconnector structure is positioned on the top surface of the bottom
interconnector layer, wherein the top surface of the bottom interconnector layer is partially covered by the bottom glue layer” as recited in claim 6.
Claims 7-10 depend on claim 6 and would be allowable for the same reasons.
Response to Arguments
Applicant’s arguments with respect to the 35 USC § 102 and 35 USC § 103 rejections of claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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