DETAILED ACTION
This Office action responds to the application filed on 08/31/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species 1a-1d, reading on figures 1, 2, & 5-8, in the reply filed on 01/20/2026 is acknowledged. The traversal is on the grounds that Species 2 shares the same inventive concept as Species 1a-1d in that “a connector assembly is integrated with a stiffener attached to a package substrate and electrically coupled to functional circuitry of an integrated circuit die, with the alleged distinction relating only to whether a communicating integrated circuit die is located within or outside the chip package assembly. Such a difference reflects a system-level implementation choice and does not render the connector-stiffener integration patentably distinct, nor does it require a separate field of search, as the same structural features and functional relationships govern both embodiments.” This is found persuasive because both Species 1a-1d & Species 2 share the same device features.
Thus, the restriction filed on 12/18/2025 is withdrawn. Claims 1-20 will be examined in this Office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 3, 4, 14, 15, 16, 17, & 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dungan (US 20240361547).
Regarding Claim 1, Dungan (see, e.g., figs. 1a-b, fig, 2) shows a chip package assembly comprising:
a package substrate 101 (see, e.g., para.0028) coupled with an integrated circuit die 141, 142, 143, & 144 (see, e.g., para.0027);
a stiffener 130a-b (see, e.g., para.0031) attached to a top surface of the package substrate outward of the integrated circuit die;
and a connector assembly (elements 110, 111, 120, & 121, see, e.g., para.0030-0032) integrated with the stiffener and communicatively coupled with functional circuitry of the integrated circuit die through a circuitry of the package substrate (data path 260, see, e.g., fig. 2, para.0036).
Regarding Claim 2, Dungan (see, e.g., fig. 1b) shows the chip package assembly according to claim 1,
wherein both the connector assembly and the stiffener 130a-b are disposed at a peripheral area of the top surface.
Regarding Claim 3, Dungan (see, e.g., fig. 1b) shows the chip package assembly according to claim 2,
wherein the connector assembly and the stiffener 130a-b are configured to substantially enclose the integrated circuit die 141, 142, 143, & 144 (see, e.g., fig. 1b).
Regarding Claim 4, Dungan (see, e.g., fig. 1a, para.0030-0032) shows the chip package assembly according to claim 3,
wherein the connector assembly is configured to connect to an optical cable 111, 112, & 122 (see, e.g., para.0030-0032).
Regarding Claim 14, Dungan (see, e.g., figs. 1a-b, fig. 2) shows an electronic device comprising: a chip package assembly comprising:
a package substrate 101 (see, e.g., para.0028) coupled with an integrated circuit die 141, 142, 143, & 144 (see, e.g., para.0027);
a stiffener 130a-b (see, e.g., para.0031) attached to a top surface of the package substrate outward of the integrated circuit die;
and a connector assembly (elements 110, 111, 120, & 121, see, e.g., para.0030-0032) integrated with the stiffener and communicatively coupled with functional circuitry of the integrated circuit die through a circuitry of the package substrate (data path 260, see, e.g., fig. 2, para.0036);
a remote integrated circuit die 123 (see, e.g., para.0032) disposed outside of the chip package assembly;
and a cable 122 connecting the remote integrated circuit die with the connector assembly of the chip package assembly.
Regarding Claim 15, Dungan (see, e.g., fig. 1a) shows the electronic device of claim 14,
wherein the cable is an optical cable 122 (see, e.g., para.0030-0032).
Regarding Claim 16, Dungan (see, e.g., para.0026) shows the electronic device of claim 14,
wherein the remote integrated circuit die and the chip package assembly are coupled to a common printed circuit board 360.
Dungan (see, e.g., para.0026) states the package substrate 101 and extension substrates 110 & 120 can be, but are not limited to, printed circuit boards. In this interpretation, the printed circuit boards are present. Thus, Dungan anticipates Claim 16.
Regarding Claim 17, Dungan (see, e.g., para.0026) shows the electronic device of claim 14,
wherein the chip package assembly and the remote integrated circuit die are not coupled to a common printed circuit board.
Although Dungan (see, e.g., para.0026) states the package substrate 101 and extension substrates 110 & 120 can be printed circuit boards, said elements are not limited to being PCBs and thus, can be treated just as substrates. The chip package assembly and the remote integrated circuit die are not limited to being coupled to a printed circuit board. Thus, Dungan anticipates Claim 17.
Regarding Claim 18, Dungan (see, e.g., figs. 1a-b) shows the electronic device of claim 14,
wherein the connector assembly is secured to or by the stiffener (see, e.g., para.0030-0032).
Claims 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 19, & 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lim (US 20250054819).
Regarding Claim 1, Lim (see, e.g., fig. 5b) shows a chip package assembly comprising:
a package substrate 501 (see, e.g., para.0127) coupled with an integrated circuit die 551 (see, e.g., para.0134);
a stiffener 500 (see, e.g., para.0128) attached to a top surface of the package substrate outward of the integrated circuit die;
and a connector assembly (see, e.g., fig. 5b, para.0131) integrated with the stiffener and communicatively coupled with functional circuitry of the integrated circuit die through a circuitry of the package substrate.
Regarding Claim 2, Lim (see, e.g., figs. 5a-b) shows the chip package assembly according to claim 1,
wherein both the connector assembly 530 & 540 and the stiffener 500 are disposed at a peripheral area of the top surface.
Regarding Claim 3, Lim (see, e.g., figs. 5a-b) shows the chip package assembly according to claim 2,
wherein the connector assembly 530 & 540 and the stiffener 500 are configured to substantially enclose the integrated circuit die 551.
Regarding Claim 5, Lim (see, e.g., fig. 5b, annotated figure 5b) shows the chip package assembly according to claim 1,
wherein the connector assembly comprises:
a bracket 530 and a connector 540, the bracket is formed by a cavity of the stiffener (cavity of 510 pertaining to stiffener 500, see, e.g., para.0127).
Regarding Claim 6, Lim (see, e.g., fig. 5b, para.0131) shows the chip package assembly according to claim 5,
wherein the cavity (cavity of 510) is configured to retain the connector 540.
Regarding Claim 7, Lim (see, e.g., fig. 5b) shows the chip package assembly according to claim 1,
wherein the connector assembly comprises:
a bracket 530 (see, e.g., para.0131) and a connector 540 (see, e.g., para.0131), the bracket is attached to the top surface of the package substrate (see, e.g., fig. 5b).
Regarding Claim 8, Lim (see, e.g., fig. 5b, para.0131) shows the chip package assembly according to claim 7,
wherein the bracket 530 and the stiffener 500 are coupled to each other directly.
Regarding Claim 9, Lim (see, e.g., annotated figure 5b) shows the chip package assembly according to claim 8,
wherein the bracket 530 comprises a first part of a retaining mechanism (see, e.g., annotated figure 5b),
the stiffener comprises a second part of the retaining mechanism (520 portion of 500, see, e.g., annotated figure 5b, para.0128),
and the first part and the second part engage with each other (see, e.g., fig. 5b).
Regarding Claim 10, Lim (see, e.g., fig. 5b, para.0129) shows the chip package assembly according to claim 8,
wherein the stiffener comprises cantilever extensions 520b (see, e.g., para.0129) configured to engage with the bracket.
Regarding Claim 11, Lim (see, e.g., figs. 2a-2c) shows the chip package assembly according to claim 7,
wherein the connector 540 (alternate of 240, see, e.g., para.0076) comprises retainers (230a & 240a, see, e.g., para.0076) that secure the connector to the stiffener 500.
Regarding the limitations, “alternate of 240, 230a,& 240a,”Lim (see, e.g., para.0126) states the chip package assembly 500 can include all the features of the chip package assembly 200 reading on figs. 2a-c.
Regarding Claim 12, Lim (see, e.g., fig. 5b) shows the chip package assembly according to claim 1,
wherein the connector assembly further comprises:
a bracket 510 and a connector 540, the bracket coupled to the stiffener 500 by a frame 530,
wherein the frame comprises a cutout (cavity region of 530 in which 540 is disposed, see, e.g., figs. 5a-b) configured to allow the connector to go through,
and the frame is attached to atop surface of the stiffener.
Regarding Claim 19, Lim (see, e.g., fig. 5b) shows a method of assembling a chip package assembly, the method comprising:
mounting one or more integrated circuit dies 780 (see, e.g., para.0148) to a substrate 701 (see, e.g., para.0147) (see, e.g., fig. 7b);
and mounting a stiffener 710 (see, e.g., para.0147) to the substrate outward of the one or more integrated circuit dies (see, e.g., fig. 7b);
and securing a connector assembly 720 (see, e.g., para.0131) to the chip package assembly via the stiffener (see, e.g., figs. 7e-f), the connector assembly electrically coupled to functional circuitry of the one or more integrated circuit dies via the substrate.
Regarding Claim 20, Lim (see, e.g., fig. 7e) shows the method of claim 19,
wherein securing the connector assembly 720 further comprises:
interlocking the stiffener 710 with the connector assembly (connection of 710 & 720, see, e.g., fig. 7e, para.0151).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lim (US 20250054819) in view of Wright (US 20140170866).
Regarding Claim 13, Lim shows the chip package assembly according to claim 1,
Lim, however, fails to show
further comprising a lid disposed on a planar member, the planar member being configured to pivot around a hinge to open and close the lid,
a connector of the connector assembly disposed on the planar member.
Wright (see, e.g., figs. 2-5, para.0038, para.0041), in a similar device to Lim, teaches a configuration wherein a hinge structure 480 comprising a lid on a planar member 450 and a connector of a connector assembly 215 & 220 on the planar member of the hinge structure would simplify connector assembly connections and operation, and would lower assembly costs.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Wright in the connector assembly of Lim to simplify connector assembly connections and operation, and to lower assembly costs.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814