DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/24/2026 have been fully considered but they are moot in view of the new grounds of rejection necessitated by Applicant’s claim amendments as addressed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,5-6,8,21 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2006/0220152 A1 to Huang et al., “Huang”, in view of U.S. Patent Application Publication Number 2015/0236115 A1 to Chan et al., “Chan”, and U.S. Patent Application Publication Number 2021/0125929 A1 to Shin et al., “Shin”.
Regarding claim 1, Huang discloses a semiconductor device (e.g. Figure 2), comprising:
a first dielectric layer (221, ¶ [0036]) deposited on a sidewall of an active device (gate 10); and
a second dielectric layer (222, ¶ [0036]) covering the first dielectric layer, wherein a dielectric constant of the first dielectric layer is between 2 and 2.5 (Figure 15 includes values between 2 and 2.5 as pictured, ¶ [0042]), and wherein both the first dielectric layer (221) is a non-silicon-based material (e.g. aromatic polymer, a parylene, a fluorine-doped amorphous carbon, Teflon, porogen (¶ [0036]).
Huang fails to clearly teach wherein the dielectric constant of the second dielectric layer (222) is less than or equal to 4 and wherein the second dielectric layer (222) is a non-silicon based material.
Chan teaches (e.g. FIG. 2F) wherein a second dielectric layer (214) is a boron nitride spacer (Abstract, ¶ [0002],[0006],[0007],[0019],[0030]) which is non-silicon based.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang with the second dielectric layer made of boron nitride as taught by Chan in order to achieve various desirable properties (Chan Abstract, ¶ [0019]) such as reduced dielectric constant (Chan FIG. 10, ¶ [0055],[0056]) which one having ordinary skill in the art would recognize to be desirable to reduce spacing since low-k materials reduce cross-talk and parasitic capacitances, and/or reduced leakage current (Chan FIG. 9 ¶ [0054]).
Although Chan teaches wherein the boron nitride spacer has a dielectric constant of between 3 and 4.5 (¶ [0049]) and is preferably crystalline (hexagon, Abstract, ¶ [0048]), Chan fails to clearly state wherein the boron nitride has a dielectric constant less than or equal to 4.
Shin teaches (FIG. 9A) wherein crystalline boron nitride (h-BN) has a dielectric constant of less than 4 over the frequency range of 10k and higher (¶ [0116]) or nanocrystalline boron nitride having a dielectric constant of 2.3-2.5 at 100 kHz (¶ [0098]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan with the dielectric constant of the hexagonal crystal structure boron spacer having a dielectric constant of less than 4 as taught by Shin since the dielectric constant of less than 4 appears to be an inherent characteristic of crystalline boron nitride, or generally within the claimed range as taught by Shin in order to achieve a low dielectric constant together with high mechanical strength (Shin ¶ [0119]-[0121],[0135]) and/or low dielectric constant together with a higher breakdown voltage than other materials (FIG. 11, 12, ¶ [0122],[0123],[0126],[0131],[0132]).
Regarding claim 5, Huang in view of Chan and Shin yields the semiconductor device according to claim 1, and Huang further teaches (e.g. Figure 2) wherein the active device comprises a gate structure (¶ [0034],[0037],[0038]) and a spacer layer (221,222,224) arranged along sidewalls of the gate structure, the spacer layer comprises the first dielectric layer (221) and the second dielectric layer (222).
Regarding claim 6, Huang in view of Chan and Shin yields the semiconductor device according to claim 1, and Huang further teaches (e.g. Figure 2) wherein the active element includes a substrate (13, ¶ 0034]) and a source region (one of 17), a drain region (other 17), and a channel region (14) formed on the substrate, and the channel region (14) is located between the source region and the drain region (between source/drains 17).
Regarding claim 8, Huang in view of Chan and Shin yields the semiconductor device according to claim 1, and Huang further teaches (e.g. Figure 2) wherein the active device comprises a source region (one of 17, ¶ [0034]), a drain region (other 17), a channel region (14), a gate structure (10) and a gate spacer (221-224), and the channel region (14) is located between the source region and the drain region (regions 17), the gate structure (10) is formed on the channel region (14), and the gate spacer (221-224) is arranged around sidewalls of the gate structure (10).
Regarding claim 21, Huang in view of Chan and Shin yields the semiconductor device according to claim 1, and applying the teachings of Chan and Shin to Huang yields wherein the second dielectric layer (Huang layer 222) comprises crystalline boron nitride (Chan Abstract, ¶ [0048]) (Shin FIG. 9A (h-BN)).
Claims 13,17,22 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2006/0220152 A1 to Huang et al., “Huang”, in view of U.S. Patent Application Publication Number 2015/0236115 A1 to Chan et al., “Chan”, and U.S. Patent Application Publication Number 2021/0125929 A1 to Shin et al., “Shin”, further in view of U.S. Patent Application Publication Number 2021/0376072 A1 to Yu et al., “Yu”.
Regarding claim 13, Huang discloses a semiconductor device (e.g. Figure 2), comprising:
a first dielectric layer (221, ¶ [0036]) deposited on a sidewall of an active device (gate 10); and
a second dielectric layer (222, ¶ [0036]) covering the first dielectric layer, wherein a dielectric constant of the first dielectric layer is between 2 and 2.5 (Figure 15 includes values between 2 and 2.5 as pictured, ¶ [0042]), and wherein both the first dielectric layer (221) is a non-silicon-based material (e.g. aromatic polymer, a parylene, a fluorine-doped amorphous carbon, Teflon, porogen (¶ [0036]).
Huang fails to clearly teach wherein the dielectric constant of the second dielectric layer (222) is less than or equal to 4 and wherein the second dielectric layer (222) is a non-silicon based material.
Chan teaches (e.g. FIG. 2F) wherein a second dielectric layer (214) is a boron nitride spacer (Abstract, ¶ [0002],[0006],[0007],[0019],[0030]) which is non-silicon based.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang with the second dielectric layer made of boron nitride as taught by Chan in order to achieve various desirable properties (Chan Abstract, ¶ [0019]) such as reduced dielectric constant (Chan FIG. 10, ¶ [0055],[0056]) which one having ordinary skill in the art would recognize to be desirable to reduce spacing since low-k materials reduce cross-talk and parasitic capacitances, and/or reduced leakage current (Chan FIG. 9 ¶ [0054]).
Although Chan teaches wherein the boron nitride spacer has a dielectric constant of between 3 and 4.5 (¶ [0049]) and is preferably crystalline (hexagon, Abstract, ¶ [0048]), Chan fails to clearly state wherein the boron nitride has a dielectric constant less than or equal to 4.
Shin teaches (FIG. 9A) wherein crystalline boron nitride (h-BN) has a dielectric constant of less than 4 over the frequency range of 10k and higher (¶ [0116]) or nanocrystalline boron nitride having a dielectric constant of 2.3-2.5 at 100 kHz (¶ [0098]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan with the dielectric constant of the hexagonal crystal structure boron spacer having a dielectric constant of less than 4 as taught by Shin since the dielectric constant of less than 4 appears to be an inherent characteristic of crystalline boron nitride, or generally within the claimed range as taught by Shin in order to achieve a low dielectric constant together with high mechanical strength (Shin ¶ [0119]-[0121],[0135]) and/or low dielectric constant together with a higher breakdown voltage than other materials (FIG. 11, 12, ¶ [0122],[0123],[0126],[0131],[0132]).
Huang fails to clearly teach wherein the dielectric layers are formed in the trench of a gate structure.
Yu teaches (e.g. FIG. 32A) forming a low-k dielectric layer (284A, ¶ [0052]-[0054]) in the trench of a gate structure (264, ¶ [0045]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan and Shin as applied to a low-k dielectric of the isolation structure of a cut-on-poly-oxide-definition-edge (CPODE) as taught by Yu (¶ [0053],[0060]) in order to benefit from the isolation structure having a low dielectric constant together with high mechanical strength (Shin ¶ [0119]-[0121],[0135]) and/or low dielectric constant together with a higher breakdown voltage than other materials (FIG. 11, 12, ¶ [0122],[0123],[0126],[0131],[0132]).
Regarding claim 17, Huang in view of Chan and Shin and Yu yields the isolation structure according to claim 13, and Yu further teaches wherein the first dielectric layer and the second dielectric layer (when applying teachings of Huang and Chan and Shin) serve as a filler for a cut-on-poly-oxide-definition- edge (CPODE) of the gate structure (Yu ¶ [0053],[0060]).
Regarding claim 22, Huang in view of Chan and Shin and Yu yields the isolation structure according to claim 13, and applying the teachings of Chan and Shin to Huang yields wherein the second dielectric layer (Huang layer 222) comprises crystalline boron nitride (Chan Abstract, ¶ [0048]) (Shin FIG. 9A (h-BN)).
Claims 7,10-12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2006/0220152 A1 to Huang et al., “Huang”, in view of U.S. Patent Application Publication Number 2015/0236115 A1 to Chan et al., “Chan”, and U.S. Patent Application Publication Number 2021/0125929 A1 to Shin et al., “Shin”, as applied to claim 6 above, and further in view of U.S. Patent Application Publication Number 2021/0376072 A1 to Yu et al., “Yu”.
Regarding claim 7, although Huang in view of Chan and Shin yields the semiconductor device according to claim 6, Huang fails to clearly teach wherein the channel region (14) includes a plurality of semiconductor layers and a plurality of spacer layers, the semiconductor layers are stacked and arranged at intervals, and the spacer layers are respectively formed on opposite sidewalls of the semiconductor layers, wherein each of the spacer layers comprises the first dielectric layer and the second dielectric layer.
Yu teaches wherein a channel region includes a plurality of semiconductor layers (channels 206, ¶ [0020]) and a plurality of spacer layers (212a,212b ¶ [0027],[0028]), the semiconductor layers (206) are stacked and arranged at intervals, and the spacer layers (specifically 212b) are respectively formed on opposite sidewalls of the semiconductor layers (206).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan and Shin as applied to a channel having multiple semiconductor layers (e.g. a gate-all-around (GAA) or nanostructure transistor, Yu ¶ [0015]) in order to benefit from better gate control, lowered leakage current, and improved scaling capability for various IC applications (Yu ¶ [0015]) and since the low-k dielectric spacers reduce parasitic capacitances leading to improved performance such as higher speed (Cheng ¶ [0004]-[0006]).
Regarding claim 10, Huang in view of Chan and Shin yields the semiconductor device according to claim 1, and Huang further teaches wherein the active device comprises a gate structure (10), the gate structure comprises a gate electrode layer (¶ [0038]).
Huang fails to clearly teach a plurality of semiconductor layers and a plurality of gate dielectric layers, and the semiconductor layers deposited in the gate electrode layer, and the semiconductor layers are stacked and arranged at intervals, the gate dielectric layers surround the semiconductor layers respectively and are electrically isolated from the gate electrode layer and the semiconductor layers, wherein the gate structure comprises a trench exposing opposite sidewalls and a bottom surface of the gate electrode layer.
Yu teaches a plurality of semiconductor layers (channels 206, ¶ [0020]) and a plurality of gate dielectric layers (262, ¶ [0045]), and the semiconductor layers (206) are deposited in the gate dielectric layer (262), and the semiconductor layers (206) are stacked and arranged at intervals (as pictured), the gate dielectric layers (262) surround the semiconductor layers (206) respectively and are electrically isolated by the gate electrode layer (264, ¶ [0045]) and the semiconductor layers (206), wherein the gate structure comprises a trench (e.g. FIG. 25A,25C trench 280, ¶ [0051]) exposing opposite sidewalls and a bottom of the gate electrode layer (264, 280 is filled with CPODE, ¶ [0052],[0053]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan and Shin as applied to a channel having multiple semiconductor layers (e.g. a gate-all-around (GAA) or nanostructure transistor, Yu ¶ [0015]) including a Continuous Poly on Diffusion Edge (CPODE) structure (Yu ¶ [0024]) in order to benefit from better gate control, lowered leakage current, and improved scaling capability for various IC applications (Yu ¶ [0015]) and since the low-k dielectric spacers reduce parasitic capacitances leading to improved performance such as higher speed (Cheng ¶ [0004]-[0006]).
Regarding claim 11, Huang in view of Chan and Shin and Yu yields the semiconductor device according to claim 10, and Yu further teaches (e.g. FIG. 13A-13C) wherein the semiconductor device comprises a liner (240, ¶ [0039]), the liner (240) is arranged on the opposite sidewalls of the gate electrode layer (209 becomes gate electrode layer) and covers the bottom surface, the liner comprises the first dielectric layer and the second dielectric layer (when generally applying the teachings of Huang in view of Chan and Shin).
Regarding claim 12, Huang in view of Chan and Shin and Yu yields the semiconductor device according to claim 11, and Yu further teaches wherein the liner is located in an isolation structure of a cut-on-poly-oxide-definition-edge (CPODE) (¶ [0024],[0025],[0052],[0060]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2006/0220152 A1 to Huang et al., “Huang”, in view of U.S. Patent Application Publication Number 2015/0236115 A1 to Chan et al., “Chan”, and U.S. Patent Application Publication Number 2021/0125929 A1 to Shin et al., “Shin”, as applied to claim 8 above, and further in view of U.S. Patent Application Publication Number 2015/0228788 A1 to Chen et al., “Chen”.
Regarding claim 9, although Huang in view of Chan and Shin yields the semiconductor device according to claim 8, Huang fails to clearly teach wherein the semiconductor device comprises a contact etch stop layer deposited on the sidewalls of the gate spacer and along the upper surface of the source region and the upper surface of the drain region, and the contact etch stop layer comprises the first dielectric layer (118a) and the second dielectric layer (118b).
Chen teaches a contact etch stop layer (layers 250 and 260) deposited on sidewalls of a gate spacer (130 and 140) and along the upper surface of a source region (142’) the upper surface of a drain region (other 142’), and the contact etch stop layer comprises a first dielectric layer (low-k 250, ¶ [0031],[0032]) and a second dielectric layer (260, ¶ [0034]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan and Shin with the low-k dielectric as a contact etch stop layer (CESL) as taught by Chen in order to achieve a low dielectric constant together with high mechanical strength (Shin ¶ [0119]-[0121],[0135]) and/or low dielectric constant together with a higher breakdown voltage than other materials (FIG. 11, 12, ¶ [0122],[0123],[0126],[0131],[0132]) and since a low-k CESL improves device performance (Chen ¶ [0004],[0006],[0009],[0022]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2006/0220152 A1 to Huang et al., “Huang”, in view of U.S. Patent Application Publication Number 2015/0236115 A1 to Chan et al., “Chan”, and U.S. Patent Application Publication Number 2021/0125929 A1 to Shin et al., “Shin”, further in view of U.S. Patent Application Publication Number 2015/0228788 A1 to Chen et al., “Chen”.
Regarding claim 1, Huang discloses a semiconductor device (e.g. Figure 2), comprising:
a first dielectric layer (221, ¶ [0036]) deposited on a sidewall of an active device (gate 10); and
a second dielectric layer (222, ¶ [0036]) covering the first dielectric layer, wherein a dielectric constant of the first dielectric layer is between 2 and 2.5 (Figure 15 includes values between 2 and 2.5 as pictured, ¶ [0042]), and wherein both the first dielectric layer (221) is a non-silicon-based material (e.g. aromatic polymer, a parylene, a fluorine-doped amorphous carbon, Teflon, porogen (¶ [0036]).
Huang fails to clearly teach wherein the dielectric constant of the second dielectric layer (222) is less than or equal to 4 and wherein the second dielectric layer (222) is a non-silicon based material.
Chan teaches (e.g. FIG. 2F) wherein a second dielectric layer (214) is a boron nitride spacer (Abstract, ¶ [0002],[0006],[0007],[0019],[0030]) which is non-silicon based.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang with the second dielectric layer made of boron nitride as taught by Chan in order to achieve various desirable properties (Chan Abstract, ¶ [0019]) such as reduced dielectric constant (Chan FIG. 10, ¶ [0055],[0056]) which one having ordinary skill in the art would recognize to be desirable to reduce spacing since low-k materials reduce cross-talk and parasitic capacitances, and/or reduced leakage current (Chan FIG. 9 ¶ [0054]).
Although Chan teaches wherein the boron nitride spacer has a dielectric constant of between 3 and 4.5 (¶ [0049]) and is preferably crystalline (hexagon, Abstract, ¶ [0048]), Chan fails to clearly state wherein the boron nitride has a dielectric constant less than or equal to 4.
Shin teaches (FIG. 9A) wherein crystalline boron nitride (h-BN) has a dielectric constant of less than 4 over the frequency range of 10k and higher (¶ [0116]) or nanocrystalline boron nitride having a dielectric constant of 2.3-2.5 at 100 kHz (¶ [0098]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan with the dielectric constant of the hexagonal crystal structure boron spacer having a dielectric constant of less than 4 as taught by Shin since the dielectric constant of less than 4 appears to be an inherent characteristic of crystalline boron nitride, or generally within the claimed range as taught by Shin in order to achieve a low dielectric constant together with high mechanical strength (Shin ¶ [0119]-[0121],[0135]) and/or low dielectric constant together with a higher breakdown voltage than other materials (FIG. 11, 12, ¶ [0122],[0123],[0126],[0131],[0132]).
Huang fails to clearly teach wherein the layer is a contact etch stop layer.
Chen teaches (e.g. FIG. 6) a contact etch stop layer (layers 250 and 260) deposited on sidewalls of a gate spacer (130 and 140) and along the upper surface of a source region (one of 142’) the upper surface of a drain region (other 142’), and the contact etch stop layer comprises a first dielectric layer (low-k 250, ¶ [0031],[0032]) and a second dielectric layer (260, ¶ [0034]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan and Shin with the low-k dielectric as a contact etch stop layer (CESL) as taught by Chen in order to achieve a low dielectric constant together with high mechanical strength (Shin ¶ [0119]-[0121],[0135]) and/or low dielectric constant together with a higher breakdown voltage than other materials (FIG. 11, 12, ¶ [0122],[0123],[0126],[0131],[0132]) and since a low-k CESL improves device performance (Chen ¶ [0004],[0006],[0009],[0022]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2006/0220152 A1 to Huang et al., “Huang”, in view of U.S. Patent Application Publication Number 2015/0236115 A1 to Chan et al., “Chan”, and U.S. Patent Application Publication Number 2021/0125929 A1 to Shin et al., “Shin”, and U.S. Patent Application Publication Number 2021/0376072 A1 to Yu et al., “Yu”, as applied to claim 8 above, and further in view of U.S. Patent Application Publication Number 2022/0013364 A1 to Chang et al., “Chang”.
Regarding claim 16, although Huang in view of Chan and Shin and Yu yields the isolation structure according to claim 13, HuangHuang fails to clearly teach together wherein the gate structure comprises a gate electrode layer, the trench exposes opposite sidewalls and a bottom surface of the gate electrode layer, and the first dielectric layer and the second dielectric layer serve as a liner for a cut metal gate (CMG).
Chang teaches (e.g. Figure 13B) wherein a gate structure comprises a gate structure comprises a gate electrode layer (74a, 74b, ¶ [0063]), and trench (94) exposing opposite sidewalls and a bottom surface (edges of bottom surface) of the gate electrode player, and a first dielectric layer (100, ¶ [0069],[0070]) and a low-k second dielectric layer (102, ¶ [0071]) serve as a liner for a cut metal gate (CMG) (¶ [0011],[0012],[0068],[0077],[0078]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have applied the isolation structure of Huang in view of Chan and Shin and Yu to a cut metal gate (CMG) as exemplified by Chang in order to achieve a low dielectric constant together with high mechanical strength (Shin ¶ [0119]-[0121],[0135]) and/or low dielectric constant together with a higher breakdown voltage than other materials (FIG. 11, 12, ¶ [0122], [0123], [0126], [0131], [0132]) and since a low-k CESL improves device performance (Chen ¶ [0004],[0006],[0009],[0022]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2006/0220152 A1 to Huang et al., “Huang”, in view of U.S. Patent Application Publication Number 2015/0236115 A1 to Chan et al., “Chan”, and U.S. Patent Application Publication Number 2021/0125929 A1 to Shin et al., “Shin”, and U.S. Patent Application Publication Number 2015/0228788 A1 to Chen et al., “Chen”, further in view of U.S. Patent Application Publication Number 2002/0000556 A1 to Sakamoto et al., “Sakamoto”.
Regarding claim 19, although Huang in view of Chan and Shin and Chen yields the contact etch stop layer according to claim 18, Huang fails to clearly teach wherein the contact etch stop layer acts as an interface layer between a front-end-of-line feature or a middle-end- of-line feature and a back-end-of-line feature.
Sakamoto teaches (FIG. 6) wherein a contact etch stop layer (boron nitride layer 107 or 111, ¶ [0001],[0004]-[0006],[0058],[0059]) acts as an interface between a front-end-of-line feature (e.g. transistor 101) and a middle or back-end-of-line feature (exposed upper surface of 100).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Huang in view of Chan and Shin and Chen with the boron nitride based low-k dielectric used as an interface between FEOL and MEOL/BEOL as taught by Sakamoto in order to achieve a low dielectric constant together with high mechanical strength (Shin ¶ [0119]-[0121],[0135]) and/or low dielectric constant together with a higher breakdown voltage than other materials (FIG. 11, 12, ¶ [0122],[0123],[0126],[0131],[0132]) and since a low-k CESL improves device performance (Chen ¶ [0004],[0006],[0009],[0022]), and since boron nitride provides good mechanical strength, heat diffusion efficiency, and moisture-absorption and permeation characteristics (Sakamoto ¶ [0006],[0007]).
Allowable Subject Matter
Claims 3-4,15,20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art generally teaches low-k spacers e.g. U.S. Patent Application Publication Number 2002/0179982 A1 to Cheng et al. teaches a semiconductor device (e.g. FIG. 1D), comprising:
a first dielectric layer (114, ¶ [0018],[0019]) deposited on a sidewall of an active device (gate 108); and
a second dielectric layer (116, ¶ [0018],[0019]) covering the first dielectric layer,
wherein a dielectric constant of the first dielectric layer (114) is less than 3 (¶ [0018]), and
a dielectric constant of the second dielectric layer is less than or equal to 4 (SiO2 inherently has a dielectric constant of about 3.9), as discussed previously.
Prior art generally teaches forming gate sidewall spacers from boron nitride, e.g. U.S. Patent Application Publication Number 2015/0236115 A1 to Chan et al. (Abstract).
Prior art generally teaches depositing amorphous boron nitride, e.g. U.S. Patent Application Publication Number 2018/0144930 A1 to Glavin et al. using pulsed laser deposition (Abstract) including amorphous boron nitride with a dielectric constant of 2.5 or less, and U.S. Patent Application Publication Number 2021/0123161 A1 to Lee et al. teaches boron nitride having a dielectric constant of about 2.5 or less (Abstract, FIG. 2C, FIG. 9A).
However, prior art fails to reasonably teach or suggest wherein the first dielectric layer comprises amorphous boron nitride, and the second dielectric layer comprises crystalline boron nitride, as claimed in claim 3 together with all of the other limitations of claim 1 as claimed. Claim 4 is objected to as allowable insofar as it depends upon and includes all of the limitations of claims 3 and 1.
Claims 15 and 20 are objected to for similar reasons to claim 3 together with all of the limitations of claims 13 and 18 respectively.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
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