DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2, 6, 7 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by LEE et al. (2020/0194721).
With regard to claim 2, LEE et al. disclose a display device (for example, see figs. 1 – 3) comprising:
a substrate (101) in which a transmission area, a display area surrounding at least a portion of the transmission area (an area HA, fig. 2 functioning as the transmission area), a non-display area (an area BA, fig. 2 functioning as a non-display area) between the transmission area (HA, fig. 2) and the display area (an area EA, fig. 2 functioning as the display area), and a peripheral area (NA, fig. 1) outside the display area (the display EA area forming in the area AA as shown in fig. 1) are defined;
a plurality of pixels (SP, fig. 1) arranged on the display area (the display EA area forming in the area AA as shown in fig. 1) in pixel rows and pixel columns (as shown in fig. 1);
a plurality of gate lines (scanning lines SL, fig. 3 functioning as gate lines) respectively extending along the pixel rows (the rows, as shown in fig. 1, having rows of the scanning lines SL as shown in fig. 3); and
a first gate connection line (referred to as “SL3” by examiner’s annotation shown in fig. 3 below) on the non-display area (BA),
wherein each of mth and (m+1)th gate lines (for example, first and second gate lines SL functioning as mth and (m+1)th gate lines) of the plurality of gate lines (SL) includes a first
portion (referred to as “SL1” by examiner’s annotation shown in fig. 3 below) and a second portion (referred to as “SL2” by examiner’s annotation shown in fig. 3 below) which are physically apart from each other by the transmission area (HA),
the first portion (SL1) and the second portion (SL2) of each of the mth and (m+1)th gate lines are electrically connected to each other through the first gate connection line (referred to as “SL3” by examiner’s annotation shown in fig. 3 below), and m is a natural number.
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With regard to claim 6, LEE et al. disclose a second gate connection line (referred to as “SL4” by examiner’s annotation shown in fig. 3 below) on the non-display area (BA), wherein each of nth and (n+1)th gate lines (for example, third and fourth gate lines SL) of the plurality of gate lines (SL) includes a first portion (referred to as “SL11” by examiner’s annotation shown in fig. 3 below) and a second portion (referred to as “SL22” by examiner’s annotation shown in fig. 3 below) which are physically apart from each other by the transmission area (HA), and the first portion (SL11) and the second portion (SL22) of each of the nth and (n+1)th gate lines are
electrically connected to each other through a second gate connection line (SL4), and
n is a natural number greater than m+1.
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With regard to claim 7, LEE et al. disclose a through hole (120) is defined through the
substrate (110) to correspond to the transmission area (HA).
Claim(s) 8, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon (9293082).
With regard to claim 8, Jeon discloses a display device (for example, see fig. 9) comprising:
a substrate (there is inherently a substrate in order to form the display device, fig. 9 thereon) in which a display area (510) and a peripheral area (referred to as “PA” by examiner’s annotation shown in fig. 9 below) outside the display area (510) are defined;
a plurality of pixels (515) arranged on the display area (510) in pixel rows and pixel columns (the pixels 515 can be formed in a matrix form and inherently in pixel rows and pixel columns; for example, see column 16, lines 62, 63);
a plurality of initialization gate lines (LGI, RGI) respectively extending along the pixel rows; and
a plurality of gate driving circuits (540, 550) disposed on the peripheral area (PA) and arranged in a direction of the pixel columns (for example, columns in a Y-direction),
wherein a kth gate driving circuit (for example, a gate driving circuit 540 functioning as a kth gate driving circuit) among the plurality of gate driving circuits (540, 550) simultaneously drives (the first and second gate drivers 540, 550 that simultaneously apply, serves as simultaneously drive, the left and right gate initialization signals LGI, RGI. Thus, the first gate drivers 540 simultaneously drives initialization gate lines LGI on the left side; for example, column 5, lines 57 – 59; column 18, lines 6 - 17) m th and (m+1)th initialization gate lines (for example, initialization gate lines LGI including m th and (m+1)th initialization gate lines) as among the plurality of initialization gate lines (LGI, RGI), and
k and m are natural numbers.
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With regard to claim 20, Jeon discloses the m+1 is same as 2k (for example, m = 1; and k = 1; wherein the first initialization gate line wherein m = 1; and the first gate driving circuit and k = 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (2020/0194721) in view of You (8009133).
With regard to claim 21, Jeon discloses a display device (for example, see fig. 9) comprising:
a substrate (there is inherently a substrate in order to form the display device, fig. 9 thereon) in which a display area (510) and a peripheral area (referred to as “PA” by examiner’s annotation shown in fig. 9 below) outside the display area (510) are defined;
a plurality of pixels (515) arranged on the display area (510) in pixel rows and pixel columns (the pixels 515 can be formed in a matrix form and inherently in pixel rows and pixel columns; for example, see column 16, lines 62, 63);
a plurality of gate driving circuits (540, 550) disposed on the peripheral area (PA) and arranged in a direction of the pixel columns (for example, columns in a Y-direction),
wherein a kth gate driving circuit (for example, a gate driving circuit 540 functioning as a kth gate driving circuit) among the plurality of gate driving circuits (540, 550) simultaneously drives (the first and second gate drivers 540, 550 that simultaneously apply, serves as simultaneously drive, the left and right gate initialization signals LGI, RGI. Thus, the first gate drivers 540 simultaneously drives initialization gate lines LGI on the left side; for example, column 5, lines 57 – 59; column 18, lines 6 - 17) m th and (m+1)th initialization gate lines (for example, initialization gate lines LGI including m th and (m+1)th initialization gate lines) as among the plurality of gate lines (LGI, RGI), and
k and m are natural numbers.
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Jeon does not clearly disclose a plurality of compensation gate lines respectively extending along the pixel rows wherein a kth gate driving circuit drives among the plurality of compensation gate lines.
However, You discloses a plurality of compensation gate lines (compensation gate lines CLN comprising a plurality of compensation gate lines; wherein N is a number of compensation gate lines) respectively extending along the pixel rows (display panel 140 inherently including the pixel rows) wherein a kth gate driving circuit (gate driving part 170 functioning as a kth gate driving circuit) drives among the plurality of compensation gate lines (CLN).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jeon’s device to a plurality of compensation gate lines respectively extending along the pixel rows wherein a kth gate driving circuit drives among the plurality of compensation gate lines as taught by You in order to enhance a high light brightness of the image on the display panel, as is known to one of ordinary skill in the art.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 8 – 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5, 6, 12, 15, 17 - 21 of U.S. Patent No. 11778877. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 2 of current Application is corresponding to claim 1 of U.S. Patent No. 11778877.
Claim 8 of current Application is corresponding to claim 1 of U.S. Patent No. 11778877.
Claim 9 of current Application is corresponding to claim 1 of U.S. Patent No. 11778877.
Claim 10 of current Application is corresponding to claim 2 of U.S. Patent No. 11778877.
Claim 11 of current Application is corresponding to claim 5 of U.S. Patent No. 11778877.
Claim 12 of current Application is corresponding to claim 6 of U.S. Patent No. 11778877.
Claim 13 of current Application is corresponding to claim 12 of U.S. Patent No. 11778877.
Claim 14 of current Application is corresponding to claim 15 of U.S. Patent No. 11778877.
Claim 15 of current Application is corresponding to claim 17 of U.S. Patent No. 11778877.
Claim 16 of current Application is corresponding to claim 18 of U.S. Patent No. 11778877.
Claim 17 of current Application is corresponding to claim 19 of U.S. Patent No. 11778877.
Claim 18 of current Application is corresponding to claim 20 of U.S. Patent No. 11778877.
Claim 19 of current Application is corresponding to claim 21 of U.S. Patent No. 11778877.
Claim 20 of current Application is corresponding to claim 1 of U.S. Patent No. 11778877. (It is inherently m + 1 is same 2k, in case m = 1 and K = 1).
Claim 21 of current Application is corresponding to claim 1 of U.S. Patent No. 11778877.
Allowable Subject Matter
8. Claims 3 -5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3 -5 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as each of n-th and (n+1)-th gate lines of the plurality of gate lines includes a first portion and a second portion which are physically apart from each other by the transmission area, the first portions of the m-th, (m+1)-th, n-th, and (n+1)-th gate lines are connected to each other in the peripheral area as recited in claim 3.
Claims 9 -19 would be allowable if rewritten or the filing of a terminal disclaimer to overcome the nonstatutory double patenting rejection, set forth in this Office action such as a plurality of compensation gate lines arranged in each of the pixel rows and including n-th and (n+1)-th compensation gate lines, wherein the k-th gate driving circuit simultaneously drives the m-th and (m+1)-th initialization gate lines and the n-th and (n+1)-th compensation gate lines as recited in claim 9.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812