Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant's arguments filed 5/4/26 have been fully considered but they are not persuasive.
Information Disclosure Statement
The information disclosure statements filed 1/30/26; 6/18/26 have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5-14, 16-20 is/are stand rejected under 35 U.S.C. 103 as being unpatentable over Falk et al. (U.S. Patent Publication No. 2020/0118822) in view of Batinica et al. (U.S. Patent Publication No. 2017/0178891), as previously applied.
Referring to figures 1-7, Falk et al. teaches a method of forming a three-dimensional memory device, comprising:
forming a distortion correction layer (112) of the distortion correction structure on the backside surface of the substrate, wherein the distortion correction layer comprises a first material that has a compressive or tensile stress as-deposited on the backside surface and has a thickness (see figure 1); and
performing an ion implant process to implant ions uniformly across a backside surface of the first material deposited on the backside surface of the substrate, wherein the thickness and compressive or tensile stress formed in the as- deposited first material is unable to compensate for all of the out-of-plane- distortion formed in the substrate, the implanted ions include a uniform dose of an implanted ion that was provided at a first ion energy, and the combination of the as-deposited first material and the addition of the implanted ions within the first material is configure to correct the out-of- plane-distortion formed in the substrate (see paragraphs# 25+).
However, the reference does not clearly teach measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate.
Batinica et al. teaches teach measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate (see figures 1a-1d, paragraphs# 19-20, meeting claims 5, 10).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate in Falk et al. as taught by Batinica et al. because the process is known in the art to induce stress on the substrate.
Regarding to claim 6, the thickness of the as-deposited first material and parameters of the ion implant process used to implant the implanted ions are selected so that the implanted ions are not implanted into the backside surface of the substrate (see paragraph# 25, figures 1a-1f).
Regarding to claim 8, the plurality of semiconductor device layers are configured to form at least a portion of a 3D memory device (see paragraph# 48).
Regarding to claim 9, the at least one distortion correction parameter comprises at least one of the thicknesses of the as-deposited first material, ion energy, dose amount, and ion species required during the ion implant process (see paragraphs# 21-55).
Regarding to claim 10, the determining the at least one distortion correction parameter is performed by a system controller after receiving information relating to the measurement of the out-of-plane-distortion formed in the substrate (see paragraphs# 44-48).
Regarding to claim 11, the system controller is further configured to control the thickness of the as-deposited first material, ion energy, dose amount, and ion species during the ion implant process after determining the at least one distortion correction parameter (see paragraphs# 21-55).
Regarding to claim 12, a method of forming a distortion correction structure, comprising:
depositing a distortion correction layer (112) on a backside surface of a substrate (106) comprising a plurality of semiconductor device layers (104) on a front-side of the substrate, wherein at least one of the plurality of semiconductor device layers has a compressive or tensile stress that causes an out-of-plane-distortion in the substrate (see paragraph# 24-34); and
performing an ion implant process to expose the as-deposited distortion correction layer to a uniform dose of implanted ions (see paragraphs# 25-27).
Regarding to claim 13, the distortion correction layer comprises a silicon nitride (Si3N4) containing layer (see paragraph# 23).
Regarding to claim 14, the distortion correction layer has thickness of between 1,000 A and 2,000 A (see paragraph# 24).
Regarding to claim 16, the ion implant process comprises implanting argon (Ar) ions at a constant energy of between 65 keV and 70 keV into the as-deposited distortion correction layer and a dose of between 1 x 1012 and 1 x 1016 atoms/cm2(see paragraphs# 27, 34)
However, the reference does not clearly teach the prior to the depositing of the distortion correction layer, measuring the out-of-plane-distortion in the substrate; and determining at least one distortion correction parameter that is used to form the distortion correction layer (in claim 17), the at least one distortion correction parameter comprises at least one of thickness of the distortion correction layer, ion energy, dose amount, and ion species required during the ion implant process (in claim 18), subsequent to the ion implant process, measuring an out-of-plane-distortion found in the substrate; and determining at least one distortion correction parameter that is used to form an additional distortion correction layer (in claim 19).
Batinica et al. teaches the prior to the depositing of the distortion correction layer, measuring the out-of-plane-distortion in the substrate; and determining at least one distortion correction parameter that is used to form the distortion correction layer, the at least one distortion correction parameter comprises at least one of thickness of the distortion correction layer, ion energy, dose amount, and ion species required during the ion implant process, subsequent to the ion implant process, measuring an out-of-plane-distortion found in the substrate; and determining at least one distortion correction parameter that is used to form an additional distortion correction layer (see figures 1a-1d, paragraphs# 19-20, meeting claims 17-19).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate in Falk et al. as taught by Batinica et al. because the process is knonwn in the art to induce stress on the substrate.
Regarding to claim 20, depositing the additional distortion correction layer on the backside surface of the substrate; and performing an ion implant process to expose the as-deposited additional distortion correction layer to a uniform dose of implanted ions (see figures 1-2, paragraphs# 21-55).
Claim 15 is/are stand rejected under 35 U.S.C. 103 as being unpatentable over Falk et al. (U.S. Patent Publication No. 2020/0118822) in view of Batinica et al. (U.S. Patent Publication No. 2017/0178891) as applied to claims 5-14, 16-20 above, further in view of Kamm (U.S. Patent Publication No. 2004/0041102), as previously applied.
Referring to figures 1-7, Falk et al. teaches a method of forming a three-dimensional memory device, comprising:
forming a distortion correction layer (112) of the distortion correction structure on the backside surface of the substrate, wherein the distortion correction layer comprises a first material that has a compressive or tensile stress as-deposited on the backside surface and has a thickness (see figure 1); and
performing an ion implant process to implant ions uniformly across a backside surface of the first material deposited on the backside surface of the substrate, wherein the thickness and compressive or tensile stress formed in the as- deposited first material is unable to compensate for all of the out-of-plane- distortion formed in the substrate, the implanted ions include a uniform dose of an implanted ion that was provided at a first ion energy, and the combination of the as-deposited first material and the addition of the implanted ions within the first material is configure to correct the out-of- plane-distortion formed in the substrate (see paragraphs# 25+).
However, the reference does not clearly teach the implanted ion comprises argon (Ar), phosphorous (P), silicon (Si), or carbon (C).
Kamm teaches implanted ion comprises argon (Ar), phosphorous (P), silicon (Si), or carbon (C) to the back surface of the substrate (see figure 2, paragraph# 19, 21).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was made would implant ion comprises argon (Ar), phosphorous (P), silicon (Si), or carbon (C) to the back surface of the substrate in Falk et al. as taught by Kamm because the process is known in the art to compensate for local features in the stress distribution on the substrate.
Response to Arguments
Applicant's arguments filed 5/4/26 have been fully considered but they are not persuasive.
The claim rejections under 35 USC 102 in view of Subrahmanyan is withdrawn.
Applicant contends that none of the prior art teaches/suggests measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate. This is not found persuasive because Falk et al. teaches the convex curvature of the substrate to compensate for the stress (see paragraph# 21). While Batinica teaches measuring the curvature (warp) in the substrate to reduce the warp (see paragraph# 10).
Applicant further contends that none of the prior are teaches/suggests Batinica generally describes measuring wafer distortion to inform stress-inducing processes, but does not show or suggest combining such measurement-based parameter determination with Falk's backside distortion-correction layer and implantation process in the manner claimed. This is not found persuasive because examiner relies on Batinica to teach measuring wafer distortion to inform stress-inducing processes (see paragraph# 19-21, figures 1a-1d), while Falk et al. teaches deposition, ion implantation and adjust the thickness of the layer to form a stress layer (see paragraphs# 23-24) and provide the specific energy of ions to implant within the stress layer to induce stress (see paragraph# 27, figure 1a-1f). Falk et al. and Batinica are in the same field of endeavor. Therefore, it is would have known in the semiconductor art to induce the stress on the substrate.
Applicant contends that the rejection relies on hindsight reconstruction of applicant’s invention. In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
