Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Group II, claims 5-20 drawn to a method claims is acknowledged. The traversal is on the ground(s) that the subject matter of all claims 1-19 is sufficiently related that a thorough search for the subject matter of any one group of the claims would encompass a search for the subject matter of the remaining claims. This is not found persuasive because claims 1-4 would require further search and for the reason of the last Office Action. The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statements filed 9/11/25; 2/3/24 have been considered.
Oath/Declaration
Oath/Declaration filed on 9/6/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 5-13, 15, 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Subrahmanyan (U.S. Patent Publication No. 2023/0367941).
The applied reference has a common assignee/applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Referring to figures 5-7, Subrahmanyan teaches a method of forming a three-dimensional memory device, comprising:
measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate (see figure 7);
forming a distortion correction layer(PVD SiN) of the distortion correction structure on the backside surface of the substrate, wherein the distortion correction layer comprises a first material that has a compressive or tensile stress as-deposited on the backside surface and has a thickness (see figure 5c); and
performing an ion implant process to implant ions uniformly across a backside surface of the first material deposited on the backside surface of the substrate, wherein the thickness and compressive or tensile stress formed in the as- deposited first material is unable to compensate for all of the out-of-plane- distortion formed in the substrate, the implanted ions include a uniform dose of an implanted ion that was provided at a first ion energy, and the combination of the as-deposited first material and the addition of the implanted ions within the first material is configure to correct the out-of- plane-distortion formed in the substrate (see figure 5c, paragraph# 35+).
Regarding to claim 6, the thickness of the as-deposited first material and parameters of the ion implant process used to implant the implanted ions are selected so that the implanted ions are not implanted into the backside surface of the substrate.
Regarding to claim 7, wherein implanted ion comprises argon (Ar), phosphorous (P), silicon (Si), or carbon (C) (see figure 5c, paragraph# 35+).
Regarding to claim 8, the plurality of semiconductor device layers are configured to form at least a portion of a 3D memory device (see paragraph# 3).
Regarding to claim 9, the at least one distortion correction parameter comprises at least one of the thickness of the as-deposited first material, ion energy, dose amount, and ion species required during the ion implant process (see figure 5c, paragraph# 35+).
Regarding to claim 10, the determining the at least one distortion correction parameter is performed by a system controller after receiving information relating to the measurement of the out-of-plane-distortion formed in the substrate (see figures 5-7, see paragraph# 36-37).
Regarding to claim 11, the system controller is further configured to control the thickness of the as-deposited first material, ion energy, dose amount, and ion species during the ion implant process after determining the at least one distortion correction parameter (see figures 2-7, see paragraph# 36-37).
Regarding to claim 12, a method of forming a distortion correction structure, comprising:
depositing a distortion correction layer (PVD SiN) on a backside surface of a substrate (Silicon) comprising a plurality of semiconductor device layers on a front-side of the substrate, wherein at least one of the plurality of semiconductor device layers has a compressive or tensile stress that causes an out-of-plane-distortion in the substrate (see figures 5C, see paragraph# 18); and
performing an ion implant process to expose the as-deposited distortion correction layer to a uniform dose of implanted ions (see paragraph# 37+).
Regarding to claim 13, the distortion correction layer comprises a silicon nitride (Si3N4) containing layer (see figures 2, 5).
Regarding to claim 15, the implanted ions comprise phosphorous, boron, argon, nitrogen, krypton, indium, or boron fluorine (see paragraph# 37+).
Regarding to claim 17, prior to the depositing of the distortion correction layer, measuring the out-of-plane-distortion in the substrate; and determining at least one distortion correction parameter that is used to form the distortion correction layer (see paragraphs# 37+, figures 2-9).
Regarding to claim 18, the at least one distortion correction parameter comprises at least one of thickness of the distortion correction layer, ion energy, dose amount, and ion species required during the ion implant process (see paragraph# 37+).
Regarding to claim 19, subsequent to the ion implant process, measuring an out-of-plane-distortion found in the substrate; and determining at least one distortion correction parameter that is used to form an additional distortion correction layer (see paragraph# 37+, figures 2-9).
Regarding to claim 20, depositing the additional distortion correction layer on the backside surface of the substrate; and performing an ion implant process to expose the as-deposited additional distortion correction layer to a uniform dose of implanted ions (see paragraph# 37+, figures 2-9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subrahmanyan (U.S. Patent Publication No. 2023/0367941) as applied to claims 5-13, 15, 17-20 above in view of Falk et al. (U.S. Patent Publication No. 2020/0118822).
Referring to figures 5-7, Subrahmanyan teaches a method of forming a three-dimensional memory device, comprising:
measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate (see figure 7);
forming a distortion correction layer (PVD SiN) of the distortion correction structure on the backside surface of the substrate, wherein the distortion correction layer comprises a first material that has a compressive or tensile stress as-deposited on the backside surface and has a thickness (see figure 5c); and
performing an ion implant process to implant ions uniformly across a backside surface of the first material deposited on the backside surface of the substrate, wherein the thickness and compressive or tensile stress formed in the as- deposited first material is unable to compensate for all of the out-of-plane- distortion formed in the substrate, the implanted ions include a uniform dose of an implanted ion that was provided at a first ion energy, and the combination of the as-deposited first material and the addition of the implanted ions within the first material is configure to correct the out-of- plane-distortion formed in the substrate (see figure 5c, paragraph# 35+).
However, the reference does not clearly teach the distortion correction layer has thickness of between 1,000 A and 2,000 A (in claim 14), the ion implant process comprises implanting argon (Ar) ions at a constant energy of between 65 keV and 70 keV into the as-deposited distortion correction layer and a dose of between 1 x 1012 and 1 x 1016 atoms/cm2(in claim 16).
In re claims 14 and 16, the selection of the thickness of distortion correction layer, the energy and dose of ion implantation is obvious because it is a matter of determining optimum process condition by routine experimentation with a limited number of species. In re Jones, 162 USPQ 224 (CCPA 1955) (the selection of optimum ranges within prior art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980) (discovery of optimum value of result effective variable in a known process is obvious). In such a situation, applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to prior art range. See M.P.E.P 2144.05 III. In particular, Falk et al. suggest that the thickness of distortion correction layer, the energy and dose of ion implantation can be optimized (paragraphs# 21-55).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed to optimize that the thickness of distortion correction layer, the energy and dose of ion implantation in Subrahmanyan as taught by Falk et al. because discovering the optimum or workable ranges involves only routine skill in the art to form a desired semiconductor device.
Claim 5-14, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Falk et al. (U.S. Patent Publication No. 2020/0118822) in view of Batinica et al. (U.S. Patent Publication No. 2017/0178891).
Referring to figures 1-7, Falk et al. teaches a method of forming a three-dimensional memory device, comprising:
forming a distortion correction layer (112) of the distortion correction structure on the backside surface of the substrate, wherein the distortion correction layer comprises a first material that has a compressive or tensile stress as-deposited on the backside surface and has a thickness (see figure 1); and
performing an ion implant process to implant ions uniformly across a backside surface of the first material deposited on the backside surface of the substrate, wherein the thickness and compressive or tensile stress formed in the as- deposited first material is unable to compensate for all of the out-of-plane- distortion formed in the substrate, the implanted ions include a uniform dose of an implanted ion that was provided at a first ion energy, and the combination of the as-deposited first material and the addition of the implanted ions within the first material is configure to correct the out-of- plane-distortion formed in the substrate (see paragraphs# 25+).
However, the reference does not clearly teach measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate.
Batinica et al. teaches teach measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate (see figures 1a-1d, paragraphs# 19+, meeting claims 5, 10).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate in Falk et al. as taught by Batinica et al. because the process is knonwn in the art to induce stress on the substrate.
Regarding to claim 6, the thickness of the as-deposited first material and parameters of the ion implant process used to implant the implanted ions are selected so that the implanted ions are not implanted into the backside surface of the substrate (see paragraph# 25, figures 1a-1f).
Regarding to claim 8, the plurality of semiconductor device layers are configured to form at least a portion of a 3D memory device (see paragraph# 48).
Regarding to claim 9, the at least one distortion correction parameter comprises at least one of the thickness of the as-deposited first material, ion energy, dose amount, and ion species required during the ion implant process (see paragraphs# 21-55).
Regarding to claim 10, the determining the at least one distortion correction parameter is performed by a system controller after receiving information relating to the measurement of the out-of-plane-distortion formed in the substrate (see paragraphs# 44-48).
Regarding to claim 11, the system controller is further configured to control the thickness of the as-deposited first material, ion energy, dose amount, and ion species during the ion implant process after determining the at least one distortion correction parameter (see paragraphs# 21-55).
Regarding to claim 12, a method of forming a distortion correction structure, comprising:
depositing a distortion correction layer (112) on a backside surface of a substrate (106) comprising a plurality of semiconductor device layers (104) on a front-side of the substrate, wherein at least one of the plurality of semiconductor device layers has a compressive or tensile stress that causes an out-of-plane-distortion in the substrate (see paragraph# 24+); and
performing an ion implant process to expose the as-deposited distortion correction layer to a uniform dose of implanted ions (see paragraphs# 25+).
Regarding to claim 13, the distortion correction layer comprises a silicon nitride (Si3N4) containing layer (see paragraph# 23).
Regarding to claim 14, the distortion correction layer has thickness of between 1,000 A and 2,000 A (see paragraph# 24).
Regarding to claim 16, the ion implant process comprises implanting argon (Ar) ions at a constant energy of between 65 keV and 70 keV into the as-deposited distortion correction layer and a dose of between 1 x 1012 and 1 x 1016 atoms/cm2(see paragraphs# 27, 34)
However, the reference does not clearly teach the prior to the depositing of the distortion correction layer, measuring the out-of-plane-distortion in the substrate; and determining at least one distortion correction parameter that is used to form the distortion correction layer (in claim 17), the at least one distortion correction parameter comprises at least one of thickness of the distortion correction layer, ion energy, dose amount, and ion species required during the ion implant process (in claim 18), subsequent to the ion implant process, measuring an out-of-plane-distortion found in the substrate; and determining at least one distortion correction parameter that is used to form an additional distortion correction layer (in claim 19).
Batinica et al. teaches the prior to the depositing of the distortion correction layer, measuring the out-of-plane-distortion in the substrate; and determining at least one distortion correction parameter that is used to form the distortion correction layer, the at least one distortion correction parameter comprises at least one of thickness of the distortion correction layer, ion energy, dose amount, and ion species required during the ion implant process, subsequent to the ion implant process, measuring an out-of-plane-distortion found in the substrate; and determining at least one distortion correction parameter that is used to form an additional distortion correction layer (see figures 1a-1d, paragraphs# 19+, meeting claims 17-19).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would measuring an out-of-plane-distortion formed in a substrate that comprises a plurality of semiconductor device layers formed on a front-side surface of the substrate; determining at least one distortion correction parameter that is used to form a distortion correction structure that is formed on a backside surface of the substrate in Falk et al. as taught by Batinica et al. because the process is knonwn in the art to induce stress on the substrate.
Regarding to claim 20, depositing the additional distortion correction layer on the backside surface of the substrate; and performing an ion implant process to expose the as-deposited additional distortion correction layer to a uniform dose of implanted ions (see figures 1-2, paragraphs# 21-55).
Claim 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Falk et al. (U.S. Patent Publication No. 2020/0118822) in view of Batinica et al. (U.S. Patent Publication No. 2017/0178891) as applied to claims 5-14, 16-20 above, further in view of Kamm (U.S. Patent Publication No. 2004/0041102).
Referring to figures 1-7, Falk et al. teaches a method of forming a three-dimensional memory device, comprising:
forming a distortion correction layer (112) of the distortion correction structure on the backside surface of the substrate, wherein the distortion correction layer comprises a first material that has a compressive or tensile stress as-deposited on the backside surface and has a thickness (see figure 1); and
performing an ion implant process to implant ions uniformly across a backside surface of the first material deposited on the backside surface of the substrate, wherein the thickness and compressive or tensile stress formed in the as- deposited first material is unable to compensate for all of the out-of-plane- distortion formed in the substrate, the implanted ions include a uniform dose of an implanted ion that was provided at a first ion energy, and the combination of the as-deposited first material and the addition of the implanted ions within the first material is configure to correct the out-of- plane-distortion formed in the substrate (see paragraphs# 25+).
However, the reference does not clearly teach the implanted ion comprises argon (Ar), phosphorous (P), silicon (Si), or carbon (C).
Kamm teaches implanted ion comprises argon (Ar), phosphorous (P), silicon (Si), or carbon (C) to the back surface of the substrate (see figure 2, paragraph# 19, 21).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was made would implant ion comprises argon (Ar), phosphorous (P), silicon (Si), or carbon (C) to the back surface of the substrate in Falk et al. as taught by Kamm because the process is known in the art to compensate for local features in the stress distribution on the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893