Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I, claims 1-16 in the reply filed on December 22nd, 2025 is acknowledged. Non-elected invention of Group II, claims 17-27 have been withdrawn from consideration. Claims 1-27 are pending.
Action on merits of Group I, claims 1-16 as follows.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 06th, 2023 has been considered by the examiner.
Drawings
The drawings filed on 09/06/2023 are objected.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features: “second gate insulating layer and the first interlayer insulating layer are located between the first metal layer and the second semiconductor layer”, as recited in dependent claims 7 and 16, and the features: “a first connection electrode connecting the first semiconductor layer of the first silicon-based transistor to the second semiconductor layer of the first oxide-based transistor” as recited in base claim 11, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Ou (US 2020/0312931, hereinafter as Ou ‘931) in view of Tanaka (US 2020/0098933, hereinafter as Tana ‘933).
Regarding Claim 1, Ou ‘931 teaches a display apparatus comprising:
a substrate (Fig. 1, (201); [0071]);
a buffer layer (Fig. 1, (203); [0076]) on the substrate;
a first semiconductor layer (Fig. 1, (204); [0076]) on the buffer layer;
a first gate insulating layer (Fig. 1, (205); [0076]) on the first semiconductor layer;
a first metal layer (Fig. 1, (206); [0076]) on the first gate insulating layer;
a second gate insulating layer (Fig. 1, (207); [0076]) on the first metal layer;
a second metal layer (Fig. 1, (208); [0076]) on the second gate insulating layer;
a first interlayer insulating layer (Fig. 1, (209); [0076]) on the second metal layer.
Thus, Ou ‘931 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a first dopant doped in at least one of the second gate insulating layer or the first interlayer insulating layer”.
Tana ‘933 teaches a first dopant doped in at least one of the gate insulating layer (a fluorine-containing silicon nitride (106); [0094]) or the first interlayer insulating layer (a fluorine-containing silicon nitride (114); [0094]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ou ‘931 by having a first dopant doped in at least one of the second gate insulating layer or the first interlayer insulating layer for the purpose of reducing an adverse influence of hydrogen by which the oxide semiconductor layer to be conductive or suppress the generation of oxygen deficiency caused to increase the carrier concentration in the oxide semiconductor layer (see para. [0094) as suggested by Tana ‘933.
Product by process limitation:
The expression “a first dopant doped” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
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Fig. 1 (Ou ‘931)
Regarding Claim 2, Tana ‘933 teaches the first dopant comprises fluorine (see para. [0094]).
Regarding Claim 3, Tana ‘933 teaches each of the gate insulating layer (106) and the first interlayer insulating layer (114) comprises silicon nitride (see para. [0094]).
Claims 4-5 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ou ‘931 and Tana ‘933 as applied to claim 1 above, and further in view of Yuji (JP 2020/126200, hereinafter as Yuji ‘200).
Regarding Claim 4, Ou ‘931 and Tana ‘933 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a second semiconductor layer and a third metal layer on the first interlayer insulating layer; a second interlayer insulating layer on the second semiconductor layer and the third metal layer; and a fourth metal layer on the second interlayer insulating layer”.
Yuji ‘200 teaches a second semiconductor layer (Fig. 4, (OSC); [0019]) and a third metal layer (101; [0021]) on the first interlayer insulating layer (IL1; [0024]); a second interlayer insulating layer (IL3; [0036]) on the second semiconductor layer (OSC) and the third metal layer (101); and a fourth metal layer (EL11/EL21; [0032]) on the second interlayer insulating layer (IL3).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ou ‘931 and Tana ‘933 by having a second semiconductor layer and a third metal layer on the first interlayer insulating layer; a second interlayer insulating layer on the second semiconductor layer and the third metal layer; and a fourth metal layer on the second interlayer insulating layer for the purpose of providing a display device that can reduce power consumption (see para. [0004) as suggested by Yuji ‘200.
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Fig. 4 (Yuji ‘200)
Regarding Claim 5, Yuji ‘200 teaches the fourth metal layer (EL11) is electrically connected to the first semiconductor layer (PSC; [0032]) through a first contact hole penetrating the first gate insulating layer (GI1), the second gate insulating layer (GI2), the first interlayer insulating layer (IL1), and the second interlayer insulating layer (IL3); the fourth metal layer (EL21) is electrically connected to the second semiconductor layer (OSC) through a second contact hole penetrating the second interlayer insulating layer (IL3); and a depth of the first contact hole is greater than a depth of the second contact hole (see Fig. 4).
Regarding Claim 9, Ou ‘931 teaches a fifth metal layer (210; [0076]) penetrating through the first interlayer insulating layer (209) (see Fig. 1).
Yuji ‘200 teaches a fifth metal layer (EL21) on the first gate insulating layer (PSC), wherein the fifth metal layer is electrically connected to the second metal layer (102; [0021]) through a fifth contact hole, wherein the fifth metal layer is electrically connected to the first semiconductor layer (PSC) through a sixth contact hole penetrating the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, and wherein a depth of the sixth contact hole is greater than a depth of the fifth contact hole (see Fig. 4).
Regarding Claim 10, Tana ‘933 teaches the second gate insulating layer (114; [0066]) comprises the first dopant (see para. [0094]), and is located between the first metal layer (110a/110b; [0097]) and the second metal layer (116; [0098]).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ou ‘931, Tana ‘933 and Yuji ‘200 as applied to claim 4 above, and further in view of Jin (US 2015/0318337, hereinafter as Jin ‘337).
Regarding Claim 6, Yuji ‘200 teaches the fourth metal layer (EL21) is electrically connected to the second semiconductor layer (OSC) through a fourth contact hole penetrating the second interlayer insulating layer (IL3); the fourth metal layer (EL12) is through a third contact hole penetrating the second gate insulating layer (GI2), the first interlayer insulating layer (IL1), and the second interlayer insulating layer (IL3).
Ou ‘931, Tana ‘933 and Yuji ‘200 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the fourth metal layer is electrically connected to the first metal layer; and a depth of the third contact hole is greater than a depth of the fourth contact hole”.
Jin ‘337 teaches the fourth metal layer (Fig. 4, (174); [0071]) is electrically connected to the first metal layer (125a; [0060]); and a depth of the third contact hole (62; [0084]) is greater than a depth of the fourth contact hole (61; [0070]) (see Fig. 4).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Ou ‘931, Tana ‘933 and Yuji ‘200 by having the fourth metal layer is electrically connected to the first metal layer; and a depth of the third contact hole is greater than a depth of the fourth contact hole for the purpose of providing a display device that can reduce power consumption (see para. [0004) as suggested by Jin ‘337.
Regarding Claim 7, Tana ‘933 teaches each of the gate insulating layer (106) and the first interlayer insulating layer (114) comprises the first dopant (a fluorine-containing silicon nitride; [0094]).
Yuji ‘200 teaches the second gate insulating layer (GI2) and the first interlayer insulating layer (IL1) are located between the fourth metal layer (EL11) and the second semiconductor layer (OSC).
Regarding Claim 8, Yuji ‘200 teaches a thickness of the first interlayer insulating layer (IL1) is greater than a thickness of the second gate insulating layer (GI2) (see Fig. 4).
Thus, Ou ‘931, Tana ‘933, Yuji ‘200 and Jin ‘337are shown to teach all the features of the claim with the exception of explicitly the limitations: “a first distance from a maximum concentration point of the first dopant to an upper surface of the first interlayer insulating layer in a thickness direction of the first interlayer insulating layer is greater than a second distance from a maximum concentration point of the first dopant to an upper surface of the second gate insulating layer in a thickness direction of the second gate insulating layer”.
However, it has been held to be within the general skill of a worker in the art to select a first distance from a maximum concentration point of the first dopant to an upper surface of the first interlayer insulating layer in a thickness direction of the first interlayer insulating layer is greater than a second distance from a maximum concentration point of the first dopant to an upper surface of the second gate insulating layer in a thickness direction of the second gate insulating layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select
a first distance from a maximum concentration point of the first dopant to an upper surface of the first interlayer insulating layer in a thickness direction of the first interlayer insulating layer is greater than a second distance from a maximum concentration point of the first dopant to an upper surface of the second gate insulating layer in a thickness direction of the second gate insulating layer in order to improve the performance of the display device.
Claims 11-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Suzumura (US 2021/0288078, hereinafter as Suzu ‘078) in view of Tanaka (US 2020/0098933, hereinafter as Tana ‘933).
Regarding Claim 11, Suzu ‘078 teaches a display apparatus comprising:
a substrate (Fig. 19, (100); [0038]);
a first silicon-based transistor on the substrate, and comprising a first semiconductor layer including a silicon-based semiconductor (Fig. 19, (103); [0042]), and a first gate electrode overlapping with the first semiconductor layer (Fig. 19, (105); [0044]); at least one insulating layer (Fig. 19, (107); [0046]) on the first gate electrode (105); a first oxide-based transistor on the at least one insulating layer, and comprising a second semiconductor layer (Fig. 19, (109); [0046) comprising an oxide-based semiconductor; and a first connection electrode (115; [0057]) connecting the first semiconductor layer (103) of the first silicon-based transistor to the second semiconductor layer (109) of the first oxide-based transistor (not shown), wherein the first connection electrode (115) is electrically connected to the first semiconductor layer through a first contact hole (113; [0050]), and the first connection electrode is electrically connected to the second semiconductor layer through a second contact hole (114; [0053]), the first contact hole having a depth different from a depth of the second contact hole (see Fig. 19), and wherein an insulating layer (107; [0046]) from among the at least one insulating layer is located between the first gate electrode (105) and the second semiconductor layer (109), and comprises an inorganic insulating material (SiNx; [0046]).
Thus, Suzu ‘078 is shown to teach all the features of the claim with the exception of explicitly the limitations: “an inorganic insulating material doped with a first dopant”.
Tana ‘933 teaches an inorganic insulating material doped with a first dopant (a fluorine-containing silicon nitride (114); [0094]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Suzu ‘078 by having an inorganic insulating material doped with a first dopant for the purpose of reducing an adverse influence of hydrogen by which the oxide semiconductor layer to be conductive or suppress the generation of oxygen deficiency caused to increase the carrier concentration in the oxide semiconductor layer (see para. [0094) as suggested by Tana ‘933.
Product by process limitation:
The expression “doped with a first dopant” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Regarding Claim 12, Tana ‘933 teaches the first dopant comprises fluorine (see para. [0094]).
Regarding Claim 13, Suzu ‘078 teaches a first gate insulating layer (104; [0044]) on the first semiconductor layer (103) of the first silicon-based transistor; a second gate insulating layer (117; [0074]) on the first gate electrode (105) of the first silicon-based transistor; and a first interlayer insulating layer (112; [0053]) on the second gate insulating layer (117), wherein the first contact hole (113) penetrates the first gate insulating layer (104), the second gate insulating layer (117), and the first interlayer insulating layer (112), and wherein the second contact hole (114) penetrates the first interlayer insulating layer (112).
Regarding Claim 16, Tana ‘933 teaches each of the second gate insulating layer and the first interlayer insulating layer comprises the first dopant (see para. [0094]),
Yuji ‘200 teaches the second gate insulating layer (GI2) and the first interlayer insulating layer (IL1) are located between the fourth metal layer (EL11) and the second semiconductor layer (OSC).
Allowable Subject Matter
Claims 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 14 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: “a first node connection electrode connecting the first gate electrode of the first silicon-based transistor to the second semiconductor layer of the first oxide-based transistor, wherein a depth of a third contact hole for electrically connecting the first node connection electrode to the first gate electrode is different from a depth of a fourth contact hole for electrically connecting the first node connection electrode to the second semiconductor layer”.
Claim 15 depends from claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Hanada et al. (2020/0350341 A1)
Lee et al. (US 2016/0181339 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893