DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention II, Claims 6 – 20 drawn to a process of making, in the reply filed on 27 March 2026 is acknowledged. The traversal is on the ground(s) that “no unreasonable search and examination burden exists because a search would likely yield a limited number of references for examination”. This is not found persuasive, as restriction for examination purposes is proper because there would be a serious search and examination burden if restriction were not required since each invention has attained recognition in the art as a separate subject for inventive effort and also would require a separate field of search based on the separate classification of each invention. Furthermore, where it is necessary to search for one of the inventions, such a search would not necessarily result in finding art pertinent to the other invention, as each invention would require a different field of search. Hence, there would be a serious search and examination burden if restriction were not required in the instant application.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 & 14 – 16 and their respective dependent claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 9,
Lin. 1 – 2 recites the limitation “a high pressure anneal process”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “an anneal process”.
Regarding Claim 9,
Lin. 1 – 2 recites the limitation “annealing of the substrate” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “annealing of the substrate in the hydrogen containing environment”.
Regarding Claim 14,
Lin. 2 recites the limitation “a spike anneal process”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as any reasonable annealing process of which the claimed “first anneal process” may be comprised.
Regarding Claim 15,
Lin. 3 recites the limitation “hydrogen or deuterium containing environment” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “a hydrogen or deuterium containing environment”.
Regarding Claim 16,
Lin. 2 recites the limitation “a spike anneal process”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as any reasonable annealing process of which the claimed “second anneal process” may be comprised.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (KR 20220014402 A) in view of SON (US 20180175050 A1).
Regarding Claim 6,
CHOI discloses:
A method of forming a three-dimensional memory device (Fig. 9A – 9F), comprising:
forming a channel structure (Fig. 9F: CH) within a plurality of openings (Fig. 9A: CHH) formed through a plurality of alternating (Fig. 9F: 120/130) layers formed over a surface of a substrate (Fig. 9F: 101), comprising:
forming a [gate dielectric] (Fig. 9B: 145; Pag. 4, Par. 4) layer over a surface of each of the plurality of openings (CHH); and
forming a polysilicon (Fig. 9B: 140; Pag. 4, Par. 2) layer over a surface of the [gate dielectric] (145) layer;
forming a fluorine containing (Fig. 9C: 160; Pag. 11, Par. 7) layer on the formed polysilicon (140) layer;
annealing the substrate (101), wherein annealing the substrate (101) causes fluorine atoms originally disposed in the fluorine containing layer (160) to diffuse into the polysilicon (140) layer (Pag. 11, Par. 8);
selectively removing the fluorine containing (160) layer (Pag. 11, Par. 9); and
forming a drain region (Fig. 9D: 175; Pag. 5, Par. 4) layer over the plurality of alternating (120/130) layers, wherein at least a portion of the formed channel structure (CH) is coupled to a portion of the drain region (175) layer (Pag. 5, Par. 4) and coupled to a portion of a source region (Fig. 9F: 102; Pag. 2, Par. 2) layer of the three-dimensional memory device (As seen in Fig. 9F).
CHOI does not disclose:
wherein the gate dielectric layer is an ONO layer stack
However, CHOI does disclose that the gate dielectric layer may comprise “a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from…140 . The tunneling layer…may include, for example, silicon oxide (SiO2)… The charge storage layer may be a charge trap layer…[and] the blocking layer may include silicon oxide (SiO2)” That is, CHOI discloses the gate dielectric layer may be an oxide-charge trap layer-oxide layer stack.
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention select a silicon nitride for the chare trap layer of CHOI, as CHOI discloses a charge trap layer but does not disclose a material for said layer. Therefore, a person having ordinary skill in the art would look to the prior art for a charge trap layer material recognized for its suitability and intended purpose (MPEP 2144.07). Further still, selecting a silicon nitride for the charge trap layer meets these criteria, as it is a known choice in the art for such devices, as evidenced by SON, Par. 48 – 51.
CHOI does not disclose:
annealing the substrate in a hydrogen containing environment, wherein annealing the substrate causes hydrogen atoms from the hydrogen containing environment to diffuse into the polysilicon layer;
SON discloses:
annealing the substrate (Fig. 9L – 9M: 101) in a hydrogen containing environment (Par. 104), wherein annealing the substrate causes hydrogen atoms from the hydrogen containing environment to diffuse into the polysilicon (Fig. 9L – 9M: 130b; Par. 103) layer;
(Inherently, annealing the substrate in a hydrogen containing environment causes hydrogen atoms from the hydrogen containing environment to diffuse into the polysilicon layer.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of CHOI with those of SON to enable annealing the substrate in a hydrogen containing environment, wherein annealing the substrate causes hydrogen atoms from the hydrogen containing environment to diffuse into the polysilicon layer in CHOI according to the teachings of SON for the further advantage of curing most of the crystal defects in the polysilicon layer (SON, Par. 104).
Regarding Claim 7,
CHOI discloses:
The method of claim 6,
wherein forming the channel structure (CH) further comprises forming a filler (Fig. 9D: 170; Pag. 12, Par. 1) layer over a surface of the polysilicon (140) layer after the fluorine containing (160) layer is selectively removed (Pag. 11, Par. 9).
Regarding Claim 8,
CHOI discloses:
The method of claim 7, wherein the plurality of alternating (120/130) layers comprise:
a word line (Fig. 9F: 130; Pag. 12, Par. 7) layer and an inter-word line dielectric (Fig. 9F: 120; Pag. 12, Par. 3) layer that are stacked in a first direction (Fig. 9F: Z) over the source region (102) layer that is disposed over the surface of the substrate (101); and
the plurality of openings (CHH) extend in the first (Z) direction from the source region (102) layer and through the plurality of alternating (120/130) layers (As seen in Fig. 9A/9F).
Regarding Claim 9,CHOI does not disclose:
The method of claim 8,
wherein the annealing of the substrate in the hydrogen containing environment comprises an anneal process.
SON discloses:
wherein the annealing of the substrate (101) in the hydrogen containing environment comprises an anneal process (Par. 104).
Regarding Claim 10,CHOI discloses:
The method of claim 7, wherein fluorine passivates grain boundaries and interface traps in the polysilicon layer (Pag. 4, Par. 1 – 2).
CHOI does not disclose:
wherein hydrogen passivates grain boundaries and interface traps in the polysilicon layer.
SON discloses:
wherein hydrogen passivates grain boundaries and interface traps in the polysilicon layer.
(Par. 103 – 104 teaches a “hydrogen annealing process” which “cures” most of the “crystal defects” in the polysilicon layer. Inherently and by design, the disclosed “hydrogen annealing process” of SON also passivates grain boundaries and interface traps in the polysilicon layer with hydrogen.)
Claims 11, 12, 14, & 17 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI in view of RABKIN (US 20160118396 A1).
Regarding Claim 11,
CHOI discloses:
A method of forming a channel structure of a three-dimensional memory device (Fig. 9A – 9F), comprising:
performing a mold [formation] process to form a plurality of alternating (Fig. 9A: 120/180) layers of dummy nitride (Fig. 9A: 180; Pag. 10, Par. 5) layers and inter-word line dielectric (Fig. 9A: 120; Pag. 10, Par. 5) layers over a surface of a substrate (Fig. 9A: 101);
performing a memory hole etch process (Pag. 11, Par. 1) to etch a plurality of memory holes (Fig. 9A: CHH) through the plurality of alternating (120/180) layers;
performing a memory hole channel layer deposition process (Fig. 9B – 9D) to form a channel structure (Fig. 9D: CH) within each of the plurality of memory holes (CHH), the memory hole channel layer deposition process (Fig. 9B – 9D) comprising:
depositing an [oxide-charge trap layer-oxide] layer stack (Fig. 9B: 145; Pag. 11, Par. 3) over the surface of each of the memory holes (CHH), the [oxide-charge trap layer-oxide] (145) layer stack comprising
a first oxide layer on inner surfaces of each of the plurality of memory holes, a charge trap layer on the first oxide layer, and a second oxide layer on the charge trap layer (Pag. 4, Par. 4); and
depositing a channel (Fig. 9B: 140; Pag. 11, Par. 4) layer on the second oxide layer;
performing a fluorine containing layer deposition process (Pag. 4, Par. 5) to form a fluorine (F) containing (Fig. 9C: 160; Pag. 11, Par. 7) layer over the channel (140) layer;
performing a first anneal process (Pag. 11, Par. 8) to diffuse mobile fluorine (F) atoms in the fluorine (F) containing (160) layer; and
performing a [removal] process to selectively remove the fluorine (F) containing (160) layer (Pag. 11, Par. 9).
CHOI does not disclose:
wherein the formation method of the mold formation process is deposition
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention select the formation method of the mold formation process to be deposition in CHOI, as CHOI discloses the formation of a mold (CHOI Fig. 9A) but does not disclose the method of formation. Therefore, a person having ordinary skill in the art would look to the prior art for method of formation recognized for its suitability and intended purpose (MPEP 2144.07). Further still, selecting deposition to be the method of formation of the mold meets these criteria, as deposition is a known choice in the art for the formation of the mold for such devices, as evidenced by RABKIN, Par. 14.
CHOI does not disclose:
wherein the charge trap layer comprises a nitride
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention select silicon nitride for the chare trap layer of CHOI, satisfying the requirements of this claim, as CHOI discloses a charge trap layer but does not disclose a material for said layer. Therefore, a person having ordinary skill in the art would look to the prior art for a charge trap layer material recognized for its suitability and intended purpose (MPEP 2144.07). Further still, selecting silicon nitride for the charge trap layer meets these criteria, as it is a known choice in the art for such devices, as evidenced by RABKIN, Par. 32 & 36.
CHOI does not disclose:
wherein the removal method of the removal process is etching
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention select etching for the removal method of the removal process for CHOI, as CHOI discloses selectively removing the fluorine (F) containing layer but does not disclose the associated removal method. Therefore, a person having ordinary skill in the art would look to the prior art for a removal method recognized for its suitability and intended purpose (MPEP 2144.07). Further still, selecting etching for the removal method meets these criteria, as it is a known choice in the art for such devices, as evidenced by RABKIN, Par. 42, 47, 48, & 52.
Regarding Claim 12,
CHOI discloses:The method of claim 11, wherein the channel (140) layer comprises polysilicon (Pag. 4, Par. 2).
Regarding Claim 14,
CHOI discloses:The method of claim 11, wherein the first anneal process comprises a spike anneal process (Page. 11, Par. 8: “relatively high temperature for a relatively short time”), and concentration of fluorine atoms in the channel (140) layer after the first anneal process is greater than 1x 1014 /cm3 (Pag. 4, Par. 1 & Pag. 6, Par. 3).
Regarding Claim 17,
CHOI discloses:The method of claim 11, further comprising: subsequent to the [removal] process, performing a memory hole fill process (Fig. 9D) to deposit a filler (Fig. 9D: 170; Pag. 12, Par. 1) layer in each of the plurality of memory holes (CHH).
CHOI does not disclose:
wherein the removal method of the removal process is etching.
(See argument for Claim 11, referencing RABKIN, Par. 42, 47, 48, & 52)
Regarding Claim 18,
CHOI discloses:The method of claim 17, wherein the filler (170) layer comprises (Pag. 5, Par. 3) silicon dioxide (SiO2), aluminum oxide (A12O3), or silicon nitride (Si3N4).
Regarding Claim 19,
CHOI discloses:The method of claim 17, further comprising: subsequent to the memory hole fill (Fig. 9D) process, performing a mold pull back (Fig. 9F) process to remove (Pag, 12, Par. 9) the dummy nitride (180) layers of the plurality of alternating (120/180) layers and deposit word line (Fig. 9F: 130; Pag. 12, Par. 10) layers.
Regarding Claim 20,
CHOI discloses:The method of claim 19, further comprising: forming a drain region (Fig. 9D: 175; Pag. 5, Par. 4) layer over the plurality of alternating (120/180) layers, wherein at least a portion of the formed channel structure (CH) is coupled to a portion of the drain region (175) layer (Pag. 5, Par. 4) and coupled to a portion of a source region (Fig. 9F: 102; Pag. 2, Par. 2) layer of the three-dimensional memory device (As seen in Fig. 9F).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over CHOI in view of RABKIN and in further view of MITANI (US 6191463 B1).
Regarding Claim 13,
CHOI discloses:The method of claim 11, wherein the fluorine containing (160) layer deposition process comprises forming a fluorine (F)-containing [polycrystalline] silicon (Pag. 8, Par. 6) layer on the channel (140) layer.
CHOI does not disclose:
forming a fluorine (F)-containing amorphous silicon layer
MITANI discloses:
forming a fluorine (F)-containing amorphous silicon layer (Col. 27, Lin. 5 – 35)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of CHOI with those of MITANI to enable the forming a fluorine (F)-containing amorphous silicon layer to be performed in CHOI according to the teachings of MITANI, as the fluorine (F)-containing silicon layers of CHOI and MITANI are recognized in the art for the same purpose of providing a source of fluorine to be diffused into a layer adjacent to the fluorine (F)-containing silicon layer during an anneal in order to passivate the adjacent layer with fluorine (MPEP 2144.06).
Claims 15 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI in view of RABKIN and in further view of LU (US 20170229472 A1).
Regarding Claim 15,
CHOI does not disclose:The method of claim 11, further comprising: subsequent to the etching process, performing a second anneal process to drive hydrogen atoms from a hydrogen or deuterium containing environment to diffuse into the channel layer.
LU discloses:
performing a second anneal process (Par. 101 – 103) to drive hydrogen atoms from a hydrogen or deuterium containing environment (Par. 101: “dielectric core”) to diffuse into the channel (Par. 101: “polycrystalline channel”) layer.
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of CHOI with those of LU to enable performing a second anneal process to drive hydrogen atoms from a hydrogen or deuterium containing environment to diffuse into the channel layer in CHOI according to the teachings of LU for the further advantage of enhancing the conductivity of the channel layer via passivation (LU, Par. 101).
Regarding Claim 16,
CHOI does not disclose:The method of claim 15, wherein the second anneal process comprises a spike anneal process, and concentration of hydrogen atoms in the channel layer after the second anneal process is greater than 1x 1014 /cm3.
LU discloses:
wherein the second anneal process (Par. 101 – 103) comprises a spike anneal process (Par. 103 teaches “limiting the duration and/or the temperature of the [second] anneal process”), and concentration of hydrogen atoms in the channel layer after the second anneal process is greater than 1x 1014 /cm3 (Par. 103).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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