Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant's arguments directed to the newly amended claim filed 3/12/2026 have been fully considered but they are not persuasive.
The amendments correct the issues which resulted in the rejection under 35 USC 112, therefore the rejection has been withdrawn.
Specifically, regarding the new amendments, they are not understood to provide a clear structural distinction over the cited art. Claim 1 now recites “includes a conductive layer, is electrically connected to any of the plurality of common electrodes, and is disposed in a different layer from the plurality of common electrodes.” This language is broad and ambiguous and does not provide a clear structural distinction in the device structure. Previously Identified common electrode 372 is understood to be part of the overall circuit thus is “electrically connected” to another conductive layer. See Fig. 2 of Kim. Common electrodes 372 are shown to be connected to Vcom which is shown through the circuit diagram to be connected to various conductive lines shown in the cross section al figures [e.g. fig. 5] to be clearly in different levels/layers and as best understood meet the broad scope of the recited feature under broadest reasonable interpretation (BRI)..
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220358889 A1) in view of Li et al. (US 20210325748 A1).
PNG
media_image1.png
754
440
media_image1.png
Greyscale
PNG
media_image2.png
504
698
media_image2.png
Greyscale
An array substrate, comprising:
a plurality of common electrodes 372 (Kim et al. Figs. 3 & 5 – Note: While Kim et al. may be silent upon “a plurality” or common electrodes, it would be inferred that the array substrate comprises a plurality of common electrodes. As disclosed in Li et al. figure 2A & paragraph [0026]1 describing an analogous pixel array substrate, Li teaches wherein the plurality of common electrode patterns are generally expected to be one-to-one correspondence with the plurality of pixel unit groups. As such, it would be obvious to a PHOSITA to extrapolate from the figures 3 and 5 of Kim et al. to expect the presence of a plurality of common electrodes with a one-to-one correspondence to the pixel unit groups shown in figure 3.);;
a plurality (Kim et al. Fig. 3 – Demonstrates an array of pixel groups, each having a subset of pixel electrodes.) of pixel electrodes 371 disposed overlapping the plurality of common electrodes 372 via a first insulating film 370;
a plurality of switching elements TR connected to the plurality of pixel electrodes; and
a plurality of wiring lines DL connected to any of the plurality of common electrodes or any of the plurality of switching elements (Fig. 2 & 3),
PNG
media_image3.png
482
416
media_image3.png
Greyscale
PNG
media_image4.png
756
426
media_image4.png
Greyscale
wherein the plurality of pixel electrodes include a first pixel electrode, a second pixel electrode disposed being spaced apart from the first pixel electrode in a first direction, a third pixel electrode, and a fourth pixel electrode disposed being spaced apart from the third pixel electrode in the first direction (Kim et al. depicts a plurality of pixel groups in the array. Each group may be designated 1st through 4th, each spaced apart, thereby meeting the scope of the limitation.), the plurality of wiring lines include a first wiring line DL2n located between the first pixel electrode (pixel group viewed to the LEFT of the wiring line.) and the second pixel electrode (pixel group viewed to the RIGHT of the wiring line.) in the first direction (e.g. the direction perpendicular to the direction of wiring lines DL as shown in fig. 3), and extending along a second direction intersecting with the first direction (pixel groups are shown to have a plurality of pixel finger electrodes 371 which extend in the second direction.), and also include a second wiring line GL located between the third pixel electrode and the fourth pixel electrode in the first direction, and extending along the second direction,
PNG
media_image5.png
776
474
media_image5.png
Greyscale
PNG
media_image3.png
482
416
media_image3.png
Greyscale
the plurality of switching elements TR (A switching element corresponds to each pixel group [e.g. fig. 2]) include a first switching element TR connected to the first wiring line DL and the first pixel electrode 371, and a second switching element TR (e,g, a second pixel group fig. 3 above) connected to the second wiring GL line and the third pixel electrode (e,g, a third pixel group fig. 3 above. See also Kim et al. Fig. 4 – demonstrates the Gate line connecting the gates along the second direction.),
PNG
media_image6.png
480
450
media_image6.png
Greyscale
the plurality of common electrodes include a first common electrode and a second common electrode being spaced apart from the first common electrode] in the first direction ( Kim et al. Fig. 5 depicts a cross sectional view showing portions of a common electrode 372 having spaced portions. As addressed above and supported by Li et al ¶26, it is a general expectation in the display array substrate art, that each pixel group may have a corresponding common electrode. As such it would at least be obvious to expect the common electrode could or would be spaced apart.),
the first switching element includes a first semiconductor portion S, A, D (Kim et Fig. 5 & al. ¶74-75 – Transistors are formed of semiconductor materials.), the second switching element includes a second semiconductor portion S, A, D (Kim et Fig. 5 & al. ¶74-75 – Transistors are formed of semiconductor materials.),
PNG
media_image2.png
504
698
media_image2.png
Greyscale
the first common electrode 372 is disposed overlapping the first pixel electrode 371 , the second pixel electrode 371 (e.g. second pixel group of fig. 3), the third pixel electrode 371 (e.g. third pixel group of fig. 3), the first wiring line DL, and at least the first semiconductor portion TR of the first switching element, the second common electrode is disposed overlapping the fourth pixel electrode and the second wiring line, and there is provided an overlapping portion that is disposed overlapping at least the second semiconductor portion of the second switching element and has a potential identical to the potential of any of the plurality of common electrodes (As best understood, Kim et al. depicts the common electrode in the same manner as applicant’s fig. 5. As shown the common electrodes are shown to overlap with the recited element. Paragraph [0055] of Kim et al. teaches that common electrodes are connected at “common voltage Vcom.”) includes a conductive layer, is electrically connected to any of the plurality of common electrodes, and is disposed in a different layer from the plurality of common electrodes (This limitation does not provide a clear structural distinction in the device structure. Identified common electrode 372 is understood to be part of the overall circuit thus is “electrically connected” to another conductive layer. See Fig. 2 of Kim. Common electrodes 372 are shown to be connected to Vcom which is shown through the circuit diagram to be connected to various conductive lines shown in the cross section al figures [e.g. fig. 5] to be clearly in different levels/layers.).
Claim(s) 2-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220358889 A1) in view of Li et al. (US 20210325748 A1) in view of Nishiyama et al. (US 20200064669 A1
CLAIM 2. Kim in view of Li teach an array substrate according to claim 1, however is silent upon the capability of the common electrodes being capable of functioning as position sensors. At the time of the invention, analogous common electrodes in an analogous display array substrate were known to be capable of position detection. Nishiyama teaches an analogous display array substrate as recited in claim 1 and as disclosed by Kim. Paragraph ¶[0079] of Nishiyama teaches common electrode such and found in Kim, when “in pair with the pixel electrode” may both be “used during the controlling operation for displaying an image, and is also used during the controlling operation for detecting a touch position.”
Nishyama teaches, wherein the plurality of common electrodes 17 are a plurality of position detection electrodes ¶79, the first common electrode is a first position detection electrode, the second common electrode is a second position detection electrode, the plurality of wiring lines include a third wiring line extending along the first direction (Figs 4 – depicts Source and Signal lines 202 extending in the first direction between pixel groups. Fig. 15 depicts control lines 411 further located extending in the first direction between pixel groups) , and connected to any of the plurality of position detection electrodes (¶76 – common electrodes 17 are connected to Signal lines 202), and a fourth wiring line 411 extending along the first direction and connected to at least the second switching element (Fig. 15), at least part of the third wiring line is disposed overlapping the fourth wiring line via a second insulating film, part of the third wiring line is disposed overlapping the second semiconductor portion, and the overlapping portion includes a first overlapping portion constituted by a portion of the third wiring line overlapping the second semiconductor portion (Fig. 11 – Source and signal lines are shown to overlap in the plan view over transistor switching elements 12.).
At the time of the invention it would be obvious to a PHOSITA to modify the circuit of Kim with third and fourth wiring extending in the first direction along with the first wiring, since applying a known technique (providing wiring to enable dual function of the common electrodes) to a known device ready for improvement (a display array substrate) to yield predictable results (e.g. display control and position detection) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 3. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 2, wherein the second switching element includes a first electrode connected to part of the second semiconductor portion and disposed overlapping part of the third pixel electrode (Kim & Nishiyama – Transistors), and is provided with a second electrode disposed overlapping part of the first electrode and part of the third pixel electrode (Kim fig. 4 & 5; Nishiyama fig. 11 – As shown in Kim and Nishiyama gate, signal, control lines overlap at the electrodes of the switching element electrodes and pixel electrodes.), the third wiring line is formed of a first conductive film located on a lower-layer side relative to any of the plurality of position detection electrodes and the plurality of pixel electrodes via a third insulating film (Kim fig. 4 & 5; Nishiyama fig. 11 – Switching element wiring is shown to be located below the common electrodes.),, the fourth wiring line (Nishiyama – 411) is formed of a second conductive film located on a lower-layer side relative to the first conductive film via the second insulating film(Nishiyama – 411 – “the gate drivers 40 corresponding to the odd-numbered gate lines G (G(1), G(3), G(5), . . . ) are connected with one another via control lines 411” - being connected to the gate would require at least a portion of the wiring line to be located in the recited location.), the first electrode is formed of a portion of the second conductive film different from the fourth wiring line, the second electrode is formed of a portion of the first conductive film different from the third wiring line and the first overlapping portion, and is connected to the third pixel electrode and the first electrode overlapping each other, and the first overlapping portion is disposed to be aligned being spaced apart from the second electrode in the second direction (Kim illustrates TFT structure [Figs. 4&5] where S/D electrodes, formed of a second metal layer, overlap a planar common electrode 372 and pixel electrodes. Nishiyama similarly shows that conductive films used for wiring are also used to form the transistor electrodes. It is standard practice to utilize the existing metal layers, first and second conductive films, to define the electrodes of the switching elements (TFTs) to simplify manufacturing processes.)
CLAIM 4. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 3, wherein the second switching element includes a third electrode connected to a section of the second semiconductor portion different from a section of the second semiconductor portion connected to the first electrode, the third electrode is constituted by part of the fourth wiring line, and the first electrode includes a first portion overlapping the second electrode, and a second portion extending from the first portion along the second direction and connected to part of the second semiconductor portion (Kim illustrates TFT structure [Figs. 4&5] where S/D electrodes, formed of a second metal layer, overlap a planar common electrode 372 and pixel electrodes. Nishiyama similarly shows that conductive films used for wiring are also used to form the transistor electrodes. It is standard practice to utilize the existing metal layers, first and second conductive films, to define the electrodes of the switching elements (TFTs) to simplify manufacturing processes.)
CLAIM 5. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 2, wherein the plurality of wiring lines include a fifth wiring line extending along the first direction, overlapping the first position detection electrode, disposed not overlapping the second position detection electrode, and connected to the first position detection electrode (Nishiyama teaches signal lines that are aligned with and connected to specific partitioned common electrodes used for auxiliary functions like sensing, [0072-79]), a sixth wiring line extending along the first direction, overlapping the second position detection electrode, disposed not overlapping the first position detection electrode, and connected to the second position detection electrode (Nishiyama teaches a plurality of control lines connected to specific segmented electrode areas, [0120-124]), and a seventh wiring line which extends along the first direction, and at least part of which is disposed overlapping the fifth wiring line and the sixth wiring line via the second insulating film (Nishiyama teaches multi-layer wiring where different signal lines are stacked and inferred to be separated by insulating films, [0124]. Kim fig. 4-5 demonstrates insulation layers separating stacked metallization layers.), the plurality of switching elements include a third switching element connected to the second wiring line and the seventh wiring line (Nishiyama teaches pixel switching elements connected to gate and source lines, [0120-124]), the third switching element includes a third semiconductor portion (Kim teaches a TFT including an active layer A, [0082-53]), part of the fifth or sixth wiring line is disposed overlapping the third semiconductor portion (Kim teaches that conductive portions are strategically disposed to overlap the semiconductor active layer, [0082-95] & Figs. 4-5), and the overlapping portion includes a second overlapping portion constituted by a portion of the fifth or sixth wiring line overlapping the third semiconductor portion (Kim teaches using a conductive bump BP as an overlapping shield for the active layer, [0082-95] & Figs. 4-5).
CLAIM 6. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 2, wherein the plurality of position detection electrodes include a third position detection electrode aligned being spaced apart from the first position detection electrode in the second direction (Kim Figs. 4-5 & Nishiyama teaches partitioning the common electrode layer into a plurality of sensing regions or blocks, [0015, 30-31 ]), the plurality of wiring lines include an eighth wiring line extending along the first direction, disposed being interposed between the first position detection electrode and the third position detection electrode, and disposed overlapping neither the first position detection electrode nor the third position detection electrode (Nishiyama teaches that signal lines are arranged in a space between two columns of pixels where no other source line is arranged, [0028-29]), and a ninth wiring line which extends along the first direction, and at least part of which is disposed overlapping the eighth wiring line via the second insulating film (Nishiyama teaches a multi-layer structure where different wiring lines are provided in a stacked arrangement, [0120-124]), the eighth wiring line is directly or indirectly connected to any of the plurality of position detection electrodes (Nishiyama teaches signal lines connected with the common electrodes for sensing, [0031]), the plurality of switching elements include a fourth switching element connected to the second wiring line and the ninth wiring line (Nishiyama teaches switching elements connected to specific data and control lines, [0120-124]), the fourth switching element includes a fourth semiconductor portion (Kim teaches a transistor including an active layer A, [0082-95] & Figs. 4-5), part of the eighth wiring line is disposed overlapping the fourth semiconductor portion (Kim teaches disposing conductive elements to overlap the active layer of the transistor, [0082-95] & Figs. 4-5),, and the overlapping portion includes a third overlapping portion constituted by a portion of the eighth wiring line overlapping the fourth semiconductor portion (Kim teaches a bump BP or electrode portion overlapping the active layer to act as a shield, 0082-95] & Figs. 4-5).
CLAIM 7. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 1, wherein the plurality of common electrodes are a plurality of position detection electrodes (Nishiyama teaches that the common electrodes can be utilized for position detection/sensing, [0072-79]), the first common electrode is a first position detection electrode, the second common electrode is a second position detection electrode (Nishiyama teaches partitioning electrodes for auxiliary coordinate detection, [0015, 30-31]), the plurality of wiring lines include a tenth wiring line extending along the first direction and connected to any of the plurality of position detection electrodes (Nishiyama teaches signal lines connected to segmented common electrodes, [0031]), and an eleventh wiring line extending along the first direction and connected to at least the second switching element (Nishiyama teaches source lines connected to pixel switching elements, [0028-29]), the eleventh wiring line is formed of a third conductive film located on a lower-layer side relative to any of the plurality of position detection electrodes and the plurality of pixel electrodes via a fourth insulating film (Kim figs. 4-5 & Nishiyama teaches using lower-layer metal films for routing below the pixel electrode, [0120-124]), the tenth wiring line is formed of a portion of the third conductive film different from the eleventh wiring line, and disposed to be aligned being spaced apart from the eleventh wiring line in the second direction (Nishiyama teaches that source lines and control lines are formed of conductive films and spaced apart in light-shielding areas, [0120-124]), the plurality of pixel electrodes are formed of a fourth conductive film (Kim teaches pixel electrodes 371 formed of a distinct transparent conductive layer, [0087-91]), and the overlapping portion includes a fourth overlapping portion constituted by a portion of the fourth conductive film different from the plurality of pixel electrodes (Kim teaches that auxiliary conductive patterns can be formed in the same layer as the pixel electrodes, Figs. 4-5 & [0087-91]).
CLAIM 8. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 7, wherein the fourth overlapping portion includes a fifth overlapping portion having a third portion overlapping the first position detection electrode or the second position detection electrode (Nishiyama teaches that connection portions 11b or bridges overlap electrode layers to facilitate interconnection, [0049-53] &Fig. 4 & Kim Figs 4-5)), and the third portion of the fifth overlapping portion is connected to the first position detection electrode or the second position detection electrode (Nishiyama teaches using connection portions to link segmented sensing elements, [054-55 & 77-78]).
CLAIM 9. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 7, wherein the fourth overlapping portion includes a sixth overlapping portion having a fourth portion overlapping the tenth wiring line (Nishiyama teaches routing lines that overlap sensing electrodes via insulating films, [0120-124]), and the fourth portion of the sixth overlapping portion is connected to the tenth wiring line (Nishiyama teaches connecting sensing signals to peripheral wiring lines through inter-layer vias, [0120-124]).
CLAIM 10. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 1, wherein the first common electrode and the second common electrode are disposed to interpose the second semiconductor portion between the first and second common electrodes in the first direction and not to overlap the second semiconductor portion (Kim illustrates layouts where the planar common electrode is patterned to avoid specific transistor areas, Fig. 5).
CLAIM 11. Kim in view of Li in view of Nishiyama teach an array substrate according to claim 1, wherein part of the first common electrode or the second common electrode is disposed overlapping the second semiconductor portion (Kim teaches a planar common electrode 372 that is disposed over the thin film transistor, [0087-95]), and the overlapping portion is constituted by a portion of the first common electrode or the second common electrode overlapping the second semiconductor portion (Kim teaches using the wide planar electrode as a shield for the underlying transistor, [0087-95]).
CLAIM 12. Kim in view of Li in view of Nishiyama teach an display device, comprising: the array substrate according to claim 1; and a counter substrate disposed to face the array substrate (Kim & Nishiyama both teach a liquid crystal display device comprising an active matrix substrate and a counter substrate opposed to it, Kim [0017]; Nishiyama [0037]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
3/24/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Li et al. = ¶ [0026] For example, in at least one example of the array substrate, the array substrate further comprises a plurality of common electrode patterns arranged in an array; the plurality of common electrode patterns are in one-to-one correspondence with the plurality of pixel unit groups; common electrode patterns in a same row are between a first gate line and a second gate line which are for driving pixel unit groups corresponding to the common electrode patterns in the same row; common electrode patterns adjacent in the first direction are electrically connected to each other through a first common electrode connection portion, and the first common electrode connection portion is in a layer same as the common electrode patterns; and common electrode patterns adjacent in the second direction are electrically connected to each other through a second common electrode connection portion, and the second common electrode connection portion is in a layer same as the first connection portion, and the second common electrode connection portion and a corresponding common electrode pattern are electrically connected through a third via-hole.