Attorney’s Docket Number: TSMC 200146US01
Filing Date: 9/08/2023
Inventors: Song et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 7/07/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendments filed on 7/07/2026, responding to the Office action mailed 4/07/2026, has
been entered. Applicant amended claims 1, 13-14, and 21. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendments
Applicant’s amendments to the claims overcome the drawing objections and claim rejections under 35 U.S.C. 112 and 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 4/07/2026. Accordingly, pending in this application are claims 1-17 and 21-23. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20160358919 A1) in view of Ma (US 8420488 B2).
Regarding claim 1, Chen (see, e.g., figs. 3-4) shows most aspects of the instant invention including a method for forming a gate oxide layer of a high voltage transistor comprising:
Forming a recess (see, e.g., formation of recess 409 in fig. 3) in a substrate (e.g., 300);
Thermally oxidizing (see, e.g., paragraph 18 “Preferably, the first dielectric layer 410 is also formed by a second thermal oxidization process”) exposed surfaces of the recess (e.g., recess 409) to form a thermal oxide layer (e.g., first dielectric 410 layer formed via thermal oxidization of paragraph 18) of the gate oxide layer (e.g., first dielectric layer 410);
Chen (see, e.g., figs. 3-4), however, fails to show performing chemical vapor deposition upon the thermal oxide layer to fill a remainder of the recess and form a high temperature oxide layer of the gate oxide layer.
Ma (see, e.g., fig. 1A), in a similar device to Chen, teaches performing chemical vapor deposition (see, e.g., paragraph 11 “the high temperature oxide material layer 112 is formed by low pressure-CVD process, for example”) upon a thermal oxide layer (e.g., thermal oxide layer 110) to fill a recess (see, e.g., recess within the silicon nitride layers out of which the high temperature oxide extends) and form a high temperature oxide layer (e.g., chemical vapor deposited material layer 112 + paragraph 11 “…the chemical vapor deposited material layer 112 is a high temperature oxide layer (HTO)”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chemical vapor deposition of Ma onto the thermal oxide layer of Chen, in order to improve the uniform thickness of the oxide layer within the device (see, e.g., paragraph 12 of Ma).
Regarding claim 10, Ma (see, e.g., fig. 1A) teaches wherein the high temperature oxide layer (e.g., chemical vapor deposited material layer 112 + paragraph 11 “…the chemical vapor deposited material layer 112 is a high temperature oxide layer (HTO)”) forms a rim extending out of the recess (see, e.g., recess within the silicon nitride layers out of which the high temperature oxide extends).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the rim extension of Ma within the high temperature oxide layer of Chen in view of Ma, in order to improve the uniformity and insulating profile within the recess of the device as desired.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ma further in view of Tezuka (US 20140106502 A1).
Regarding claim 2, Chen in view of Ma fails to teach wherein the thermal oxidation occurs at a temperature of about 900°C to about 950°C.
Tezuka (see, e.g., fig. 4A), in a similar device to Chen in view of Ma, teaches a thermal oxidation process (e.g., thermal oxidation process of paragraph 181) occurs at a temperature of 950°C (see, e.g., paragraph 181 “Thermal oxidation was performed on a silicon substrate….to form a thermal oxide film…the thermal oxidation was performed at 950.degree.C…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxidation temperature profile of Tezuka within the thermal oxidation of Chen in view of Ma, as 950°C was a known-temperature at the time of filing the invention to use as a thermal oxidizing temperature for forming a thermal oxide layer on a silicon substrate, as taught by Tezuka (see, e.g., paragraphs 181-182).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ma further in view of Lin (US 20140252486 A1).
Regarding claim 3, Chen in view of Ma fails to teach wherein the chemical vapor deposition occurs at a temperature of about 780°C to about 800°C.
Lin (see, e.g., fig. 1B), in a similar device to Chen in view of Ma, teaches a chemical vapor deposition occurs at 780°C to 800°C (see, e.g., paragraph 20 “…CVD techniques…deposition temperatures ranging from 550.degree to 900.degree. C”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chemical vapor deposition temperature profile of Lin within the chemical vapor deposition of Chen in view of Ma, as a range within 780°C to 800°C was a known-temperature at the time of filing the invention to use as a chemical vapor deposition temperature on an oxide layer (see, e.g., paragraph 20 of Lin).
Regarding claim 4, Chen in view of Ma fails to explicitly wherein the chemical vapor deposition uses a silicon precursor.
Lin (see, e.g., fig. 1B), in a similar device to Chen in view of Ma, teaches a chemical vapor deposition uses a silicon precursor (see, e.g., paragraph 20 “…CVD techniques using TEOS…silane…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chemical vapor deposition silicon precursor of Lin within the chemical vapor deposition of Chen in view of Ma, as silicon was a well-known precursor/material to be included within a chemical vapor deposition process at the time of filing the invention, as taught by Lin.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ma further in view of Fujimoto (US 20080073709 A1).
Regarding claim 5, Chen in view of Ma fails to teach the thermal oxide layer has a thickness of about 50 to about 80 angstroms.
Fujimoto (see, e.g., fig. 6A), in a similar device to Chen in view of Ma, teaches a thermal oxide layer (e.g., thermal oxide film 12) has a thickness within a range of 50 to 80 angstroms (see, e.g., paragraph 56 “…thermal oxide film 12…having a thickness of about 6-8 nm…” + note 6-8 nm is equivalent to 60 to 80 angstroms).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxide thickness profile of Fujimoto within the method of Chen in view of Ma, in order to achieve the expected result of providing a distinct thermal oxide profile while simultaneously limiting the space required for the thermal oxide layer.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ma further in view of Mahajani (US 20050062098 A1).
Regarding claim 6, Chen in view of Ma fails to teach the high temperature oxide layer has a thickness of about 140 angstroms to about 170 angstroms.
Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Ma, teaches a high temperature oxide layer (e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…”) has a thickness within the range of 140 to 170 angstroms (see, e.g., paragraph 38 “…about 30 to 200 angstroms thick…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the high temperature oxide layer of Chen in view of Ma, in order to achieve the expected result of providing a distinct high temperature oxide profile while simultaneously limiting the space required for the layer.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ma further in view of Fujimoto and Mahajani.
Regarding claim 7, Chen in view of Ma fails to teach the gate oxide layer has a thickness of about 200 angstroms to about 250 angstroms.
Fujimoto (see, e.g., fig. 6A), in a similar device to Chen in view of Ma, teaches a thermal oxide layer (e.g., thermal oxide film 12) has a thickness within a range of 50 to 80 angstroms (see, e.g., paragraph 56 “…thermal oxide film 12…having a thickness of about 6-8 nm…” + note 6-8 nm is equivalent to 60 to 80 angstroms).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxide thickness profile of Fujimoto within the method of Chen in view of Ma, in order to achieve the expected result of providing a distinct thermal oxide profile while simultaneously limiting the space required for the thermal oxide layer. Note that the gate oxide layer is made up of both the thermal oxide layer and the high temperature oxide layer, and hence the thermal oxide layer comprises 60 to 80 angstroms of the 200-250 angstrom gate oxide layer range.
Chen in view of Ma further in view of Fujimoto, however, fails to teach the high temperature oxide layer suffices the remaining gate oxide layer angstrom range.
Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Ma further in view of Fujimoto, teaches a high temperature oxide layer (e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…”) has a thickness within the range of 140 to 170 angstroms (see, e.g., paragraph 38 “…about 30 to 200 angstroms thick…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the high temperature oxide layer of Chen in view of Ma further in view of Fujimoto, in order to achieve the expected result of providing a distinct high temperature oxide profile while simultaneously limiting the space required for the layer. Note that 60 to 80 angstroms of the gate oxide layer were already accounted for (see, e.g., paragraph 28 above), and hence the remaining approximate 180 angstrom thickness is satisfied (see, e.g., upper thickness of Mahajani range).
Regarding claim 8, Chen in view of Ma fails to teach wherein a ratio of a thickness of the thermal oxide layer to a thickness of the high temperature oxide layer is from about .40 to about .55.
Fujimoto (see, e.g., fig. 6A), in a similar device to Chen in view of Ma, teaches a thermal oxide layer (e.g., thermal oxide film 12) has a thickness within a range of 50 to 80 angstroms (see, e.g., paragraph 56 “…thermal oxide film 12…having a thickness of about 6-8 nm…” + note 6-8 nm is equivalent to 60 to 80 angstroms).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxide thickness profile of Fujimoto within the method of Chen in view of Suzawa, in order to achieve the expected result of providing a distinct thermal oxide profile while simultaneously limiting the space required for the thermal oxide layer.
Chen in view of Ma further in view of Fujimoto, however, fails to teach the high temperature oxide layer suffices the remaining gate oxide layer angstrom range.
Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Ma further in view of Fujimoto, teaches a high temperature oxide layer (e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…”) has a thickness within the range of 140 to 170 angstroms (see, e.g., paragraph 38 “…about 30 to 200 angstroms thick…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the high temperature oxide layer of Chen in view of Suzawa further in view of Fujimoto, in order to achieve the expected result of providing a distinct high temperature oxide profile while simultaneously limiting the space required for the layer. Note that the ratio of, for example, 60 nanometers (thermal oxide layer thickness) to 150 nanometers (high temperature oxide layer thickness) is .40.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ma further in view of Hu (US 20100001364 A1).
Regarding claim 9, Chen in view of Ma fails to teach wherein the gate oxide layer has a breakdown voltage of at least 8 volts.
Hu (see, e.g., claim 5), in a similar device to Chen in view of Ma, teaches a gate oxide layer has a breakdown voltage of greater than 8 volts (see, e.g., claim 5 “…wherein an average HV gate oxide breakdown voltage is greater than 14 volts”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high voltage breakdown configuration of Hu within the gate oxide of Chen in view of Ma, in order to enhance the performance and voltage rating within the device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ma further in view of Kim (US 20250072044 A1).
Regarding claim 11, Kim (see, e.g., fig. 3A) teaches wherein the rim (e.g., upper corner 268, note extension out of recess) has a height of around 10 nm (see, e.g., paragraph 75).
With regards to the particular spacing distance claimed, i.e. 40 to 60 angstroms, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Kim teaches a rim length above the recess of around 100 angstroms (note that 10 nm is equivalent to 100 angstroms), it would have been obvious to one of ordinary skill in the art at the time of filing the invention to slightly modify this height value of the rim past the recess of Chen in view of Suzawa further in view of Kim, to expand or isolate the corner of the gate oxide layer around the gate or device area as desired. In addition, including this rim extension assisting in altering the breakdown configuration within the oxide layer away from the gate trench/recess area, increasing the efficiency and reliability of the device (see, e.g., paragraph 73 of Kim).
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed distance ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ma further in view of Mahajani.
Regarding claim 12, Chen in view of Ma fails to teach the rim of the high temperature oxide layer has a thickness of about 140 angstroms to about 170 angstroms.
Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Ma, teaches a high temperature oxide layer (e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…”) has a thickness within the range of 140 to 170 angstroms (see, e.g., paragraph 38 “…about 30 to 200 angstroms thick…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the rim of the high temperature oxide layer of Chen in view of Ma, in order to achieve the expected result of providing a distinct high temperature oxide rim profile while simultaneously limiting the space required for the rim.
Allowable Subject Matter
Claims 14-17 and 21-23 are allowed.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, Chen (US 20160358919 A1) in view of Suzawa (20200051852 A1) further in view of Ma (US 8420488 B2), Lin (US 20220302145 A1)(hereinafter Lin2) and Kim (US 20120018800 A1) (hereinafter Kim2) teaches most aspects of the method.
However, Chen in view of Suzawa further in view of Ma, Lin2, and Kim2 fails to disclose or suggest forming the etch stop layer directly on a semiconducting substrate, then removing the entire etch stop layer to obtain a gate oxide layer within the recess, the gate oxide layer comprising the thermal oxide layer and the high temperature oxide layer.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Regarding claim 21, Chen (US 20160358919 A1) in view of Suzawa (20200051852 A1) further in view of Ma (US 8420488 B2), Lin (US 20220302145 A1)(hereinafter Lin2) and Kim (US 20120018800 A1) (hereinafter Kim2) teaches most aspects of the method.
However, Chen in view of Suzawa further in view of Ma, Lin2, and Kim2 fails to disclose or suggest removing the entire etch stop layer to obtain a gate oxide layer within the recess, the gate oxide layer comprising the thermal oxide layer and the high temperature oxide layer.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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