Attorney’s Docket Number: TSMC 200146US01 Filing Date: 9/08/2023 Inventors: Song et al. Examiner: Thomas McCoy DETAILED ACTION This Office action responds to the election filed 3/06/2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant's election without traverse of invention I, reading on a method , in the reply filed on 3 / 06 /202 6 , is acknowledged. The applicant cancelled claims 18-20, added claims 21-23, and indicated that claims 1-17 and 21-23 read on the elected invention. The examiner agrees . Drawings The drawings are objected to because the figures 14 and 15 are flipped, as opposed to the specification (see pages 15-16 of the specification, noting the highlighting of the double hump effect in figure 15, but the drawings instead show this feature in figure 14). In addition, there seems to be a “5” between the 3.5 and 4 offset bias voltage thresholds, which is unclear and undescribed within the specification. In addition, there is an unlabeled layer beneath capping layer 190 and a reference to this component has not been found in any of the figures. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim s 1 3-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Claim 13 recites the limitation “… the rim …”. There is no antecedent basis for this claim. The examiner believes that a typographical mistake was introduced and claim 13 was meant to depend from claim 10 , which would resolve the 112b issues raised supra. Accordingly, for the purpose of examination, claim 13 will be construed as reciting “The method of claim 10 …”. Claim 14 recites the limitation “…the gate oxide layer”. There is no antecedent basis for this claim. Accordingly, for the purpose of examination, the first recitation of “…the gate oxide layer…” in claim 14 will be construed to recite “…a gate oxide layer…”. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1 is rejected under 35 U.S.C. 10 3 as being unpatentable over Chen (US 20160358919 A1) in view of Suzawa (US 20200051852 A1) . Regarding claim 1, Chen (see, e.g., fig s . 3-4 ) shows most aspects of the instant invention including a method for forming a gate oxide layer of a high voltage transistor comprising: Forming a recess ( see, e.g., formation of recess 409 in fig. 3 ) in a substrate ( e.g., 300 ) ; Thermally oxidizing ( see, e.g., paragraph 18 “ Preferably, the first dielectric layer 410 is also formed by a second thermal oxidization process ” ) exposed surfaces of the recess ( e.g., recess 409 ) to form a thermal o xide layer ( e.g., first dielectric 410 layer formed via thermal oxidization of paragraph 18 ) of the gate oxide layer ( e.g., first dielectric layer 410 ); Chen (see, e.g., figs. 3-4), however, fails to show performing chemical vapor deposition upon the thermal oxide layer to form a high temperature oxide layer of the gate oxide layer . Suzawa (see, e.g., figs . 3-4 ), in a similar device to Chen, teaches performing chemical vapor deposition upon a thermal oxide layer ( see, e.g., paragraph 84 “…the HTO film 11 is formed by, for example, a CVD method as a first layer of the interlayer insulating film 13” ) to form a high temperature oxide layer ( e.g., HTO film 11 ) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chemical vapor deposition of Suzawa onto the thermal oxide layer of Chen, in order to enhance the insulating properties within the gate oxide of the transistor. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Tezuka (US 20140106502 A1) . Regarding claim 2, Chen in view of Suzawa fails to teach wherein the thermal oxidation occurs at a temperature of about 900 ° C to about 950 ° C . Tezuka (see, e.g., fig. 4A), in a similar device to Chen in view of Suzawa , teaches a thermal oxidation process ( e.g., thermal oxidation process of paragraph 181 ) occurs at a temperature of 950 ° C ( see, e.g., paragraph 181 “Thermal oxidation was performed on a silicon substrate….to form a thermal oxide film…the thermal oxidation was perform ed at 950.degree.C … ” ) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxidation temperature profile of Tezuka within the thermal oxidation of Chen in view of Suzawa , as 950 ° C was a known-temperature at the time of filing the invention to use as a thermal oxidizing temperature for forming a thermal oxide layer on a silicon substrate, as taught by Tezuka (see, e.g., paragraphs 181-182). Claim s 3 -4 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Lin (US 20140252486 A1) . Regarding claim 3, Chen in view of Suzawa fails to teach wherein the chemical vapor deposition occurs at a temperature of about 780 ° C to about 800 ° C. Lin (see, e.g., fig. 1B), in a similar device to Chen in view of Suzawa , teaches a chemical vapor deposition occurs at 780 ° C to 800 ° C ( see, e.g., paragraph 20 “…CVD techniques…deposition temperatures ranging from 550.degree to 900.degree. C” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chemical vapor deposition temperature profile of Lin within the chemical vapor deposition of Chen in view of Suzawa , as a range within 780 ° C to 800 ° C was a known-temperature at the time of filing the invention to use as a chemical vapor deposition temperature on an oxide layer (see, e.g., paragraph 20 of Lin). Regarding claim 4, Chen in view of Suzawa fails to explicitly wherein the chemical vapor deposition uses a silicon precursor. Lin (see, e.g., fig. 1B), in a similar device to Chen in view of Suzawa , teaches a chemical vapor deposition uses a silicon precursor ( see, e.g., paragraph 20 “…CVD techniques using TEOS…silane…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chemical vapor deposition silicon precursor of Lin within the chemical vapor deposition of Chen in view of Suzawa , as silicon was a well-known precursor/material to be included within a chemical vapor deposition process at the time of filing the invention, as taught by Lin. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Fujimoto (US 20080073709 A1) . Regarding claim 5 , Chen in view of Suzawa fails to teach the thermal oxide layer has a thickness of about 50 to about 80 angstroms. Fujimoto (see, e.g., fig. 6A), in a similar device to Chen in view of Suzawa , teaches a thermal oxide layer ( e.g., thermal oxide film 12 ) has a thickness within a range of 50 to 80 angstroms ( see, e.g., paragraph 56 “…thermal oxide film 12…having a thickness of about 6-8 nm…” + note 6-8 nm is equivalent to 60 to 80 angstroms ) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxide thickness profile of Fujimoto within the method of Chen in view of Suzawa , in order to achieve the expected result of providing a distinct thermal oxide profile while simultaneously limiting the space required for the thermal oxide layer. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Mahajani (US 20050062098 A1). Regarding claim 6, Chen in view of Suzawa fails to teach the high temperature oxide layer has a thickness of about 140 angstroms to about 170 angstroms. Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Suzawa , teaches a high temperature oxide layer ( e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…” ) has a thickness within the range of 140 to 170 angstroms ( see, e.g., paragraph 38 “ …about 30 to 200 angstroms thick… ” ) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the high temperature oxide layer of Chen in view of Suzawa , in order to achieve the expected result of providing a distinct high temperat u re oxide profile while simultaneously limiting the space required for the layer. Claim s 7 -8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Fujimoto and Mahajani . Regarding claim 8, Chen in view of Suzawa fails to teach the gate oxide layer has a thickness of about 200 angstroms to about 250 angstroms. Fujimoto (see, e.g., fig. 6A), in a similar device to Chen in view of Suzawa , teaches a thermal oxide layer ( e.g., thermal oxide film 12 ) has a thickness within a range of 50 to 80 angstroms ( see, e.g., paragraph 56 “…thermal oxide film 12…having a thickness of about 6-8 nm…” + note 6-8 nm is equivalent to 60 to 80 angstroms ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxide thickness profile of Fujimoto within the method of Chen in view of Suzawa , in order to achieve the expected result of providing a distinct thermal oxide profile while simultaneously limiting the space required for the thermal oxide layer. Note that the gate oxide layer is made up of both the thermal oxide layer and the high temperature oxide layer, and hence the thermal oxide layer comprises 60 to 80 angstroms of the 200-250 angstrom gate oxide layer range. Chen in view of Suzawa further in view of Fujimoto , however, fails to teach the high temperature oxide layer suffices the remaining gate oxide layer angstrom range . Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Suzawa further in view of Fujimoto , teaches a high temperature oxide layer ( e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…” ) has a thickness within the range of 140 to 170 angstroms ( see, e.g., paragraph 38 “…about 30 to 200 angstroms thick…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the high temperature oxide layer of Chen in view of Suzawa further in view of Fujimoto , in order to achieve the expected result of providing a distinct high temperature oxide profile while simultaneously limiting the space required for the layer. Note that 60 to 80 angstroms of the gate oxide layer were already accounted for (see, e.g., paragraph 28 above), and hence the remaining approximate 180 angstrom thickness is satisfied (see, e.g., upper thickness of Mahajani range). Regarding claim 9, Chen in view of Suzawa fails to teach wherein a ratio of a thickness of the thermal oxide layer to a thickness of the high temperature oxide layer is from about .40 to about .55. Fujimoto (see, e.g., fig. 6A), in a similar device to Chen in view of Suzawa , teaches a thermal oxide layer ( e.g., thermal oxide film 12 ) has a thickness within a range of 50 to 80 angstroms ( see, e.g., paragraph 56 “…thermal oxide film 12…having a thickness of about 6-8 nm…” + note 6-8 nm is equivalent to 60 to 80 angstroms ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxide thickness profile of Fujimoto within the method of Chen in view of Suzawa , in order to achieve the expected result of providing a distinct thermal oxide profile while simultaneously limiting the space required for the thermal oxide layer. Chen in view of Suzawa further in view of Fujimoto, however, fails to teach the high temperature oxide layer suffices the remaining gate oxide layer angstrom range. Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Suzawa further in view of Fujimoto, teaches a high temperature oxide layer ( e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…” ) has a thickness within the range of 140 to 170 angstroms ( see, e.g., paragraph 38 “…about 30 to 200 angstroms thick…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the high temperature oxide layer of Chen in view of Suzawa further in view of Fujimoto, in order to achieve the expected result of providing a distinct high temperature oxide profile while simultaneously limiting the space required for the layer. Note that the ratio of, for example, 60 nanometers (thermal oxide layer thickness) to 150 nanometers (high temperature oxide layer thickness) is .40. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Hu (US 20100001364 A1) . Regarding claim 9, Chen in view of Suzawa fails to teach wherein the gate oxide layer has a breakdown voltage of at least 8 volts. Hu (see, e.g., claim 5), in a similar device to Chen in view of Suzawa , teaches a gate oxide layer has a breakdown voltage of greater than 8 volts ( see, e.g., claim 5 “…wherein an average HV gate oxide breakdown voltage is greater than 14 volts” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high voltage breakdown configuration of Hu within the gate oxide of Chen in view of Suzawa , in order to enhance the performance and voltage rating within the device. Claim s 10 -11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Kim (US 20250072044 A1). Regarding claim 10, Chen in view of Suzawa fails to teach wherein the high temperature oxide layer forms a rim extending out of the recess. Kim (see, e.g., 3A ), in a similar device to Chen in view of Suzawa , teaches an oxide layer ( e.g., gate oxide layer 170 ) forms a rim ( e.g., upper corner 268, note extension out of recess ) extending out of the recess ( e.g., recess fig. 3A ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the rim extension of Kim within the high temperature oxide layer of Chen in view of Suzawa , in order to alter the breakdown configuration within the oxide layer away from the gate trench/recess area, increasing the efficiency and reliability of the device (see, e.g., paragraph 73 of Kim). Regarding claim 11, Kim (see, e.g., fig. 3A) teaches wherein the rim ( e.g., upper corner 268, note extension out of recess ) has a height of around 10 nm ( see, e.g., paragraph 75 ). With regards to the particular spacing distance claimed, i.e. 40 to 60 angstroms, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller , 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Kim teaches a rim length above the recess of around 100 angstroms (note that 10 nm is equivalent to 100 angstroms), it would have been obvious to one of ordinary skill in the art at the time of filing the invention to slightly modify this height value of the rim past the recess of Chen in view of Suzawa further in view of Kim, to expand or isolate the corner of the gate oxide layer around the gate or device area as desired. CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed distance ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff , 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Kim and Mahajani . Regarding claim 12, Chen in view of Suzawa further in view of Kim fails to teach the rim of the high temperature oxide layer has a thickness of about 140 angstroms to about 170 angstroms. Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Suzawa , teaches a high temperature oxide layer ( e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…” ) has a thickness within the range of 140 to 170 angstroms ( see, e.g., paragraph 38 “…about 30 to 200 angstroms thick…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the rim of the high temperature oxide layer of Chen in view of Suzawa further in view of Kim , in order to achieve the expected result of providing a distinct high temperature oxide rim profile while simultaneously limiting the space required for the rim . Claim s 14 -15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Lin (US 20220302145 A1) (hereinafter Lin2) and Kim (US 20120018800 A1) (hereinafter Kim2) . Regarding claim 14 , Chen (see, e.g., figs. 3- 6 ) shows most aspects of the instant invention including a method for forming a gate oxide layer of a high voltage transistor comprising: Forming a recess ( see, e.g., formation of recess 409 in fig. 3 ) in a substrate ( e.g., 300 ); Thermally oxidizing ( see, e.g., paragraph 18 “Preferably, the first dielectric layer 410 is also formed by a second thermal oxidization process” ) exposed surfaces of a recess ( e.g., recess 409 ) to form a thermal oxide layer ( e.g., first dielectric 410 layer formed via thermal oxidization of paragraph 18 ) of the gate oxide layer ( e.g., first dielectric layer 410 ); Forming source/drain terminals ( e.g., doping regions 404 + paragraph 22 “doping region 404 can serve as the source/drain region…” ) in the substrate ( e.g., substrate 300 ) on opposite sides of the gate oxide layer ( e.g., first dielectric layer 410 ); and Forming a gate terminal ( e.g., first patterned conductive layer 411 ) above the gate oxide layer ( e.g., first dielectric layer 410 ); Forming a capping layer ( e.g., first patterned capping layer 412 ) ; Depositing a dielectric layer ( e.g., inter-layer dielectric layer 312 ) upon the capping layer ( e.g., first patterned capping layer 412 ); Planarizing ( see, e.g., paragraph 23 “…a planarization process…is performed to remove a part of the ILD layer 312…” ) the dielectric layer ( e.g., inter-layer dielectric layer 312 ); Etching back ( see, e.g., paragraph 23 “…etching-back process…is performed… completely remove the first patterned capping layer 412” ); The gate oxide layer ( e.g., first dielectric layer 410 ) comprising the thermal oxide layer ( e.g., first dielectric layer 410 ) ; Chen (see, e.g., figs. 3-4), however, fails to show performing chemical vapor deposition to form a high temperature oxide layer of the gate oxide layer upon the exposed surfaces of the thermal oxide laye r and excess high temperature oxide upon the etch stop layer , etching through the etch stop layer and into the substrate to form a recess in the substrate, etching back to remove the excess high temperature oxide layer upon the etch stop layer, and removing the etch stop layer to obtain the gate oxide layer within the recess, the gate oxide layer comprising the high temperature oxide layer. Suzawa (see, e.g., figs. 3-4), in a similar device to Chen, teaches performing chemical vapor deposition upon a thermal oxide layer ( see, e.g., paragraph 84 “…the HTO film 11 is formed by, for example, a CVD method as a first layer of the interlayer insulating film 13” ) to form a high temperature oxide layer ( e.g., HTO film 11 ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chemical vapor deposition of Suzawa onto the thermal oxide layer of Chen, in order to enhance the insulating properties within the gate oxide of the transistor. In addition, note the formation of the capping layer of Chen would reside above this newly formed HTO film , and that the gate oxide layer is now comprised of both the thermal oxide layer and the high temperature oxide layer. Chen in view of Suzawa , however, fails to teach chemical vapor deposition forms excess high temperature oxide upon the etch stop layer, forming a recess in a substrate through an etch stop layer, etching through the etch stop layer and into the substrate to form a recess in the substrate, etching back to remove the excess high temperature oxide layer upon the etch stop layer, and removing the etch stop layer to obtain the gate oxide layer within the recess, the gate oxide layer comprising the high temperature oxide layer. Lin 2 (see, e.g., fig. 4A ) , in a similar device to Chen in view of Suzawa , teaches forming a n etch stop layer ( e.g., etching stop layer 103 ) on a substrate ( e.g., dielectric layer 102 ), applying a photoresist layer ( e.g., patterned mask layer 105 + paragraph 19 “The patterned mask layer 105, includes, for example, a patterned photoresist” ) upon the etch stop layer ( e.g., etching stop layer 103 ), and etching through the etch stop layer ( e.g., etching stop layer 103 ) and intro the substrate ( e.g., dielectric layer 102 ) to form a recess ( e.g., openings OP ) in the substrate ( e.g., dielectric layer 102 ) , and removing ( see, e.g., paragraph 31 ) the etch stop layer ( e.g., etching stop layer 103 ) to obtain an oxide layer ( e.g., dielectric layer 106 + paragraph 23 “…the dielectric layer 106 includes silicon oxide…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the etch stop layer and patterned photoresist layer configuration of Lin 2 within the process of Chen in view of Suzawa , in order to achieve the expected result of improving the precision of the etching process within the recess while simultaneously providing photoresist protection during the etching step , before removing the etch stop layer to allow formation of the gate oxide layer . Chen in view of Suzawa further in view of Lin 2 , however, fails to teach chemical vapor deposition forms excess high temperature oxide upon the etch stop layer, and etching back to remove the excess high temperature oxide layer upon the etch stop layer . Kim2 (see, e.g., figs. 2C-2D), in a similar device to Chen in view of Suzawa further in view of Lin 2 , teaches chemical vapor deposition ( e.g., CVD process of paragraph 64 ) forms excess oxide ( see, e.g., paragraph 64 ), and an etching back process ( e.g., etch-back process of paragraph 64 ) removes excess oxide layer material ( see, e.g., paragraph 64 “…an etch-back process can be used to remove the excess oxide material” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the etch-back process of Kim2 within the method of Chen in view of Suzawa further in view of Lin 2 , in order to achieve the expected result of removing additional and unnecessary oxide layer material formed during the chemical vapor deposition process. In addition, note that the excess oxide material of Kim2 was formed by performing chemical vapor deposition on an oxide, a substantially similar setup of Chen in view of Suzawa further in view of Lin2. Regarding claim 15, Lin 2 (see, e.g., fig. 4A) teaches the etch stop layer ( e.g., etching stop layer 103 ) is formed from a nitride ( see, e.g., paragraph 18 “…the etching stop layer 103 includes a dielectric material, such as silicon nitride…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the nitride of Lin within the etch stop layer of Chen in view of Suzawa further in view of Lin 2 and Kim2 , because many are recognized in the semiconductor art for their usage in etch stop layers , and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Regarding claim 17, Lin 2 (see, e.g., fig. 4A) teaches an oxide layer ( e.g., dielectric layer 104 + paragraph 18 “…the materials of the dielectric layers 102 and 104 include silicon oxide…” ) over the etch stop layer ( e.g., etching stop layer 103 ) prior ( e.g., note that patterned mask layer 105 is applied on top of the already disposed dielectric layer 104 ) to applying the photoresist layer ( e.g., patterned mask layer 105 + paragraph 19 “The patterned mask layer 105, includes, for example, a patterned photoresist” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the oxide layer formation prior to photoresist formation step configuration of Lin within the process of Chen in view of Suzawa further in view of Lin and Kim2 , in order to provide a protective a layer between the photoresist and the etch stop layer during the etching process. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Lin 2 , Kim2 , and Tien (US 20220013403 A1) . Regarding claim 16, Chen in view of Suzawa further in view of Lin 2 and Kim2 fails to teach wherein the etch stop layer has a thickness of about 40 angstroms to 60 angstroms. Tien (see, e.g., fig. 18), in a similar device to Chen in view of Suzawa further in view of Lin 2 and Kim2 , teaches an etch stop layer ( e.g., first etch-stop layer 108 ) has a thickness including the range of 40 angstroms to 60 angstroms ( see, e.g., paragraph 41 “Further, a thickness of the first etch-stop layer may be about 10 to 1000 angstroms” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness range of Tien (particularly the included 40-60 angstrom range) within the etch stop layer of Chen in view of Suzawa further in view of Lin 2 and Kim2 , in order to achieve the expected result of providing a distinct etch stop layer during fabrication in the recess of the substrate while simultaneously limiting the amount of etch stop material required, reducing costs while manufacturing the device. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Lin 2 and Kim (US 20250072044 A1). Regarding claim 21, Chen (see, e.g., figs. 3-6) shows most aspects of the instant invention including a method for forming a gate oxide layer of a high voltage transistor comprising: Forming a recess ( see, e.g., formation of recess 409 in fig. 3 ) in a substrate ( e.g., 300 ); Thermally oxidizing ( see, e.g., paragraph 18 “Preferably, the first dielectric layer 410 is also formed by a second thermal oxidization process” ) exposed surfaces of a recess ( e.g., recess 409 ) to form a thermal oxide layer ( e.g., first dielectric 410 layer formed via thermal oxidization of paragraph 18 ) of the gate oxide layer ( e.g., first dielectric layer 410 ); Forming source/drain terminals ( e.g., doping regions 404 + paragraph 22 “doping region 404 can serve as the source/drain region…” ) in the substrate ( e.g., substrate 300 ) on opposite sides of the gate oxide layer ( e.g., first dielectric layer 410 ); and Forming a gate terminal ( e.g., first patterned conductive layer 411 ) above the gate oxide layer ( e.g., first dielectric layer 410 ); Forming a capping layer ( e.g., first patterned capping layer 412 ); Planarizing ( see, e.g., paragraph 23 “…a planarization process…is performed to remove a part of the ILD layer 312…” ) the dielectric layer ( e.g., inter-layer dielectric layer 312 ); The gate oxide layer ( e.g., first dielectric layer 410 ) comprising the thermal oxide layer ( e.g., first dielectric layer 410 ); Chen (see, e.g., figs. 3-4), however, fails to show performing chemical vapor deposition to form a high temperature oxide layer of the gate oxide layer upon the exposed surfaces of the thermal oxide layer, etching through the etch stop layer and into the substrate to form a recess in the substrate, etching back to remove the excess high temperature oxide layer upon the etch stop layer, and removing the etch stop layer to obtain the gate oxide layer within the recess, the gate oxide layer comprising the high temperature oxide layer. Suzawa (see, e.g., figs. 3-4), in a similar device to Chen, teaches performing chemical vapor deposition ( see, e.g., paragraph 84 “…the HTO film 11 is formed by, for example, a CVD method as a first layer of the interlayer insulating film 13” ) to form a high temperature oxide layer ( e.g., HTO film 11 ) upon exposed surfaces of an oxide layer ( e.g., insulating film 13 + paragraph 6 ) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chemical vapor deposition of Suzawa onto the thermal oxide layer of Chen, in order to enhance the insulating properties within the gate oxide of the transistor. In addition, note the formation of the capping layer of Chen would reside above this newly formed HTO film, and that the gate oxide layer is now comprised of both the thermal oxide layer and the high temperature oxide layer. Chen in view of Suzawa , however, fails to teach forming a recess in a substrate through an etch stop layer, etching through the etch stop layer and into the substrate to form a recess in the substrate, etching back to remove the excess high temperature oxide layer upon the etch stop layer, and removing the etch stop layer to obtain the gate oxide layer within the recess, the gate oxide layer comprising the high temperature oxide layer. Lin 2 (see, e.g., fig. 4A), in a similar device to Chen in view of Suzawa , teaches form ing a recess ( e.g., openings OP ) in a substrate ( e.g., dielectric layer 102 ), through an etch stop layer ( e.g., etching stop layer 103 ) and removing ( see, e.g., paragraph 31 ) the etch stop layer ( e.g., etching stop layer 103 ) to obtain an oxide layer ( e.g., dielectric layer 106 + paragraph 23 “…the dielectric layer 106 includes silicon oxide…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the etch stop layer and patterned photoresist layer configuration of Lin 2 within the process of Chen in view of Suzawa , in order to achieve the expected result of improving the precision of the etching process within the recess while simultaneously providing photoresist protection during the etching step, before removing the etch stop layer to allow formation of the gate oxide layer. In addition, it should be noted that while Lin2 does not explicitly show planarizing down to the etch stop layer in the aforementioned configuration, Chen explicitly discloses planarizing a dielectric layer down to another etch stop layer, and it would have been obvious to one of ordinary skill in the art at the time of filing the invention to perform the same planarization process here in order to provide a smooth uniform surface within the recess area. Chen in view of Suzawa further in view of Lin2, however, fails to teach wherein a rim of the high temperature oxide layer extends upwards and out of the recess. Kim (see, e.g., 3A), in a similar device to Chen in view of Suzawa , teaches an oxide layer ( e.g., gate oxide layer 170 ) forms a rim ( e.g.., upper corner 268, note extension out of recess ) extending upwards and out of the recess ( e.g., recess fig. 3A ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the rim extension of Kim within the high temperature oxide layer of Chen in view of Suzawa further in view of Lin2, in order to alter the breakdown configuration within the oxide layer away from the gate trench/recess area, increasing the efficiency and reliability of the device (see, e.g., paragraph 73 of Kim). Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Lin2, Kim, and Fujimoto. Regarding claim 22, Chen in view of Suzawa further in view of Lin2 and Kim fails to teach wherein the thermal oxide layer has a thickness of about 50 angstroms to about 80 angstroms. Fujimoto (see, e.g., fig. 6A), in a similar device to Chen in view of Suzawa further in view of Lin2 and Kim, teaches a thermal oxide layer ( e.g., thermal oxide film 12 ) has a thickness within a range of 50 to 80 angstroms ( see, e.g., paragraph 56 “…thermal oxide film 12…having a thickness of about 6-8 nm…” + note 6-8 nm is equivalent to 60 to 80 angstroms ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thermal oxide thickness profile of Fujimoto within the method of Chen in view of Suzawa further in view of Lin2 and Kim , in order to achieve the expected result of providing a distinct thermal oxide profile while simultaneously limiting the space required for the thermal oxide layer. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Suzawa further in view of Lin2, Kim, and Fujimoto. Regarding claim 23, Chen in view of Suzawa further in view of Lin2 and Kim fails to teach wherein the high temperature oxide layer has a thickness of about 140 angstroms to about 170 angstroms. Mahajani (see, e.g., fig. 3B), in a similar device to Chen in view of Suzawa , teaches a high temperature oxide layer ( e.g., blocking dielectric 100 + paragraph 38 “Blocking dielectric 100 is preferably a high temperature oxide (HTO)…” ) has a thickness within the range of 140 to 170 angstroms ( see, e.g., paragraph 38 “…about 30 to 200 angstroms thick…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the high temperature oxide thickness configuration of Mahajani within the high temperature oxide layer of Chen in view of Suzawa , in order to achieve the expected result of providing a distinct high temperature oxide profile while simultaneously limiting the space required for the layer. Allowable Subject Matter Claim 13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814