DETAILED ACTION
Response to Arguments
Applicant’s arguments, see the claim amendments filed 4/13/26, with respect to the rejection(s) of the claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made below.
Terminal Disclaimer
The terminal disclaimer filed 4/13/26 has been DISAPPROVED.
This is because the instant application number and filing date were improperly identified. Note that no new fee is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eid et al., US 11,990,448, in view of Bhagavat et al., US 10,714,462.
Regarding claim 1, Eid (figures 14-17) teaches a method for manufacturing a system-level fan-out packaging structure, comprising:
forming a rewiring layer 150 on a supporting substrate 104, wherein the rewiring layer 106 includes a first surface and a second surface opposite to the first surface, at least one inorganic (column 6, lines 24-35) dielectric layer 106, and at least one metal wiring layer 112/114/116/118 (figure 14);
forming a hybrid bonding structure 108 between the first surface of the rewiring layer 150 and semiconductor chips 102-1/102-2 to electrically couple the semiconductor chips 102-1/102-2 to the first surface of the rewiring layer 150, wherein the hybrid bonding structure 108 comprises a first bonding layer (bottom 108) formed on the first surface of the rewiring layer 150 and a second bonding layer 108 (top 108) formed on surfaces of the semiconductor chips 102-1/102-2 (figure 15);
wherein forming the first bonding layer (bottom 108) comprises disposing a first passivation layer (bottom 108) on the first surface of the rewiring layer 150; disposing vias in the first passivation layer 108 by a photolithography process and an etching process (column 10, line 65-column 11, line 2), and filling the vias with a metal layer (bottom 110) to form first pads (top surface of bottom 110); wherein the second bonding layer (top 108) comprises disposing a second passivation layer (top 108) on the semiconductor chips 102-1/102-2 and second pads (bottom surface of top 110) in the second passivation layer (top 108); wherein the first bonding layer (bottom 108) and the second bonding layer (top 108) are directly bonded (figure 15);
forming a first plastic layer 126 on the first bond layer (bottom 108) to form a packaging layer 126 to cover the semiconductor chips 102-1/102-2 (figure 16);
removing the supporting substrate 104 to expose the second surface of the rewiring layer 150 (figure 17);
forming a conductive interconnection piece 120 at the second surface of the rewiring layer 150 and attaching a packaging substrate 182 (figure 1) to the conductive interconnection piece 102, wherein the package substrate 120 is electrically coupled to the rewiring layer 150.
Eid fails to teach wherein forming the conductive interconnection piece comprises forming a controlled-collapse-chip-connection (C4) layer on the second surface of the rewiring laver, wherein the C4 layer comprises conductive posts and C4 bumps; aligning and bonding the 04 bumps to contact pads provided on the packaging substrate; and
forming a second plastic layer between the C4 laver and the packaging substrate.
Bhagavat (figure 4) teaches wherein forming the conductive interconnection piece 135/142/130 comprises forming a controlled-collapse-chip-connection (C4) layer 142/130 on the second surface of the rewiring layer 125, wherein the C4 layer 142/130 comprises conductive posts 142 and C4 bumps 130; aligning and bonding the C4 bumps 130 to contact pads (where 130 attaches to 142) provided on the packaging substrate 120; and
forming a second plastic layer 135 between the C4 layer 142/130 and the packaging substrate 120.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the conductive interconnection piece of Bhagavat in the invention of because Eid teaches it provides stress relief (column 4, lines 35-40).
With respect to claim 2, Eid (figure 14) teaches the rewiring layer 150 includes two or more (column 5, lines 43-47) inorganic (column 6, lines 24-35) dielectric layers 106 and two or more (column 5, lines 43-47) metal wiring layers 112/114/116/118, wherein the two or more inorganic dielectric layers 106 are alternately formed with the two or more metal wiring layers 112/114/116/118 in a direction perpendicular to the supporting substrate 104.
As to claim 3, though Eid (column 13, lines 37-39) fails to teach removing the supporting substrate 104 includes: thinning the supporting substrate using a mechanical grinding process, then removing the thinned supporting substrate using a chemical-mechanical polishing process, wherein the supporting substrate is a silicon-based substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this process in the invention of Eid because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In re claim 5, Eid (column 6, lines 60-64) teaches a material of the at least one metal wiring layer includes one or more of copper, aluminum, nickel, gold, silver, and titanium, and though Eid fails to teach a material of the at least one inorganic dielectric layer includes one of silicon nitride and silicon oxynitride it would have been obvious to one of ordinary skill in the art at the time of the invention to use these materials in the invention of Eid because they are conventionally known and used equivalents. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teaches the state of the art.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 5/19/26
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