DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-6, in the reply filed on 12/29/25 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 of copending Application No. 18/367477 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the reference application uses a second rewiring layer instead of a packaging substrate.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding claim 1, the reference application claims a method for manufacturing a system-level fan-out packaging structure, comprising:
forming a rewiring layer on a supporting substrate, wherein the rewiring layer includes a first surface and a second surface opposite to the first surface, at least one inorganic dielectric layer, and at least one metal wiring layer (claim 1, lines 1-5);
forming a hybrid bonding structure between the first surface of the rewiring layer and semiconductor chips to electrically couple the semiconductor chips to the first surface of the rewiring layer, wherein the hybrid bonding structure comprises a first bonding layer formed on the first surface of the rewiring layer (claim 1, lines 6-9);
forming a plastic layer on the first surface of the rewiring layer to form a packaging layer cover the semiconductor chips (claim 1, lines 10-11);
removing the supporting substrate to expose the second surface of the rewiring layer (claim 3); and
providing a packaging substrate electrically coupled to the second surface of the rewiring layer, wherein a conductive interconnection piece is arranged to be between the second surface of the rewiring layer and the packaging substrate (claim 1, lines 12-17:wherein a packaging substrate can be a rewiring layer).
With respect to claim 2, the reference application (claim 2) claims the rewiring layer includes two or more inorganic dielectric layers and two or more metal wiring layers, wherein the two or more inorganic dielectric layers are alternately formed with the two or more metal wiring layers in a direction perpendicular to the supporting substrate.
As to claim 3, the reference application (claim 3) claims removing the supporting substrate includes: thinning the supporting substrate using a mechanical grinding process, then removing the thinned supporting substrate using a chemical-mechanical polishing process, wherein the supporting substrate is a silicon-based substrate.
In re claim 4, the reference application (claim 4) claims the first bonding layer is formed on the first surface of the rewiring layer by a process of: forming a first passivation layer on the first surface of the rewiring layer; and forming vias in the first passivation layer by a photolithography process and an etching process; and filling the vias with a metal to form first pads.
Concerning claim 5, the reference application (claim 5) claims a material of the at least one inorganic dielectric layer includes one of silicon nitride and silicon oxynitride, and a material of the at least one metal wiring layer includes one or more of copper, aluminum, nickel, gold, silver, and titanium.
Pertaining to claim 6, though the reference application fails to claim forming the conductive interconnection further comprising: forming a controlled-collapse-chip-connection (C4) layer on the second surface of the rewiring layer, wherein the C4 layer comprises conductive posts and C4 bumps; and aligning and bonding the C4 bumps to contact pads provided on the packaging substrate, It would have been obvious to one of ordinary skill in the art at the time of the invention to use C4 in the invention of the reference application because C4 are conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Rejection over Chen et al., US 10,522,449
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 5 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Chen et al., US 10,522,449.
In claim 1, Chen (figures 11, 12, 14, 27, 28A & 31) A method for manufacturing a system-level fan-out packaging structure, comprising:
forming a rewiring layer 100 on a supporting substrate 20, wherein the rewiring layer (figure 11:100) includes a first surface and a second surface opposite to the first surface, at least one inorganic dielectric layer 34 (column 3, lines 28-31), and at least one metal wiring layer 26/32/36;
forming a hybrid bonding structure 66 between the first surface of the rewiring layer 100 and semiconductor chips (figure 12:68A/68B) to electrically couple the semiconductor chips (figure 12:68A/68B) to the first surface of the rewiring layer 100, wherein the hybrid bonding structure 58 comprises a first bonding layer 66/64 formed on the first surface of the rewiring layer (figures 1-4);
forming a plastic layer (figure 14:80) on the first surface of the rewiring layer 100 to form a packaging layer 80 cover the semiconductor chips 68A/68B;
removing (figure 27) the supporting substrate 20 to expose the second surface of the rewiring layer 100; and
providing a packaging substrate (figure 31:116) electrically coupled to the second surface of the rewiring layer (figure 31:bottom of 104 as relates to figure 28A-see column 12, lines 13-14), wherein a conductive interconnection piece (figure 28A:110) is arranged to be between the second surface of the rewiring layer 100 and the packaging substrate 116.
With respect to claim 2, Chen teaches the rewiring layer 100 includes two or more inorganic dielectric layers (figure 11:34/38/42) and two or more metal wiring layers (figure 11:32/36/40), wherein the two or more inorganic dielectric layers (figure 11:34/38/42) are alternately formed with the two or more metal wiring layers (figure 11:32/36/40) in a direction perpendicular to the supporting substrate 20.
As to claim 5, Chen teaches a material of the at least one inorganic dielectric layer 34 includes one of silicon nitride and silicon oxynitride (column 3, lines 28-31), and a material of the at least one metal wiring layer 40/44 includes one or more of copper, aluminum, nickel, gold, silver, and titanium (column 3, lines 62-63).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 4, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., US 10,522,449, as applied to claim 1 above.
In re claim 3. (Original) The method for manufacturing the system-level fan-out packaging structure according to claim 1, wherein removing the supporting substrate includes: thinning the supporting substrate using a mechanical grinding process, then removing the thinned supporting substrate using a chemical-mechanical polishing process, wherein the supporting substrate is a silicon-based substrate.
Concerning claim 4, Chen teaches the first bonding layer (figure 11:66/64) is formed on the first surface of the rewiring layer 100 by a process of: forming a first passivation layer 64 on the first surface of the rewiring layer 100; and forming vias (figure 11:filled by 66) in the first passivation layer 64; and filling the vias (figure 11:filled by 66) with a metal to form first pads 66, but though Chen fails to teach the vias are formed by a photolithography process and an etching process it would have been obvious to one of ordinary skill in the art at the time of the invention to use these steps in the invention of Chen because they are conventionally known and used steps. The use of conventional steps to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 6, though Chen, which teaches metal bumps, solder bumps, metal pillars, or other applicable connectors (column 11, lines 15-17) fails to teach forming the conductive interconnection further comprising: forming a controlled-collapse-chip-connection (C4) layer on the second surface of the rewiring layer, wherein the C4 layer comprises conductive posts and C4 bumps; and aligning and bonding the C4 bumps to contact pads provided on the packaging substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to use C4 layers in the invention of Chen because C4 bumps are conventionally known and used in the art equivalent “applicable connectors”. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Rejections over Yu et al., US 10,026,716
Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Yu et al., US 10,026,716.
In claim 1, Yu (figures 5, 8, 9, and 11) teaches a method for manufacturing a system-level fan-out packaging structure, comprising:
forming a rewiring layer (figure 5:24/28/26) on a supporting substrate 20, wherein the rewiring layer (figure 5:24/28/26) includes a first surface and a second surface opposite to the first surface, at least one inorganic dielectric layer (figure 5:24 & column 2, lines 57-67), and at least one metal wiring layer 26;
forming a hybrid bonding (column 5, lines 8-9) structure 31 between the first surface of the rewiring layer (figure 5:24/28/26) and semiconductor chips (figure 8:136) to electrically couple the semiconductor chips (figure 8:136) to the first surface of the rewiring layer (figure 5:24/28/26), wherein the hybrid bonding structure 31 comprises a first bonding layer 31 formed on the first surface of the rewiring layer (figure 5:24/28/26);
forming a plastic layer (figure 9:44) on the first surface of the rewiring layer (figure 5:24/28/26) to form a packaging layer (figure 9:44) cover the semiconductor chips (figure 8:136);
removing (figure 11) the supporting substrate 20 to expose the second surface of the rewiring layer (figure 5:24/28/26); and
providing a packaging substrate (column 1, lines 27-38 wherein the CoWoS method bonds the present package to a package substate) electrically coupled (figure 17 through 60) to the second surface of the rewiring layer (figure 5:24/28/26), wherein a conductive interconnection piece (figure 17:60) is arranged to be between the second surface of the rewiring layer (figure 5:24/28/26) and the packaging substrate.
Regarding claim 5, Yu teaches a material of the at least one inorganic dielectric layer 24 includes one of silicon nitride and silicon oxynitride (column 2, lines 63-67), and a material of the at least one metal wiring layer 26 includes one or more of copper (column 3, lines 1-13), aluminum, nickel, gold, silver, and titanium.
Claim(s) 2-4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al., US 10,026,716, as applied to claim 1 above.
With respect to claim 2, Yu teaches the rewiring layer (figure 5:24/28/26) includes two or more inorganic dielectric layers 24/28 and though Yu fails to teach two or more metal wiring layers, wherein the two or more inorganic dielectric layers are alternately formed with the two or more metal wiring layers in a direction perpendicular to the supporting substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to use two or more wiring layers in the invention of Yu because using two or more wiring layers is conventionally known in the art. The mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)).
As to claim 3, though Yu fails to teach removing the supporting substrate includes: thinning the supporting substrate using a mechanical grinding process, then removing the thinned supporting substrate using a chemical-mechanical polishing process, wherein the supporting substrate is a silicon-based substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this method in the invention of Yu because it is a conventionally known and used method. The use of conventional steps to perform their known functions is obvious (MPEP 2144.07).
In re claim 4, though Yu, which teaches a different method (figures 3-5), fails to teach the first bonding layer is formed on the first surface of the rewiring layer by a process of: forming a first passivation layer on the first surface of the rewiring layer; and forming vias in the first passivation layer by a photolithography process and an etching process; and filling the vias with a metal to form first pads, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this method in the invention of Yu because it is a conventionally known and used equivalent method. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Concerning claim 6, though Yu, which teaches using a solder region 60 (column 7, line 45), fails to teach forming the conductive interconnection 60 further comprising: forming a controlled-collapse-chip-connection (C4) layer on the second surface of the rewiring layer, wherein the C4 layer comprises conductive posts and C4 bumps; and aligning and bonding the C4 bumps to contact pads provided on the packaging substrate, it would have been obvious to one of ordinary skill in the art at the time of the invention to use C4 in the invention of Yu because C4 is a conventionally known and used equivalent. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach various aspects of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 2/24/26