Prosecution Insights
Last updated: August 16, 2026
Application No. 18/244,354

MULTI-PLANARITY OF LIGHT EMITTING SURFACES IN LED COMPONENTS

Non-Final OA §102
Filed
Sep 11, 2023
Examiner
CHEN, DAVID Z
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
CreeLED Inc.
OA Round
2 (Non-Final)
45%
Grant Probability
Moderate
2-3
OA Rounds
8m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
307 granted / 686 resolved
-23.2% vs TC avg
Strong +50% interview lift
Without
With
+49.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
56 currently pending
Career history
753
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
24.7%
-15.3% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 686 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This Office Action is in response to Amendments/Remarks filed on May 15, 2026. Specification [0086] appears to read 104 F. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-3, 7, and 27-28 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2011/0149600 A1 to Jang (“Jang”). As to claim 1, Jang discloses a light-emitting diode (LED) package, comprising: a housing (110, 120) that forms a recess (113); a plurality of LED chips (140) arranged within the recess (113), wherein each LED chip (140) of the plurality of LED chips (140) is pitched at a different angle relative to other LED chips (140) of the plurality of LED chips (140); and a convex molded lens (160) over the plurality of LED chips (140) and the housing (110, 120) (See Fig. 8, ¶ 0003, ¶ 0026, ¶ 0030, ¶ 0031, ¶ 0048, ¶ 0050). As to claim 2, Jang further discloses wherein LED chips (140) of the plurality of LED chips (140) are pitched away from each other such that normal angles of top surfaces of the plurality of LED chips (140) diverge (See Fig. 8, ¶ 0031). As to claim 3, Jang further discloses wherein the plurality of LED chips (140) are mounted on a submount platform (115) (See Fig. 8, ¶ 0031). As to claim 7, Jang further discloses wherein the submount platform (115) comprises a plurality of surfaces that are angled with respect to one another, and the LED chips (140) of the plurality of LED chips (140) are mounted on respective surfaces of the plurality of surfaces (See Fig. 8, ¶ 0031). As to claim 27, Jang discloses a light-emitting diode (LED) display comprising: a display panel; and at least one LED package comprising: a housing (110, 120) that forms a recess (113); a plurality of LED chips (140) arranged within the recess (113), wherein each LED chip (140) of the plurality of LED chips (140) is pitched at a different angle relative to other LED chips (140) of the plurality of LED chips (140); and a convex molded lens (160) over the plurality of LED chips (140) and the housing (110, 120) (See Fig. 8, ¶ 0003, ¶ 0026, ¶ 0030, ¶ 0031, ¶ 0048, ¶ 0050). As to claim 28, Jang further discloses wherein LED chips (140) of the plurality of LED chips (140) are pitched away from each other such that normal angles of top surfaces of the plurality of LED chips (140) do diverge (See Fig. 8, ¶ 0031). Response to Arguments Applicant's arguments with respect to claims 1 and 27 have been considered but are moot in view of the new ground(s) of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Sep 11, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection mailed — §102
May 15, 2026
Response Filed
Jun 11, 2026
Final Rejection mailed — §102
Aug 11, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707723
DISPLAY DEVICE INCLUDING CRACK DETECTING LINE
2y 2m to grant Granted Aug 11, 2026
Patent 12702055
SEMICONDUCTOR MODULE WITH BENT EXTERNAL TERMINAL
4y 2m to grant Granted Aug 04, 2026
Patent 12690229
SEMICONDUCTOR DEVICE WITH SPLIT-GATE AND METHOD FORMING THE SAME
4y 7m to grant Granted Jul 21, 2026
Patent 12684792
SEMICONDUCTOR DEVICE COMPRISING A TRANSISTOR REGION AND A CAPACITANCE ADJUSTING REGION
4y 4m to grant Granted Jul 14, 2026
Patent 12656839
DISPLAY PANEL INCLUDING CIRCUIT LAYER AND CONDUCTIVE LAYER ELECTRICALLY CONNECTED TO EACH OTHER THROUGH VIA AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY APPARATUS
5y 9m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
45%
Grant Probability
95%
With Interview (+49.9%)
3y 7m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 686 resolved cases by this examiner. Grant probability derived from career allowance rate.

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