DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/244,787, application filed on 09/11/2023. Claims 1-20 are currently pending in this application.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 01/26/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1-4, 10-13 and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Sawlani et al. (US PG Pub No. 2022/0374572).
7. With respect to independent claims 1, 12 and 17, Sawlani teaches:
receiving profile data of a plurality of features of a substrate (receive component data, para 46; see sets of data structures related to receiving component information and profiles of metrology data, para 100-115);
generating a typical profile based on the profile data of the plurality of features (see using profiles to determine performance, para 55; see inhibition profile, para 108);
generating a first array of features, wherein each of the first array of features is based on the typical profile (see array, para 27; see process features, para 26-27; see 3D array/model of semiconductor features for metrology, para 35-40, see using profiles to determine performance, para 55; see inhibition profile, para 108);
providing the first array of features to a process model (see array/model to under go semiconductor process simulation using a simulation tool, para 35-40);
obtaining first output from the process model based on the first array of features (see desired output for various system process features states, para 6; see output of process, para 32; see parameters on predicted output, para 35; see process parameters and model outputs, para 49; see outputs such as findings for new/adjusted recipes, para 63-65); and
causing performance of a corrective action in view of the first output from the process model (finding correct set of parameters, para 77; see process correction, para 79; see changing/adjusting deposition parameters or compensating for feature or process changes, para 75-80).
8. With respect to claims 2 and 16, Sawlani teaches:
receiving a microscopy image comprising the plurality of features of the substrate (see imaging methods such as microscopy image process, para 103); and
extracting the profile data of the plurality of features from the microscopy image (see process and profile data extracted, para 50-54; see extracting/determining metrology features from microscopy imaging, para 103).
9. With respect to claim 3, Sawlani teaches:
wherein generating the typical profile comprises:
representing the profile data of the plurality of features as a plurality of sets of characteristic parameters (receive component data, para 46; see sets of data structures related to receiving component information and profiles of metrology data, para 100-115); and
performing a statistical analysis to generate a set of characteristic parameters comprising the typical profile (see statistical design of experiments and analysis, para 27; see statistical methods, para 37; see statistical techniques on feature parameters, para 56; statistical relationships on parameters, para 70-75).
10. With respect to claim 4 and 13, Sawlani teaches:
wherein each feature of the first array of features comprises the typical profile (see array, para 27; see process features, para 26-27; see 3D array/model of semiconductor features for metrology, para 35-40, see using profiles to determine performance, para 55; see inhibition profile, para 108).
11. With respect to claim 10, Sawlani teaches:
wherein the corrective action comprises one or more of:
scheduling maintenance of a substrate processing system, or updating a substrate processing recipe; or providing an alert to a user (see improving substrate processing recipe, para 25).
12. With respect to claim 11, Sawlani teaches:
wherein the process model comprises a physics-based deposition model (see deposition model based on physics, para 35-40).
Allowable Subject Matter
13. Claims 5-9, 14-15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
14. With respect to dependent claims 5, 14 and 18, the prior art made of record fails to teach the combination of steps recited in claims 5, 14 and 18, including the following particular combination of steps as recited in claim 5 and similarly recited in claims 14 and 18, as follows:
generating a parametric representation of the typical profile;
altering a parameter of the typical profile to generate a second profile;
generating a second array of features, wherein each of the second array of features is based on the second profile;
providing the second array of features to the process model; and
obtaining second output from the process model based on the second array of features,
wherein causing performance of the corrective action is in further view of the second output from the process model.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851