Prosecution Insights
Last updated: April 19, 2026
Application No. 18/247,077

METHOD FOR MANUFACTURING WIRING BOARD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND RESIN SHEET

Non-Final OA §102
Filed
Mar 29, 2023
Examiner
GHYKA, ALEXANDER G
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Resonac Corporation
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
97%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
1067 granted / 1278 resolved
+15.5% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
34 currently pending
Career history
1312
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
55.4%
+15.4% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
12.2%
-27.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1278 resolved cases

Office Action

§102
:30DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I (Claims 1-17) in the reply filed on 12/2/2025 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 2-4 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Yukiiri et al (US 2009/0100673). With respect to Claim 2, Yukiiri et al discloses a method for manufacturing a wiring board (Figure 18) comprising: preparing a structure body (Figure 18, 82) in which a resin sheet (Figure 18, 96 and 95, paragraph 165) sequentially including a first resin layer region (Figure 18, 96) positioned outside and a high elasticity layer region (Figure 18, 95) positioned inside with an elastic modulus higher than that of the first resin layer region (inherent as the same components are disclosed, organic resin and glass fiber) is attached onto a support body having a metal layer (Figure 25, 81) provided on a surface thereof or onto a built -in wiring layer provided on the support body; forming a recess (Figure 25, left 100, left recess) by laser (paragraph 181-183) or imprinting in the first resin layer region on a surface side of the resin sheet; forming an opening portion (Figure 25, right 100, right opening) reaching the metal layer (Figure 25, 81) on the support body from the surface of the resin sheet; and forming a wiring layer (Figure 26, 85) in the recess and the opening portion. See Figures 18-26 and corresponding text, especially paragraphs 146-186. With respect to Claim 3, Yukiiri et al discloses wherein the high elasticity layer region is formed by arranging at least one of an inorganic fiber and an organic fiber in an organic resin material. See paragraph 165. With respect to Claim 4, Yukiiri et al discloses wherein wherein the inorganic fiber is at least one of a glass fiber. See paragraph 165. Allowable Subject Matter Claims 1 and 5-17 are allowed. The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the IDS and PTO 892 forms of record. With respect to Claims 1 and 5-17, the cited prior art does not anticipate or make obvious inter alia “ forming a recess by excimer laser in a first resin layer region in which the glass cloth does not exist on a surface side of the resin sheet;” . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. AGG January 8, 2025 /ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Mar 29, 2023
Application Filed
Jan 08, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604609
DISPLAY APPARATUS HAVING A LIGHT-BLOCKING PATTERN
2y 5m to grant Granted Apr 14, 2026
Patent 12604398
SELF-HEALABLE, RECYCLABLE, AND RECONFIGURABLE WEARABLE ELECTRONICS DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12598970
TOP VIA ON SUBTRACTIVELY ETCHED CONDUCTIVE LINE
2y 5m to grant Granted Apr 07, 2026
Patent 12598958
WAFER TREATMENT METHOD
2y 5m to grant Granted Apr 07, 2026
Patent 12593661
SEMICONDUCTOR STRUCTURE WITH OVERLAY MARK, METHOD OF MANUFACTURING THE SAME, AND SYSTEM FOR MANUFACTURING THE SAME
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
97%
With Interview (+13.8%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1278 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month