Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim, US 2001/0003662.
Kim shows the invention as claimed including a semiconductor device comprising:
A first transistor (one of group of transistors 360);
A second transistor (another of group of transistors 360);
A first capacitor (one of group of capacitors 380);
A second capacitor (another of group of capacitors 380); and
A wiring 310, wherein the first transistor is electrically connected to the first capacitor (see, for example, fig. 7),
Wherein the second transistor is electrically connected to the second capacitor, wherein the wiring 330 is positioned below the first and second transistors and is electrically connected to either the first or second transistors through a conductor 330, wherein the wiring is positioned at least partially between a gate electrode of the first transistor and a gate electrode of the second transistor in a plan view (note cross section of the device shown in fig. 1 that shows in a plan or top view at least a portion of the wiring 310 is between transistors 360),
Wherein the first capacitor and second capacitor each comprise a ferroelectric layer 384, and wherein the first capacitor and the second capacitor are placed on the same plane (see paragraphs 0030-0054).
Concerning dependent claim 4, note that Kim discloses wherein the ferroelectric layer can comprise zirconium, for example (see paragraph 0054).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 8-9, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, US 2001/0003662 in view of Nishihara, US 2003/0058683.
Kim shows the invention substantially as claimed including a semiconductor device comprising:
A first transistor (one of group of transistors 360);
A second transistor (another of group of transistors 360);
A first capacitor (one of group of capacitors 380);
A second capacitor (another of group of capacitors 380); and
A wiring 310, wherein the first transistor is electrically connected to the first capacitor (see, for example, fig. 7),
Wherein the second transistor is electrically connected to the second capacitor, wherein the wiring 310 is positioned below the first and second transistors and is electrically connected to either the first or second transistors through a conductor 330, wherein the wiring is positioned at least partially between a gate electrode of the first transistor and a gate electrode of the second transistor in a plan view (note cross section of the device shown in fig. 1 that shows in a plan or top view the wiring 310 is between transistors 360),
Wherein the first capacitor and second capacitor each comprise a ferroelectric layer 384, and wherein the first capacitor and the second capacitor are placed on the same plane (see paragraphs 0030-0054).
Kim does not expressly disclose wherein the first capacitor and the second capacitor comprise a region where they overlap with each other. Nishihara discloses multiple capacitors having a common first electrode which overlaps between adjacent capacitors. In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Kim so as to comprise first and second capacitors that have an overlapping region because in such a way the space utilized on the particular substrate can be maximized.
Regarding dependent claim 8, note that in Kim the ferroelectric layer can comprise zirconium (see paragraph 0054).
With respect to dependent claim 9, Kim and Nishihara are applied as above but do not expressly disclose where the semiconductor device also includes a CPU (central processing unit). However, the examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a cpu in addition to the semiconductor device because such a construction is often characteristic of a computer.
Concerning dependent claim 14, note that the product of Kim modified by Nishihara discloses wherein the conductor is in contact with a bottom surface of the oxide semiconductor and a top surface the wiring between a gate electrode of the first transistor and a gate electrode of the second transistor.
Claim(s) 3, 6, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, US 2001/0003662 in view of Yamazaki et al., US 2012/0182790.
Kim is applied as in the rejection of claims 1 and 4 under 35 USC 102(a)(1) disclosed above but does not expressly disclose wherein each of the first and second transistors comprises an oxide semiconductor in a channel. Yamazaki et al. discloses forming an oxide semiconductor 3012 a channel (see paragraphs 0053-0056 and figs. 7D-7H). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Kim so as to comprise an oxide semiconductor channel as disclosed by Yamazaki et al. because this is shown to be a suitable and appropriate channel material for thin film transistors.
With respect to dependent claim 6, note the combination of Kim and Yamazaki et al. also disclose wherein the first transistor and the second transistor comprise an oxide semiconductor overlapping with the wiring.
Concerning dependent claim 13, note that the product of Kim modified by Yamazaki et al. discloses wherein the conductor is in contact with a bottom surface of the oxide semiconductor and a top surface the wiring between a gate electrode of the first transistor and a gate electrode of the second transistor.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, US 2001/0003662.
Kim is applied as above but does not expressly disclose where the semiconductor device also includes a CPU (central processing unit). However, the examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a CPU in addition to the semiconductor device because such a construction is often characteristic of a computer.
Claim(s) 7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, US 2001/0003662 in view of Nishihara, US 2003/0058683 as applied to claims 2 and 8-9 above, and further in view of Yamazaki et al., US 2012/0182790.
Kim and Nishihara are applied as above but do not expressly disclose wherein each of the first and second transistors comprises an oxide semiconductor in a channel. Yamazaki et al. discloses forming an oxide semiconductor 3012 a channel (see paragraphs 0053-0056 and figs. 7D-7H). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the reference of Kim modified by Nishihara so as to comprise an oxide semiconductor channel as disclosed by Yamazaki et al. because this is shown to be a suitable and appropriate channel material for thin film transistors.
With respect to dependent claim 10, note the combination of Kim and Yamazaki et al. also disclose wherein the first transistor and the second transistor comprise an oxide semiconductor overlapping with the wiring.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, US 2001/0003662 in view of Higuchi et al., US 2002/0154554.
Kim is applied as above but does not express disclose wherein the ferroelectric layer comprises an orthorhombic crystal structure. Higuchi et al. discloses a ferroelectric layer which is part of a ferroelectric capacitor and comprises an orthorhombic crystal structure. In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Kim so as to have a ferroelectric layer with an orthorhombic crystal structure because
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, US 2001/0003662 in view of Nishihara, US 2003/0058683 as applied to claims 2 and 8-9 above, and further in view of Higuchi et al., US 2002/0154554.
Kim and Nishihara is applied as above but does not express disclose wherein the ferroelectric layer comprises an orthorhombic crystal structure. Higuchi et al. discloses a ferroelectric layer which is part of a ferroelectric capacitor and comprises an orthorhombic crystal structure. In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Kim modified by Nishihara so as to have a ferroelectric layer with an orthorhombic crystal structure because
Response to Arguments
Applicant's arguments filed 04/06/26 have been fully considered but they are not persuasive. Applicant argues that the reference fails to disclose “the wiring is positioned below the first transistor and the second transistor and is electrically connected to the first transistor or the second transistor through a conductor”. However, as cited in the above rejections, Kim discloses wherein “the wiring is positioned below the first transistor and the second transistor and is electrically connected to the first transistor or the second transistor through a conductor”. For at least these reasons, the rejections as stated above are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
June 1, 2026
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