Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
This is a response to the election filed on 8/10/2026.
The Examiner acknowledges the election of group I (Claims 1-12), without traverse.
Thus, claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non- elected claim.
Claim Objection
In claim 6, “workload manager” should be changed to “the workload manager”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
In claim 1, the limitation “environment” in emulation environment, as presented is non-statutory and not patent eligible because the limitation environment does not fall within any one of the four statutories of invention recited in USC § 101: process, machine, manufacture and composition of
matter. The latter three categories define "things" or "products" while a process consists of a series of steps or act to be performed (See MPEP 2106.IV.B; Determine Whether the Claimed Invention Falls Within an enumerated Statutory)
Claim 2-12 are rejected because they depend directly or indirectly from claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected because “policy” in scheduling policy, as presented is unclear regarding
Policy by/from what/where.
The Applicant is claiming " scheduling policy " without proper documents
regarding the claimed "scheduling policy "
Policy " just an intended use and/or a subject matter of a company/ customer/ client / user/ product/ procedure policy, having no significant patentable weight and should not be used in the claim language.
Claims 2-12 are rejected because they depend directly or indirectly from claim 1.
Claims 4-5 are rejected because “the application handler” lacks antecedent basis. Claims 4-5 depend from claim 2 and claim 2 does not recite any application handler to provide antecedent basis for “the application handler” in claims 4-5.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, and 7-10 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Sailet (US 2020/0379803)
Regarding claim 1 , the prior art discloses:
An emulation environment for heterogeneous system-on-chip (SoC) design (simulation/test (fig 5) computing resources such as CPU, memory, cache, hardware/ circuitry, processor (par 1, 73)), comprising:
a workload manager (par 2, 4, 41, 44, fig 8) configured to schedule application tasks onto heterogeneous processing elements (PEs) in a heterogeneous SoC based on a scheduling policy (fig 2-5, 8 and related text discloses scheduling/ re-scheduling (fig 2-5, 8) tasks /jobs/ workload/ workflow / application onto processing elements such as CPU, memory, cache, hardware/ circuitry, processor (par 1, 73) ); and
a resource manager configured to simulate a test hardware configuration using the heterogeneous PEs and execute the application tasks scheduled by the workload manager (summary, par 41-45, fig 1-2 and related text discloses simulating tasks /jobs/ workload/ workflow /application scheduled by workload manager).
(Claim 2) wherein the application tasks comprise heterogeneous application tasks (each computing resource to execute each workflow in a queue,
different workflows may utilize computing resources, execution order of the workflows in the queue based on the available amount of each of the multiple computing resources, different variations usage of each computing resource
(abstract, par 9, 18, 64))
(Claim 3) an application handler configured to generate a workload comprising the application tasks (fig 1-5).
(Claim 7) wherein the workload manager comprises: an application tracker configured to track application tasks for each of a plurality of applications (monitor/ determine/ simulating availability / usage of computing resources (par 2, 8, 11, 18 and/or fig 1-5 and related text)); a resource tracker configured to track availability of the heterogeneous PEs; and a modular scheduler configured to provide the scheduling policy (monitor/ determine/ simulating availability / usage of computing resources (par 2, 8, 11, 18 and/or fig 1-5 and related text))
(Claim 8) wherein the modular scheduler is further configured to map the application tasks to corresponding PEs based on the availability of the heterogeneous Pes (monitor/ determine/ simulating availability / usage of computing resources (par 2, 8, 11, 18 and/or fig 1-5 and related text))
(Claims 9-10) wherein the resource manager is further configured to:
dispatch to hardware resources via application threads (fi 1-3, 5 and related text); coordinate data flow between the hardware resources during simulation (background/summary or fig 1-2, 4-5 and related text).
Claims 1-12 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Ashwathnarayan (US 20200364088)
Regarding claim 1 , the prior art discloses:
An emulation environment for heterogeneous system-on-chip (SoC) design (see design/simulation/emulation (par 163, 238-247, 473, 531-532, 539, 680) heterogeneous processing cores/components/elements (title, fig 18, 23-28)), comprising:
a workload manager configured to schedule (fig 17, 25, 28, 40-41, 43) application tasks onto heterogeneous processing elements (PEs) in a heterogeneous SoC (heterogeneous processing cores/components/elements (title, fig 18, 23-28)) based on a scheduling policy (fig 17, 28, 40-41, 43) ; and
a resource manager (fig 17, par 195, 198) configured to simulate (par 246, 305, 539, 680) a test hardware configuration using the heterogeneous PEs ( heterogeneous processing cores/components/elements (title, fig 18, 23-28)) and execute the application tasks scheduled by the workload manager (fig 17, 25 28, 40-41, 43 and related text)
(Claim 2) wherein the application tasks comprise heterogeneous application tasks (i.e., task running on hardware (par 61) different threads and process and on different hardware (par 115), DAG 1202 allows applications to describe their workflows across different hardware (par 158, 183), processor cores 3407 may each process a different instruction set (par 473), a number of hardware units for processing tasks (par 552), dispatching instructions from plurality of different cooperative groups to various functional units (e.g., processing core (par 566))
(Claim 3) an application handler configured to generate a workload comprising the application tasks (par 69, 80, 87, 91-93, 163-164 and/or fig 1-2, 7-8, 10 and related text).
(Claim 4) wherein the application handler is further configured to generate workloads for different applications from hardware- agnostic application code (par 91, 163).
(Claim 5) wherein the application handler is further configured to receive an application code in form of a directed acyclic graph (DAG) for the application tasks; and a binary compilation of the application (fig 12).
(Claim 6) workload manager is further configured to receive the DAG from the application handler and manage dependencies (par 62, 64, 72, 117, 142-143, 145, 153, 158-163, 456) between the application tasks.
(Claim 7) wherein the workload manager comprises: an application tracker configured to track application tasks for each of a plurality of applications (par 61, 64-65, 117, 130, 156, 234-235, 513, 545-546, 565, 582); a resource tracker configured to track availability of the heterogeneous Pes (see idle / available / free (par 80, 95, 110, 195, 229, 235, 256, 260, 309, 365, 417, 441, 449, 496, 513, 563, 591-593)) ; and a modular scheduler ((fig 17, 28, 40-41, 43) configured to provide the scheduling policy.
(Claim 8) wherein the modular scheduler is further configured to map (par 80, 95, 110, 195, 417, 563) the application tasks to corresponding PEs based on the availability of the heterogeneous PEs.
(Claims 9-10) wherein the resource manager is further configured to:
dispatch to hardware resources via application threads (fig 25-26, 28, 36-39);
coordinate data flow between the hardware resources during simulation (see one or more of fig 4, 7-14, 18, 34-44 and related text).
(Claim 11-12) wherein the heterogeneous PEs of the heterogeneous SoC comprises one or more general processor clusters (fig 18, 23, 28-29, 41) and one or more hardware accelerator clusters (fig 18, 23, 29 );
wherein the one or more hardware accelerator clusters comprises at least one of: a cluster of matrix multipliers, a cluster of Viterbi decoders, a cluster of fast Fourier transform (FFT) accelerators, a cluster of graphical processing units (GPUs), a cluster of digital signal processors (DSPs), or a cluster of tensor processing units (see at least one of fig 2, 15, 18-20, 23, 26, 28-29, 31-34, 40, 43 or 45 and related text)
Claims 1-12 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Crabtree (US 2026/0046317)
Regarding claim 1 , the prior art discloses:
An emulation environment for heterogeneous system-on-chip (SoC) design (see simulate (fig 2, par 697, 856, 920-921, 930, 934-936, 957, 1044, 1048, 1180, 1185, 1193) heterogeneous devices such as CPU, GPU , TPU, memory, tensor cores, heterogeneous compute/ accelerators/nodes / platforms/ workload, heterogeneous processing elements (abstract, background, summary, par 76, 81, 84, 120 844, 852, 981, 991, 1034, 1037)), comprising:
a workload manager configured to schedule application tasks onto heterogeneous processing elements (PEs) in a heterogeneous SoC based on a scheduling policy (schedule in fig 3-4, heterogeneous PEs are heterogeneous devices such as CPU, GPU , TPU, memory, tensor cores, heterogeneous accelerators/compute/nodes /platforms/ workload , heterogeneous processing elements (abstract, background, summary, par 76, 81, 84, 120, 844, 852, 981, 991, 1024, 1037 )); and
a resource manager configured to simulate (simulation in fig 2, 11) a test hardware configuration using the heterogeneous PEs , heterogeneous PEs are heterogeneous devices such as CPU, GPU , TPU, memory, tensor cores, heterogeneous accelerators/compute/nodes /platforms/ workload , heterogeneous processing elements (abstract, background, summary, par 76, 81, 84, 120, 844, 852, 981, 991, 1024, 1037 )) and execute the application tasks scheduled by the workload manager.
(Claim 2) wherein the application tasks comprise heterogeneous application tasks (par 76, 78, 84, 120)
(Claim 3) an application handler (par 85, 522, 546, 943, 948, 1045, 1122) configured to generate a workload comprising the application tasks.
(Claim 4) wherein the application handler (par 85, 522, 546, 943, 948, 1045, 1122) configured is further configured to generate workloads for different applications from hardware- agnostic application code (par 172, 426, 534, 502, 624, 712, 732, 767, 1045).
(Claim 5) wherein the application handler (par 85, 522, 546, 943, 948, 1045, 1122) is further configured to receive an application code in form of a directed acyclic graph (par 251, 1043, 1085) for the application tasks; and a binary compilation of the application (par 267, 270, 306, 455, 529, 599 , 1152-1153)
(Claim 6) workload manager is further configured to receive the DAG (par 251, 1043, 1085) from the application handler (par 85, 522, 546, 943, 948, 1045, 1122) and manage dependencies (par 120, 211, 765, 939, 988, 1043, 1085, 1119, 1195, 1199) between the application tasks.
(Claim 7) wherein the workload manager comprises: an application tracker configured to track application tasks for each of a plurality of applications (par 120, 129, 159, 521, 527, 528, 538, 544); a resource tracker configured to track availability (par 544, 555, 557, 565-570, 913, 927) of the heterogeneous PEs; and a modular scheduler configured to provide the scheduling policy (par 86-90, 130-131, 274, fig 3-4).
(Claim 8) wherein the modular scheduler (par 86-90, 130-131, 274, fig 3-4).is further configured to map the application tasks to corresponding PEs based on the availability (par 544, 555, 557, 565-570, 913, 927) of the heterogeneous PEs.
(Claims 9-10) wherein the resource manager is further configured to:
Dispatch (par 251, 280-281, 545, 549, 558, 974, 1068, 1113, 1119) to hardware resources via application threads (1040, 1043, 1045);
coordinate data flow between the hardware resources during simulation (abstract, background, summary).
(Claim 11-12) wherein the heterogeneous PEs of the heterogeneous SoC comprises one or more general processor clusters (par 77, 79, 200,217, 222, 491, 845 summary) and one or more hardware accelerator clusters ((par 77, 79, 200,217, 222, 491, 845 summary));
wherein the one or more hardware accelerator clusters comprises at least one of: a cluster of matrix multipliers, a cluster of Viterbi decoders, a cluster of fast Fourier transform (FFT) accelerators, a cluster of graphical processing units (GPUs), a cluster of digital signal processors (DSPs), or a cluster of tensor processing units (see one or more of par 200, 217, 222, 845, 852, 995, 1009, 1025 or 1162)
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/Primary Examiner, Art Unit 2851
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