DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 21 Apr 2023 for application number 18/250,128. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-39 are presented for examination – elected claims 1-22 and 38-39 are examined below; non-elected claims 23-37 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 21 Apr 2023, 14 Jan 2025, and 31 Jul 2025 were filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of Group I., Embodiment I., as shown in Figs. 1-33 (claims 1-22 and 38-39 are readable thereon) in the reply filed on 12 Jan 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Non-elected claims 23-37 have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-21, and 38-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege et al. [hereinafter as Simsek] (US 2022/0029015 A1) in view of Zhu (US 2018/0096896 A1 – as cited in IDS filed 14 Jan 2025).
In reference to claim 1, Simsek teaches A semiconductor apparatus, comprising:
a plurality of device stacks [stacked vertical transistors 102 (two stacks are pictured in Fig. 1B); Fig. 1B, paras 0027-0028], wherein each device stack comprises a plurality of semiconductor devices [102] that are stacked, and each semiconductor device [102] comprises a first source/drain layer [source/drain in channel region 104; Fig. 1B-C, para 0030], a channel layer [104], and a second source/drain layer [source/drain in channel region 104] that are stacked in a vertical direction [Y-direction; Fig. 1B], and a gate electrode [gate electrode 114/117a/117b; para 0048] surrounding the channel layer [104]; and
However, Simsek does not explicitly teach:
an interconnection structure disposed between the plurality of device stacks,
wherein the interconnection structure comprises:
an electrical isolation layer; and
a conductive structure in the electrical isolation layer, and
wherein at least one of the first source/drain layer, the second source/drain layer, and the gate electrode of each of at least one of the semiconductor devices is in contact with and thus electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.
Simsek and Zhu teach:
an interconnection structure [first gate conductor layer 1031, electrical contact layer 1037, gate conductor layer 1047 and electrical contacts 1051; Fig. 24, paras 0059, 0065, 0071 of Zhu] disposed between the plurality of device stacks [stacked vertical transistors 102 of Simsek],
wherein the interconnection structure comprises:
an electrical isolation layer [first isolation layer 1027, second isolation layer 1033, third isolation layer 1041, fourth isolation layer 1043; Fig. 24, paras 0057, 0064, 0068, 0070 of Zhu]; and
a conductive structure [1031/1037/1047/1051 of Zhu] in the electrical isolation layer [1027/1033/1041/1043 of Zhu], and
wherein at least one of the first source/drain layer [source/drain in channel region 104 of Simsek; analogously, first source/drain layer 1003 of Zhu; Fig. 24, para 0029], the second source/drain layer [source/drain in channel region 104 of Simsek; analogously, second source/drain layer 1007 of Zhu; Fig. 24, para 0029], and the gate electrode [114 of Simsek] of each of at least one of the semiconductor devices [102 of Simsek] is in contact with and thus electrically connected to the conductive structure [1031/1037/1047/1051 of Zhu] at a corresponding height in the interconnection structure [1031/1037/1047 of Zhu] in a lateral direction [1031/1037/1047 of Zhu connected laterally].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Simsek and Zhu before the effective filing date of the claimed invention, to include the interconnection structure as disclosed by Zhu into the semiconductor device of Simsek in order to obtain an interconnect structure between vertically stacked semiconductor devices.
One of ordinary skill in the art would be motivated to obtain an interconnect structure between vertically stacked semiconductor devices to provide the predictable result of making easy electrical contacts with semiconductor structures [Zhu, para 0074].
In reference to claim 2, Simsek and Zhu teach the invention of claim 1.
Simsek teaches The semiconductor apparatus according to claim 1, further comprising a device isolation layer [electrically insulative material 118; Fig. 1B, para 0043] between at least one pair of semiconductor devices [102] adjacent in the vertical direction [Y-direction].
In reference to claim 3, Simsek and Zhu teach the invention of claim 1.
Zhu teaches The semiconductor apparatus according to claim 1, wherein the channel layer comprises a single crystal semiconductor material [para 0016 discloses that the channel layer may be made of single crystal semiconductor material].
In reference to claim 4, Simsek and Zhu teach the invention of claim 1.
Zhu teaches The semiconductor apparatus according to claim 1, wherein each of the first source/drain layer and the second source/drain layer comprises a single crystal semiconductor material [para 0016 discloses that the source/drain regions may be made of single crystal semiconductor material].
In reference to claim 5, Simsek and Zhu teach the invention of claim 2.
Simsek teaches The semiconductor apparatus according to claim 2, wherein a thickness of the device isolation layer [118] is substantially uniform [thickness of 118 is uniform; Fig. 1B] in the device stack, and the thickness of the device isolation layer [118] is less than a thickness of the channel layer [thickness of 118 is less than thickness of 104 (essentially 102)].
In reference to claim 6, Simsek and Zhu teach the invention of claim 2.
Simsek teaches The semiconductor apparatus according to claim 2, wherein the device isolation layers [118] at a corresponding height in different device stacks [102 of different stacks] are substantially coplanar with each other [the 118 in adjacent stacks are coplanar; Fig. 1B].
In reference to claim 7, Simsek and Zhu teach the invention of claim 2.
Simsek teaches The semiconductor apparatus according to claim 2, wherein the device isolation layer comprises an oxide, a nitride, SiC, or a combination thereof [para 0043 discloses that 118 and gate dielectric material 116 may be the same material; para 0044 discloses that 116 may be an oxide, a nitride, silicon carbon nitride, etc.].
In reference to claim 8, Simsek and Zhu teach the invention of claim 2.
Simsek and Zhu teach The semiconductor apparatus according to claim 2, wherein an interface [the combination of Simsek and Zhu would provide an interface for 118 of Simsek and 1027/1033/1041/1043 of Zhu] is provided between the device isolation layer [118 of Simsek] and the electrical isolation layer [1027/1033/1041/1043 of Zhu].
In reference to claim 9, Simsek and Zhu teach the invention of claim 1.
Simsek teaches The semiconductor apparatus according to claim 1, wherein the channel layers [104] of the semiconductor devices in a same device stack are substantially coplanar with each other [the 104 in adjacent stacks are coplanar; Fig. 1B].
In reference to claim 10, Simsek and Zhu teach the invention of claim 1.
Simsek teaches The semiconductor apparatus according to claim 1, wherein the first source/drain layer [source/drain in channel region 104] and the second source/drain layer [source/drain in channel region 104] of each semiconductor device in at least one or more of the device stacks [stacked vertical transistors 102] are substantially rectangular or zigzag in a top view [Fig. 1A shows a rectangular structure in a top view].
In reference to claim 11, Simsek and Zhu teach the invention of claim 1.
Simsek teaches The semiconductor apparatus according to claim 1, wherein a sidewall of the gate electrode [114/117a/117b] of each semiconductor device [102] in at least one of the device stacks [stacks of 102], which is on a first side [on side of 102 in which 114/117a/117b is], is covered by a first sidewall isolation layer [gate dielectric material 116 on in which 114/117a/117b is; Fig. 1B, para 0037], while sidewalls [side of 102 where source/drain in channel region 104 is, but not “the first side”] of the first source/drain layer [source/drain in channel region 104] and the second source/drain layer [source/drain in channel region 104], which are on a second side different from the first side [the sides are different as expressed above], are covered by a second sidewall isolation layer [116 on “the second side”].
In reference to claim 12, Simsek and Zhu teach the invention of claim 11.
Simsek teaches The semiconductor apparatus according to claim 11, wherein the first sidewall isolation layers [116 on first side] in a same device stack are substantially coplanar with each other, and the second sidewall isolation layers [116 on second side] in the same device stack are substantially coplanar with each other [116 are coplanar due to vertically stacked nature of devices; Fig. 1B].
In reference to claim 13, Simsek and Zhu teach the invention of claim 11.
Simsek and Zhu teach The semiconductor apparatus according to claim 11, wherein an interface [the combination of Simsek and Zhu would teach an interface of these structures] is provided between the first sidewall isolation layer [116 on first side of Simsek] and the electrical isolation layer [1027/1033/1041/1043 of Zhu], and an interface [the combination of Simsek and Zhu would teach an interface of these structures] is provided between the second sidewall isolation layer [116 on second side] and the electrical isolation layer [1027/1033/1041/1043 of Zhu].
In reference to claim 14, Simsek and Zhu teach the invention of claim 11.
Simsek and Zhu teach The semiconductor apparatus according to claim 11, wherein the gate electrode [114 of Simsek] is connected, on the second side, to a corresponding conductive structure [1031/1037/1047/1051 of Zhu] in the interconnection structure, and the first source/drain layer [source/drain in channel region 104 of Simsek] and the second source/drain layer [source/drain in channel region 104 of Simsek] are connected, on the first side, to corresponding conductive structures [1031/1037/1047/1051 of Zhu] in the interconnection structure [the combination of Simsek and Zhu would teach the connections of the structures as claimed].
In reference to claim 15, Simsek and Zhu teach the invention of claim 1.
Zhu teaches The semiconductor apparatus according to claim 1, wherein the conductive structure [1031/1037/1047/1051] comprises at least one of an interconnection line [one of 1031/1037/1047] and a via hole [holes in which electrical contacts 1051-1 to 1051-5 are made; Fig. 24, para 00073].
In reference to claim 16, Simsek and Zhu teach the invention of claim 15.
Zhu teaches The semiconductor apparatus according to claim 15, wherein the conductive structure [1031/1037/1047/1051] comprises an interconnection line layer [layers in which one of 1031/1037/1047 are present] and a via hole layer [layers in which holes, in which electrical contacts 1051-1 to 1051-5 are made, are present] that are disposed alternately [these are disposed alternately; Fig. 24], wherein the interconnection line [one of 1031/1037/1047] is provided in the interconnection line layer [layers in which one of 1031/1037/1047 are present], and the via hole [holes in which electrical contacts 1051-1 to 1051-5 are made; Fig. 24, para 0073] is provided in the via hole layer [layers in which holes, in which electrical contacts 1051-1 to 1051-5 are made, are present].
In reference to claim 17, Simsek and Zhu teach the invention of claim 1.
Zhu teaches The semiconductor apparatus according to claim 1, wherein the conductive structure [1031/1037/1047] comprises at least one of metal elements W, Co, Ru, Cu, Al, Ti, Ni and Ta [para 0059 discloses that 1031 may be a metal gate conductor; para 0065 discloses that 1037 may be metal such as W; 1047 is also a gate conductor layer; it would have been obvious of one of ordinary skill in the art for 1031, 1037, and 1047 be made of W or another conductive metal, as required by the claim].
In reference to claim 18, Simsek and Zhu teach the invention of claim 1.
Simsek and Zhu teach The semiconductor apparatus according to claim 1, wherein the interconnection structure [1031/1037/1047 of Zhu] surrounds [the combination of Simsek and Zhu would teach that the interconnection surrounds the semiconductor devices] at least one of the semiconductor devices [102 of Simsek].
In reference to claim 19, Simsek and Zhu teach the invention of claim 1.
Simsek and Zhu teach The semiconductor apparatus according to claim 1, wherein an interface [the combination of Simsek and Zhu would teach an interface of these structures] is provided between the conductive structure [1031/1037/1047/1051 of Zhu] in the interconnection structure and the device stack [stacked vertical transistors 102 of Simsek].
In reference to claim 20, Simsek and Zhu teach the invention of claim 1.
Simsek and Zhu teach The semiconductor apparatus according to claim 1, wherein an interface [the combination of Simsek and Zhu would teach an interface of these structures] is provided between the electrical isolation layer [1027/1033/1041/1043 of Zhu] in the interconnection structure [1031/1037/1047 of Zhu] and the device stack [stacked vertical transistors 102 of Simsek].
In reference to claim 21, Simsek and Zhu teach the invention of claim 8.
Simsek and Zhu teach The semiconductor apparatus according to claim 8, wherein at least two of the interfaces at different heights are substantially coplanar with each other [the combination of Simsek and Zhu would provide an interface for 118 of Simsek and 1027/1033/1041/1043 of Zhu; because of the vertically stacked nature, interfaces would be coplanar at different heights].
In reference to claim 38, Simsek and Zhu teach the invention of claim 1.
Simsek teaches An electronic device comprising the semiconductor apparatus according to claim 1 [para 0097 discloses various electronic devices].
In reference to claim 39, Simsek and Zhu teach the invention of claim 38.
Simsek teaches The electronic device according to claim 38, wherein the electronic device comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply [para 0097 discloses various electronic devices as similarly claimed].
Allowable Subject Matter
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. While Simsek and Zhu teach the invention of claim 1, the prior art does not teach the invention of claim 1, including these limitations of claim 22, “wherein the interconnection structure comprises a dummy conductive structure, and a minimum gap between conductive structures in a same layer, a minimum gap between the conductive structure and the dummy conductive structure in the same layer, and a minimum gap between dummy conductive structures in the same layer remain substantially consistent with each other in the layer.”
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Yu et al. (US-20210091207-A1) discloses vertically stacked semiconductor devices [Fig. 17A].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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