Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-5 in the reply filed on 02/10/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Or-Back (Pub. No.: US 2026/0075821).
Re claim 1, Or-Back, Figs. 3A-3P teaches a high-density three-dimensional memory device with interconnection of low resistance, comprising an underlying circuit part, and a base structure disposed on the underlying circuit part, wherein the base structure comprises first conductive medium layers and insulating medium layers which are alternately stacked on each other from bottom to top;
the base structure has dendritic interdigitated structure, wherein the dendritic interdigitated structure is composed of two dendritic structures (324/326, Fig. 3E, ¶ [0175]), and a curved division trench is formed between the two dendritic structures;
each dendritic structure comprises at least one trunk (384, Fig. 3P, and branches connected to and perpendicular to the trunk, and at least three branches (385/386) are disposed on at least one side of both sides of the trunk;
a preset number of memory holes (memory cells, Fig. 3F) are formed in the curved division trench, an upper opening of each memory hole is located on a plane where the top face of the base structure is located, a lower opening of each memory hole (the circles intersected between bit line and word lines, Figs. 3H-3I) is located on a plane where the bottom face of the base structure is located, the memory holes are independent of one another, and the adjacent memory holes are isolated from each other by an insulating material;
a vertical electrode (Memory Cell Gates) perpendicular to the bottom face of the base structure is disposed in the memory hole, and a storage medium required for a preset memory device is provided between the vertical electrode and an inner wall of the memory hole.
Re claim 2, Or-Back, Figs. 3A-3P teaches the high-density three-dimensional memory device with interconnection of low resistance according to claim 1, wherein at least two memory holes (the circles intersected between bit line and word lines, Figs. 3H-3I) are formed in each middle division region, and the middle division region is a part, parallel to the pointing of the branch, of the curved division trench.
Re claim 3, Or-Back, Fig. 4A teaches the high-density three three-dimensional memory device with interconnection of low resistance according to claim 1, wherein the first conductive medium (402/406), the storage medium (Charge storage layer) and the electrode (Gate) are made of materials required to constitute a semiconductor memory.
Re claim 4, Or-Back, Fig. 4A teaches the high-density three-dimensional memory device with interconnection of low resistance according to claim 1, wherein the first conductive medium is made of a semiconductor material (402/406, [0188]).
Re claim 5, Or-Back, in different embodiment, Fig. 69D teaches the high-density three-dimensional memory device with interconnection of low resistance according to claim 1, wherein the preset memory is a PN junction type semiconductor memory (6946/6956, [0472]), a Schottky diode memory or a medium memory; the medium memory is a resistance change memory (6902), a magnetic phase change memory, a phase change memory, or a ferroelectric memory.
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2893
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