DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 18 November 2025 was filed after the mailing date of the first Office Action on 4 September 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Office acknowledges receipt on 3 December 2025 of Applicants’ amendments in which the drawings, specification, and claims 1 and 10 are amended and claim 7 is cancelled. The Office withdraws the drawing objections, specification objection, and indefiniteness rejections identified in the Office Communication dated 4 September 2025 in view of the amendments.
Response to Arguments
Applicants’ arguments with respect to independent claim(s) 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Darwish et al. (US20210175348A1) in view of Chen (US20110133258A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Darwish teaches in Fig. 4A a semiconductor device, comprising:
a base (107, 109, 113, 115, 421, 433), wherein a first surface (top surface) of the base (107, 109, 113, 115, 421, 433) is provided with a first trench (center trench) and a second trench (left/right trench) {¶0035, 0037, 0038, 0049};
a gate electrode (423A), provided in the first trench (center trench) {¶0049};
a gate insulation isolation structure (421, 433), provided in the first trench (center trench), wherein the gate insulation isolation structure (421, 433) covers the gate electrode (423A) at a bottom, sides, and a top {¶0049};
a source doped region(115) with a first conductivity type (n-type), provided in the base (107, 109, 113, 115, 421, 433), on both sides of the first trench (center trench) and on both sides of the second trench (left/right trench) {¶0037};
a trench conductive structure (131), provided in the second trench (left/right trench) {¶0049};
a source electrode (103), provided on the trench conductive structure (131) and the source doped region (115), and electrically connected to the trench conductive structure (131) and the source doped region (115) {¶0043}; and
a drain electrode (101), provided on a second surface (bottom surface) of the base (107, 109, 113, 115, 421, 433), wherein the first surface (top surface) and the second surface are opposite (bottom surface) {¶0042}.
Darwish does not teach a top of the gate insulation isolation structure is lower than a top of the source doped region, and the source electrode extends into an upper part of the first trench and directly contacts with sides of the source doped region, wherein a material of the source electrode includes conductive metal, alloy, or both.
In an analogous art, Chen teaches in Figs. 26A-C and paragraph [0044] a top of a gate insulation isolation structure (3309, 3324, and/or 3326) is lower than a top of a source doped region (3332), and a source electrode (3334) extends into an upper part of a first trench (trench housing 3326, 3320, etc.) and directly contacts with sides of the source doped region (3332), wherein a material of the source electrode (3334) includes conductive metal, alloy, or both. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s semiconductor device based on the teachings of Chen, to achieve the above-identified subject matter, for: (1) [i]ncreased source-metal contact areas lead[ing] to reduced contact resistance and more stable transient response, (2) increased area mean[ing] that it is less likely that the contact would be defective, and (3) more reliable devices and higher manufacturing yields. Chen ¶0044.
Regarding claim 2, Darwish as modified by Chen teaches the semiconductor device according to claim 1, and Darwish further teaches further comprising:
a second-conductivity-type doped region (435A), provided in the base (107, 109, 113, 115, 421, 433) and at a bottom of the first trench (center trench) and/or the second trench (left/right trench), wherein the first conductivity type (n-type) and the second conductivity type (p-type) are opposite {¶0049}.
Regarding claim 3, Darwish as modified by Chen teaches the semiconductor device according to claim 2, and Darwish further teaches further comprising:
a second-conductivity-type well region (113), provided in the base (107, 109, 113, 115, 421, 433), wherein the source doped region (115) is in the second-conductivity-type well region (113), and both a depth of the first trench (center trench) and a depth of the second trench (left/right trench) are greater than a depth of the second-conductivity-type well region (113) {¶0038}.
Regarding claim 4, Darwish as modified by Chen teaches the semiconductor device according to claim 3, and Darwish further teaches wherein the base (107, 109, 113, 115, 421, 433) comprises a first-conductivity-type substrate (107) and a first-conductivity-type epitaxial layer (109) on the first-conductivity-type substrate (107), and the second-conductivity-type well region (113) is provided in the first-conductivity-type epitaxial layer (109) {¶0035}.
Regarding claim 5, Darwish as modified by Chen teaches the semiconductor device according to claim 4, and Darwish further teaches wherein a doping concentration of the first-conductivity-type substrate (107; N+) is greater than a doping concentration of the first-conductivity-type epitaxial layer (109; N) {Fig. 4A}.
Regarding claim 6, Darwish as modified by Chen teaches the semiconductor device according to claim 4, and Darwish further teaches wherein the second-conductivity-type doped region (435A) and the second-conductivity-type well region (113) are separated by a part of the first-conductivity-type epitaxial layer (109) {Fig. 4A).
Regarding claim 10, Darwish teaches in Fig. 4A a manufacturing method for a semiconductor device, comprising:
obtaining a base (107, 109, 113, 115, 421, 433) {¶0035, 0037, 0038, 0049};
forming a first trench (center trench) and a second trench (left/right trench) on a first surface (top surface) of the base (107, 109, 113, 115, 421, 433) {¶0040};
forming a trench wall insulation isolation structure (421, 433) on an inner surface of the first trench (center trench) {¶0049};
filling the first trench (center trench) with a gate material (423A) {¶0049};
forming a first-conductivity-type source doped region (115/1209) on both sides of the first trench (center trench) and on both sides of the second trench (left/right trench) {Figs. 4A, 12C; ¶0037, 0067};
forming a gate insulation isolation structure (421) on the gate material (423A) in the first trench (center trench) {¶0049};
forming, on the first surface of the base (107, 109, 113, 115, 421, 433), a source electrode (103) electrically connected to the source doped region (115/1209), and filling a conductive material of the source electrode (103) into the second trench (left/right trench) to form a trench conductive structure (131) electrically connected to the source electrode (103) {¶0043, 0049}; and
forming a drain electrode (101) on a second surface (bottom surface) of the base (107, 109, 113, 115, 421, 433), wherein the first surface (top surface) and the second surface (bottom surface) are opposite {¶0049}.
Darwish does not teach a top of the gate insulation isolation structure is lower than a top of the source doped region, and the source electrode extends into an upper part of the first trench and directly contacts with sides of the source doped region, wherein a material of the source electrode includes conductive metal, alloy, or both.
Chen teaches in Figs. 26A-C and paragraph [0044] a top of a gate insulation isolation structure (3309, 3324, and/or 3326) is lower than a top of a source doped region (3332), and a source electrode (3334) extends into an upper part of a first trench (trench housing 3326, 3320, etc.) and directly contacts with sides of the source doped region (3332), wherein a material of the source electrode (3334) includes conductive metal, alloy, or both. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s manufacturing method based on the teachings of Chen, to achieve the above-identified subject matter, for: (1) [i]ncreased source-metal contact areas lead[ing] to reduced contact resistance and more stable transient response, (2) increased area mean[ing] that it is less likely that the contact would be defective, and (3) more reliable devices and higher manufacturing yields. Chen ¶0044.
Claim(s) 8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Darwish in view of Chen as applied to claim 1 and claim 10 respectively above, and further in view of Cho et al. (US20140042530A1).
Regarding claim 8, Darwish as modified by Chen teaches the semiconductor device according to claim 1, but Darwish does not teach wherein a material of the source electrode is same as a material of the trench conductive structure, and the material of the source electrode and the material of the trench conductive structure both comprise metal and/or alloy.
In an analogous art, Cho teaches in Fig. 5 and paragraph [0104] a material (Cu) of the source electrode (140) is same as a material (Cu) of a trench conductive structure (145), and the material (Cu) of the source electrode (140) and the material (Cu) of the trench conductive structure (145) both comprise metal and/or alloy. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s semiconductor device as modified by Chen based on the teachings of Cho – such that a material of the source electrode is same as a material of the trench conductive structure, and the material of the source electrode and the material of the trench conductive structure both comprise metal and/or alloy – to reduce the manufacturing resources (e.g., number of different materials and/or processing operations). Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 14, Darwish as modified by Chen teaches the manufacturing method according to claim 10, but Darwish does not teach wherein a material of the source electrode is same as a material of the trench conductive structure, and the material of the source electrode and the material of the trench conductive structure both comprise metal and/or alloy.
Cho teaches in Fig. 5 and paragraph [0104] a material (Cu) of the source electrode (140) is same as a material (Cu) of a trench conductive structure (145), and the material (Cu) of the source electrode (140) and the material (Cu) of the trench conductive structure (145) both comprise metal and/or alloy. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s manufacturing method as modified by Chen based on the teachings of Cho – such that a material of the source electrode is same as a material of the trench conductive structure, and the material of the source electrode and the material of the trench conductive structure both comprise metal and/or alloy – to reduce the manufacturing resources (e.g., number of different materials and/or processing operations). Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Darwish in view of Chen as applied to claim 1 and claim 10 respectively above, and further in view of Hino (US20090242976A1).
Regarding claim 9, Darwish as modified by Chen teaches the semiconductor device according to claim 1, but Darwish does not expressly teach wherein the semiconductor device is a trench vertical double-diffused metal oxide semiconductor field effect transistor.
However, Darwish teaches in Fig. 4A and paragraph [0048] the semiconductor device is a trench vertical metal oxide semiconductor field effect transistor (MOSFET). Darwish does not expressly teach the trench vertical MOSFET is double diffused.
In an analogous art, Hino teaches in Fig. 1 and paragraph [0069] a trench vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s semiconductor device as modified by Chen based on the teachings of Hino – such that the semiconductor device is a trench vertical double-diffused metal oxide semiconductor field effect transistor – to achieve low on-resistance properties. Hino ¶0004. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, substituting equivalents (trench VDMOSFET for a trench vertical MOSFET) known for the same purpose (e.g., power transistor) would be obvious to a skilled artisan. MPEP §2144.06(II).
Regarding claim 15, Darwish as modified by Chen teaches the manufacturing method according to claim 10, but Darwish does not teach wherein the semiconductor device is a trench vertical double-diffused metal oxide semiconductor field effect transistor.
However, Darwish teaches in Fig. 4A and paragraph [0048] the semiconductor device is a trench vertical metal oxide semiconductor field effect transistor (MOSFET). Darwish does not expressly teach the trench vertical MOSFET is double diffused.
Hino teaches in Fig. 1 and paragraph [0069] a trench vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s manufacturing method as modified by Chen based on the teachings of Hino – such that the semiconductor device is a trench vertical double-diffused metal oxide semiconductor field effect transistor – to achieve low on-resistance properties. Hino ¶0004. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, substituting equivalents (trench VDMOSFET for a trench vertical MOSFET) known for the same purpose (e.g., power transistor) would be obvious to a skilled artisan. MPEP §2144.06(II).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Darwish in view of Chen as applied to claim 10 above, and further in view of Amali et al. (US20170200799A1).
Regarding claim 11, Darwish as modified by Chen teaches the manufacturing method according to claim 10, and Darwish further teaches
wherein upon forming the trench wall insulation isolation structure (1243) on the inner surface of the first trench (center trench), the method further comprises: simultaneously forming a trench wall insulation isolation structure (1243) on an inner surface of the second trench (left/right trench) {Fig. 12C; ¶0067; ¶0027, FIGS. 12A-12K show a sample process flow that can be used to realize the present inventions};
upon filling the first trench (center trench) with the gate material (1293), the method further comprises: simultaneously filling the second trench (left/right trench) with the gate material (1293) {Figs. 12F, 12G; ¶0068};
after forming the first-conductivity-type source doped region (1209) {Figs. 12C, 12D}, the manufacturing method further comprises: removing (from upper portion of the left/right trench where source material is subsequently disposed) the gate material (1293) in the second trench (left/right trench) {Figs. 12G, 12J}.
Darwish does not expressly teach:
removing the gate material in the second trench before forming the gate insulation isolation structure on the gate material in the first trench; and
after forming the gate insulation isolation structure on the gate material in the first trench, the manufacturing method further comprises: forming an interlayer dielectric on the gate insulation isolation structure, and removing the interlayer dielectric.
In an analogous art, Amali teaches in Fig. 1 removing (178) {Figs. 1, 2D, 2E; ¶0034} a gate material (210) in a second trench (center trench) before forming (180) {Figs. 1,2E, 2F; ¶0035} a gate insulation isolation structure (212) on gate material (210a/b) in a first trench (left/right trench). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s manufacturing method as modified by Chen based on the teachings of Amali – to include removing the gate material in the second trench before forming the gate insulation isolation structure on the gate material in the first trench – for saving manufacturing cost and time (i.e., the inverse sequence of operations would make the end result more difficult to achieve). Moreover, such would have been obvious because the skilled artisan could have applied Amali’s two-step process to the method taught by Darwish as modified by Chen in the same way taught by Amali and the result(s) would have been predictable to the skilled artisan. MPEP §2143(I)(C). Still further, the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. MPEP ¶2144.04(IV)(C).
Regarding the limitations of “forming an interlayer dielectric on the gate insulation isolation structure, and removing the interlayer dielectric,” the Office notes that – with respect to the claimed method for manufacturing a semiconductor device – the claimed operations of adding something and subsequently removing it has no ultimate effect on the manufactured semiconductor device (i.e., the latter operation nullifies the former operation). The same (i.e., identical) outcome may be achieved by omitting entirely both the former and latter operations. Stated another way for increased understanding, both the forming and removing operations are undesired because: (1) the latter operation undoes the former (i.e., undesired) operation and (2) the latter operation is superfluous (e.g., undesired) in the absence of the former operation. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s manufacturing method as modified by Chen and Amali – to omit the operations of forming an interlayer dielectric on the gate insulation isolation structure, and removing the interlayer dielectric – because the elimination of undesired operations is obvious to one of ordinary skill in the art. MPEP ¶2144.04.
As for: (1) “forming an interlayer dielectric on the gate insulation isolation structure, and removing the interlayer dielectric” after (2) forming the gate insulation isolation structure on the gate material in the first trench, the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. MPEP ¶2144.04(IV)(C). And because the undesired feature (1) is eliminated, only operation (2) remains and has no identified sequence with any remaining operation; thus, no unexpected result can prospectively exist from a particular (i.e., non-existent) sequence.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Darwish in view of Chen as applied to claim 10 above, and further in view of Yilmaz et al. (US20130200451A1).
Regarding claim 12, Darwish as modified by Chen teaches the manufacturing method according to claim 10, and Darwish further teaches wherein after forming the first trench (center trench) and the second trench (left/right trench) on the first surface (top surface) of the base (107, 109, 113, 115, 421, 433), the manufacturing method further comprises:
forming a second-conductivity-type doped region (1299), wherein the second-conductivity-type doped region (1299) is formed in the base (107, 109, 113, 115, 421, 433) and is located at a bottom of the first trench (center trench) and/or the second trench (left/right trench), and the first conductivity type (n-type) and the second conductivity type (p-type) are opposite {Figs. 12E, 12F; ¶0068, 0073}.
Darwish does not unequivocally and expressly teach forming the second-conductivity-type doped region before forming the trench wall insulation isolation structure on the inner surface of the first trench. However, Darwish illustrates in Fig. 12E, with only a partial accompanying written description in paragraphs [0068] and [0073] of the specification, forming the second-conductivity-type doped region (1299) by implantation through the first and second trenches in the absence of (i.e., before depositing) the trench wall insulation isolation structure (1243) on the inner surface of the first trench.
In an analogous art, Yilmaz teaches in Fig. 1B and paragraph [0028] forming a second-conductivity-type doped region (134) by implantation through a trench (130) in the absence of a trench wall insulation isolation structure on the inner surface of the trench (130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s manufacturing method as modified by Chen based on the teachings of Yilmaz – such that forming the second-conductivity-type doped region before forming the trench wall insulation isolation structure on the inner surface of the first trench – because the skilled artisan could have applied Yilmaz’s technique to the method taught by Darwish as modified by Chen in the same way taught by Yilmaz and the result would have been predictable to the skilled artisan. MPEP §2143(I)(C). Moreover, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP ¶2143((I)(E).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Darwish in view of Chen as applied to claim 10 above, and further in view of Ohtani (US20190097041A1).
Regarding claim 13, Darwish as modified by Chen teaches the manufacturing method according to claim 10, and Darwish further teaches wherein material of the trench wall insulation isolation structure comprises silicon dioxide {Fig. 12D; ¶0066}.
Darwish does not expressly teach the material of the gate insulation isolation structure comprises silicon dioxide. However, Darwish applies the same continuous shading to both the trench wall insulation isolation structure, which is silicon dioxide, and the gate insulation isolation structure, seemingly indicating the materials of the two structures are identical.
Ohtani teaches in Fig. 1A and paragraph [0054] a material of a gate insulation isolation structure (134) comprises silicon dioxide. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Darwish’s manufacturing method as modified by Chen based on the teachings of Ohtani – such that the material of the gate insulation isolation structure comprises silicon dioxide – because [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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