DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Previous objections to the claims are withdrawn in view of Applicant’s Amendments filed 08/17/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 8-13, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over PENG-FANG CHEN et. al. (CN 112906328 A) Hereinafter CHEN in view of John Blaine et. al. (US 10867093 B1) hereinafter Blaine, Sabyasachi Das et. al. (US 9483597 B1) hereinafter Das, Srinivasan Dasasathyan et. al. (US 11003826 B1) hereinafter Dasasathyan, and Jason Peters et.al. (US 20080059931 A1) hereinafter Peters.
Regarding claim 1
CHEN discloses
A method for constructing a Field Programmable Gate Array (FPGA)-based prototype verification platform, comprising:
(CHEN, Contents of the Invention, “An FPGA prototype verification system generating method, the generating method comprises:”)
converting, based on a set constraint condition, codes for constructing the FPGA-based prototype verification platform into a gate-level netlist
(CHEN, Contents of the Invention, “An FPGA prototype verification system generating method, the generating method comprises:
step S1, dividing the whole FPGA prototype verification system into several verification subsystems
step S2, each verification subsystem is independent; synchronously performing comprehensive processing
step S3, the comprehensive processing of each verification subsystem resource is downloaded to each FPGA verification subsystem, forming a complete verification system; the comprehensive processing refers to converting the RTL code into a door-level netlist file or program, comprising compiling, converting, scheduling, distributing, controller synthesis and result generation; the resource refers to the comprehensive processing result, namely comprehensive processing the generated netlist file;”)
determining whether an operation result of the gate-level netlist meets a requirement defined by preset parameters,
(CHEN, Contents of the Invention, “step S4, verifying the function and performance of the complete verification system
step S5, judging whether the verification is successful;”)
(CHEN, Contents of the Invention, “According to another aspect of the present invention, the following technical solution is adopted: An FPGA prototype verification system generating method, the generating method comprises:
dividing the whole FPGA prototype verification system into several verification subsystems; each verification sub-system can perform FPGA verification of setting function and performance
carrying out comprehensive treatment to each verification subsystem; downloading each verification sub-system resource after comprehensive processing to each FPGA verification sub-system, forming a complete verification system.”)
CHEN does not explicitly teach
wherein the operation result comprise parameters of fanout, timing and congestion
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist according to a set parameter optimization rule,
wherein the parameter optimization rule comprises a fanout optimization rule, a timing optimization rule, and a congestion optimization rule,
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist;
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
wherein after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule,
the method further comprises:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
However Blaine discloses
wherein the operation result comprise parameters of fanout, timing and congestion
(Blaine, col. 3, lines 60-62 “The design checks can be categorized into classes, such as utilization, timing, design constraints, congestion and clocking.”)
(Blaine, col. 4, lines 27-29 “An example of a congestion design check is the level of fanout of a net that drives control pins in a particular congestion region.”)
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist according to a set parameter optimization rule,
(Blaine, col. 5, lines 42-45 “In response to the satisfaction level determined after block 114 being greater than the satisfaction threshold level, the design tool can proceed to block 104 and perform optimization processing on the circuit design.”)
(Blaine, col. 8, lines 6-10 “The synthesis and optimization phases both have threshold values of −0.250 ns, the placement and physical optimization phases both have threshold values of −0.300 ns, and the routing phase has a threshold value of −0.100 ns.”)
wherein the parameter optimization rule comprises a fanout optimization rule, a timing optimization rule, and a congestion optimization rule,
(Blaine, col. 6, lines 26-30 “An exemplary automated suggested action identifies a high fanout net in a critical path and the design tool can automatically tag the high fanout net with a property that causes design tool to replicate the net in an optimization phase of the design flow.”)
(Blaine, col. 2, line 64 – col. 3, line 2 “The design tool can assess the circuit design following design flow stages of synthesis, optimization, placement, and routing. The assessment indicates to the designer the likelihood that the design tool can successfully complete routing the circuit design and satisfy timing and/or power constraints.”)
(Blaine, col. 3, lines 32-35 “The optimizations can redirect an earlier stage of the design flow based on more accurate information of timing or congestion obtained later in the design flow.”)
(Blaine, col. 5, lines 42-45 “In response to the satisfaction level determined after block 114 being greater than the satisfaction threshold level, the design tool can proceed to block 104 and perform optimization processing on the circuit design.”)
(Blaine, col. 5, lines 58-62 “ The manual or automated suggested actions can change the timing or placement constraints of the circuit design to resolve the violation of the design check, and the design tool can rerun the optimization phase at block 104.”)
CHEN and Blaine do not teach
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist;
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
wherein after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule,
the method further comprises:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
However Das discloses
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
(Das, col. 3, lines 60-62 “The modules 202, 204, 206, 208, 210, 216, and 218 are just one example implementation of the circuit design tool 110.”)
(Das, col. 4, lines 8-15 “The circuit design tool 110 can process the abstract description of the circuit design through various intermediate transformations to produce the physical implementation of the circuit design. For a programmable IC (e.g., a field programmable gate array (FPGA)), a physical implementation of a circuit design can be formatted and loaded into the programmable IC to produce a physical circuit.”)
(Das, col. 4, lines 28-30 “A user can interact with the circuit design tool 110 to specify source files 222. The source files 222 can include register-transfer level (RTL) source 224 and constraints 232.”)
(Das, col. 4, lines 36-38 “The constraints 232 include one or more files specifying constraints on the circuit design.”)
(Das, col. 4, lines 42-43 “The constraints 232 can also include placement constraints 235 and routing constraints 237.”)
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
(Das, col. 1, lines 49-58 “The method further includes executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack.”)
(Das, col. 4, lines 56-61 “The IDE module 202 controls the overall circuit design process, including invocation of the design entry module 204, the logic synthesis module 206, the physical implementation module 210, the timing analysis module 216, and the physical optimization module 218.”)
(Das, col. 5, lines 61-63 “The physical optimization module 218 performs timing-driven optimization on negative-slack timing paths in the physical description of the circuit design.”)
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
(Das, col. 8, lines 36-39 “Various optimization strategies 316 can be performed, such as placement optimization, routing optimization, rewiring optimization, clock optimization, retiming optimization, or the like, as well as combinations thereof.”)
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
(Das, col. 8, lines 62-65 “In another example, the convergence criteria 310 can dictate that if timing performance of a path has not improved from a previous iteration, then that timing path is excluded from the candidate timing paths 312.”)
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
(Das, col. 9, lines 11-18 “In another example, the convergence criteria 310 can dictate that if timing performance of a path as not improved by a threshold amount from a previous iteration, then the timing path is considered “timing-congested.” Timing performance can include setup-time performance, hold-time performance, or both. The threshold amount can be dynamically adjusted from one iteration to another based on the slope of the optimization trajectory.”)
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
(Das, col. 3, lines 60-62 “The modules 202, 204, 206, 208, 210, 216, and 218 are just one example implementation of the circuit design tool 110.”)
(Das, col. 4, lines 8-15 “The circuit design tool 110 can process the abstract description of the circuit design through various intermediate transformations to produce the physical implementation of the circuit design. For a programmable IC (e.g., a field programmable gate array (FPGA)), a physical implementation of a circuit design can be formatted and loaded into the programmable IC to produce a physical circuit.”)
(Das, col. 4, lines 28-30 “A user can interact with the circuit design tool 110 to specify source files 222. The source files 222 can include register-transfer level (RTL) source 224 and constraints 232.”)
(Das, col. 4, lines 36-38 “The constraints 232 include one or more files specifying constraints on the circuit design.”)
(Das, col. 4, lines 42-43 “The constraints 232 can also include placement constraints 235 and routing constraints 237.”)
(Das, col. 4, lines 56-61 “The IDE module 202 controls the overall circuit design process, including invocation of the design entry module 204, the logic synthesis module 206, the physical implementation module 210, the timing analysis module 216, and the physical optimization module 218.”)
(Das, col. 5, lines 61-63 “The physical optimization module 218 performs timing-driven optimization on negative-slack timing paths in the physical description of the circuit design.”)
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end of any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
CHEN, Blaine, and Das do not explicitly teach
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist;
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
wherein after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule,
the method further comprises:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
CHEN, Blaine, and Das do not teach
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist;
wherein after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule,
the method further comprises:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
However Dasasathyan discloses
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist;
(Dasasathyan, col. 4, lines 8-13 “Each strategy can target improvement of one or more aspects of the design known to make timing closure difficult, such as routing congestion, control set distribution, whitespace allocation in the placer, resource utilization of different primitives, net fanout distribution, distribution of control sets, etc.”)
(Dasasathyan, col. 6, lines 43-51 “Another exemplary strategy can specify a directive to merge equivalent drivers in a logic optimization phase, a directive to aggressively spread the logic during a placement phase, a directive to aggressively explore different algorithms in multiple passes of physical optimization, including replication for very high fanout nets, and phase in which a subset of physical optimizations are run on the top critical paths of all endpoint clocks, regardless of slack.”)
wherein after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule,
the method further comprises:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
(Dasasathyan, col. 5 line 66 – col. 6, line 4 “The implementation flow process can be performed by one or more circuit design tools (collectively, “circuit design tool”) that perform netlist optimization, placement, physical synthesis, and routing. The implementation flow outputs circuit implementation data and run data.”)
CHEN, Blaine, Das, and Dasasathyan do not teach
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
However Peters discloses
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
(Peters, p. 2, par. [0033] “Verification module 50 may support and perform a variety of verification and simulation options, as desired. The options may include functional verification, …. formal netlist verification, … “)
(Peters, p. 1, par. [0004] “One aspect of the inventive concepts relates to a method of performing placement of resources. In one exemplary embodiment, the method includes performing a first congestion analysis, proposing a placement move, and evaluating the placement move. The method further includes incrementally updating information used for performing another congestion analysis.”)
(Peters, p. 2, par. [0023] “Creating a placement which minimizes the possibility for routing congestion is therefore a desirable optimization goal, as it can improve routing time and quality, and reduce the likelihood of routing failures. This goal should typically be satisfied in conjunction with other optimization goals, including but not limited to, meeting a user's timing constraints, minimizing power consumption, or minimizing total design area.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of CHEN, Blaine, Das, Dasasathyan, and of Peters to yield predictable result of having all the relevant tools for prototype verification platform included in the respective processing units enabling a comprehensive and integrated platform to perform verification to meet design specifications, thereby simplifying design verification and reducing design time.
Regarding claim 6
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 1 as disclosed above and the combination further discloses
The method for constructing the FPGA-based prototype verification platform according to claim 1,
wherein after performing the routing on the elements in the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform, the method further comprises
determining whether there is a timing violation in the FPGA-based prototype verification platform
(Das, col. 1, lines 51-58 “In an example, physical optimization is performed on a placed and routed circuit design (“post-route physical optimization”). Often times, traditional place and route of a circuit design is not able to meet established timing requirements. Post-route physical optimization can be used in an attempt to eliminate or mitigate timing constraint violations (“timing-closure”) by optimizing timing path(s) in the placed and routed design.”)
and calling,
when there is a timing violation in the FPGA-based prototype verification platform,
a post place strategy to adjust the placement of the FPGA-based prototype verification platform,
and performing re-routing based on the adjusted placement.
(Das, col. 1, lines 51-58 “In an example, physical optimization is performed on a placed and routed circuit design (“post-route physical optimization”). Often times, traditional place and route of a circuit design is not able to meet established timing requirements. Post-route physical optimization can be used in an attempt to eliminate or mitigate timing constraint violations (“timing-closure”) by optimizing timing path(s) in the placed and routed design.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of CHEN, Blaine, Das, Dasasathyan, and of Peters to yield predictable result of having all the relevant tools for prototype verification platform included in the respective processing units enabling a comprehensive and integrated platform to perform verification to meet design specifications, thereby simplifying design verification and reducing design time enabling a comprehensive and integrated platform to perform verification to meet design specifications, thereby simplifying design verification and reducing design time, as well as generate a complete report of all the operational results.
Regarding claim 8
CHEN discloses
A device for constructing a Field Programmable Gate Array (FPGA)-based prototype verification platform, comprising:
(CHEN, Background, “In the architecture, the FPGA prototype verification system is composed of three parts:
FPGA RTL comprehensive device, responsible for the RTL source code integrated into the FPGA gate level net table.
FPGA hardware platform, special integrated circuit (ASIC) or on-chip system (SoC) function hardware carrier, comprising an auxiliary hardware device for verifying ASIC or SoC function or performance.”)
a memory, configured to store a computer program
(CHEN, Specific implementation examples, “Likewise, the software program of the present application (including related data structure) can be stored in the computer readable recording medium; For example, RAM memory, magnetic or optical driver or soft magnetic disk and similar device.”)
And a processor, configured to execute the computer program to implement following operations:
(CHEN, Specific implementation examples, “In some embodiments, the software program application can be executed by a processor to implement the above steps or functions.”)
converting, based on a set constraint condition, codes for constructing the FPGA-based prototype verification platform into a gate-level netlist
(CHEN, Contents of the Invention, “each FPGA verification subsystem, forming a complete verification system; the comprehensive processing refers to converting the RTL code into a door-level netlist file or program”)
determining whether an operation result of the gate-level netlist meets a requirement defined by preset parameters,
(CHEN, Contents of the Invention, “… the comprehensive processing refers to converting the RTL code into a door-level netlist file or program, comprising compiling, converting, scheduling, distributing, controller synthesis and result generation; the resource refers to the comprehensive processing result, namely comprehensive processing the generated netlist file;
step S4, verifying the function and performance of the complete verification system
step S5, judging whether the verification is successful;”)
CHEN does not explicitly teach
wherein the operation result comprise parameters of fanout, timing and congestion
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist according to a set parameter optimization rule,
wherein the parameter optimization rule comprises a fanout optimization rule, a timing optimization rule, and a congestion optimization rule,
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers,
a logical replication instruction to adjust the fanout of the gate-level netlist
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
wherein the processor is further configured to execute the computer program to implement following operations after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
However Blaine discloses
wherein the operation result comprise parameters of fanout, timing and congestion
(Blaine, col. 3, lines 60-62 “The design checks can be categorized into classes, such as utilization, timing, design constraints, congestion and clocking.”)
(Blaine, col. 4, lines 27-29 “An example of a congestion design check is the level of fanout of a net that drives control pins in a particular congestion region.”)
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist according to a set parameter optimization rule,
(Blaine, col. 5, lines 42-45 “In response to the satisfaction level determined after block 114 being greater than the satisfaction threshold level, the design tool can proceed to block 104 and perform optimization processing on the circuit design.”)
(Blaine, col. 8, lines 6-10 “The synthesis and optimization phases both have threshold values of −0.250 ns, the placement and physical optimization phases both have threshold values of −0.300 ns, and the routing phase has a threshold value of −0.100 ns.”)
wherein the parameter optimization rule comprises a fanout optimization rule, a timing optimization rule, and a congestion optimization rule,
(Blaine, col. 6, lines 26-30 “An exemplary automated suggested action identifies a high fanout net in a critical path and the design tool can automatically tag the high fanout net with a property that causes design tool to replicate the net in an optimization phase of the design flow.”)
(Blaine, col. 2, line 64 – col. 3, line 2 “The design tool can assess the circuit design following design flow stages of synthesis, optimization, placement, and routing. The assessment indicates to the designer the likelihood that the design tool can successfully complete routing the circuit design and satisfy timing and/or power constraints.”)
(Blaine, col. 3, lines 32-35 “The optimizations can redirect an earlier stage of the design flow based on more accurate information of timing or congestion obtained later in the design flow.”)
(Blaine, col. 5, lines 42-45 “In response to the satisfaction level determined after block 114 being greater than the satisfaction threshold level, the design tool can proceed to block 104 and perform optimization processing on the circuit design.”)
(Blaine, col. 5, lines 58-62 “ The manual or automated suggested actions can change the timing or placement constraints of the circuit design to resolve the violation of the design check, and the design tool can rerun the optimization phase at block 104.”)
CHEN and Blaine do not teach
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers,
a logical replication instruction to adjust the fanout of the gate-level netlist
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
wherein the processor is further configured to execute the computer program to implement following operations after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
However Das discloses
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
(Das, col. 3, lines 60-62 “The modules 202, 204, 206, 208, 210, 216, and 218 are just one example implementation of the circuit design tool 110.”)
(Das, col. 4, lines 8-15 “The circuit design tool 110 can process the abstract description of the circuit design through various intermediate transformations to produce the physical implementation of the circuit design. For a programmable IC (e.g., a field programmable gate array (FPGA)), a physical implementation of a circuit design can be formatted and loaded into the programmable IC to produce a physical circuit.”)
(Das, col. 4, lines 28-30 “A user can interact with the circuit design tool 110 to specify source files 222. The source files 222 can include register-transfer level (RTL) source 224 and constraints 232.”)
(Das, col. 4, lines 36-38 “The constraints 232 include one or more files specifying constraints on the circuit design.”)
(Das, col. 4, lines 42-43 “The constraints 232 can also include placement constraints 235 and routing constraints 237.”)
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
(Das, col. 1, lines 49-58 “The method further includes executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack.”)
(Das, col. 4, lines 56-61 “The IDE module 202 controls the overall circuit design process, including invocation of the design entry module 204, the logic synthesis module 206, the physical implementation module 210, the timing analysis module 216, and the physical optimization module 218.”)
(Das, col. 5, lines 61-63 “The physical optimization module 218 performs timing-driven optimization on negative-slack timing paths in the physical description of the circuit design.”)
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
(Das, col. 8, lines 36-39 “Various optimization strategies 316 can be performed, such as placement optimization, routing optimization, rewiring optimization, clock optimization, retiming optimization, or the like, as well as combinations thereof.”)
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
(Das, col. 8, lines 62-65 “In another example, the convergence criteria 310 can dictate that if timing performance of a path has not improved from a previous iteration, then that timing path is excluded from the candidate timing paths 312.”)
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
(Das, col. 9, lines 11-18 “In another example, the convergence criteria 310 can dictate that if timing performance of a path as not improved by a threshold amount from a previous iteration, then the timing path is considered “timing-congested.” Timing performance can include setup-time performance, hold-time performance, or both. The threshold amount can be dynamically adjusted from one iteration to another based on the slope of the optimization trajectory.”)
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
(Das, col. 3, lines 60-62 “The modules 202, 204, 206, 208, 210, 216, and 218 are just one example implementation of the circuit design tool 110.”)
(Das, col. 4, lines 8-15 “The circuit design tool 110 can process the abstract description of the circuit design through various intermediate transformations to produce the physical implementation of the circuit design. For a programmable IC (e.g., a field programmable gate array (FPGA)), a physical implementation of a circuit design can be formatted and loaded into the programmable IC to produce a physical circuit.”)
(Das, col. 4, lines 28-30 “A user can interact with the circuit design tool 110 to specify source files 222. The source files 222 can include register-transfer level (RTL) source 224 and constraints 232.”)
(Das, col. 4, lines 36-38 “The constraints 232 include one or more files specifying constraints on the circuit design.”)
(Das, col. 4, lines 42-43 “The constraints 232 can also include placement constraints 235 and routing constraints 237.”)
(Das, col. 4, lines 56-61 “The IDE module 202 controls the overall circuit design process, including invocation of the design entry module 204, the logic synthesis module 206, the physical implementation module 210, the timing analysis module 216, and the physical optimization module 218.”)
(Das, col. 5, lines 61-63 “The physical optimization module 218 performs timing-driven optimization on negative-slack timing paths in the physical description of the circuit design.”)
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end of any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
CHEN, Blaine, and Das do not teach
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers,
a logical replication instruction to adjust the fanout of the gate-level netlist
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
wherein the processor is further configured to execute the computer program to implement following operations after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
However Dasasathyan discloses
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers,
a logical replication instruction to adjust the fanout of the gate-level netlist
(Dasasathyan, col. 4, lines 8-13 “Each strategy can target improvement of one or more aspects of the design known to make timing closure difficult, such as routing congestion, control set distribution, whitespace allocation in the placer, resource utilization of different primitives, net fanout distribution, distribution of control sets, etc.”)
(Dasasathyan, col. 6, lines 43-51 “Another exemplary strategy can specify a directive to merge equivalent drivers in a logic optimization phase, a directive to aggressively spread the logic during a placement phase, a directive to aggressively explore different algorithms in multiple passes of physical optimization, including replication for very high fanout nets, and phase in which a subset of physical optimizations are run on the top critical paths of all endpoint clocks, regardless of slack.”)
wherein the processor is further configured to execute the computer program to implement following operations after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule:
generating a placement file each time the physical optimization of the gate-level netlist is performed,
and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
(Dasasathyan, col. 5 line 66 – col. 6, line 4 “The implementation flow process can be performed by one or more circuit design tools (collectively, “circuit design tool”) that perform netlist optimization, placement, physical synthesis, and routing. The implementation flow outputs circuit implementation data and run data.”)
CHEN, Blaine, Das, and Dasasathyan do not teach
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
However Peters discloses
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
(Peters, p. 2, par. [0033] “Verification module 50 may support and perform a variety of verification and simulation options, as desired. The options may include functional verification, …. formal netlist verification, … “)
(Peters, p. 1, par. [0004] “One aspect of the inventive concepts relates to a method of performing placement of resources. In one exemplary embodiment, the method includes performing a first congestion analysis, proposing a placement move, and evaluating the placement move. The method further includes incrementally updating information used for performing another congestion analysis.”)
(Peters, p. 2, par. [0023] “Creating a placement which minimizes the possibility for routing congestion is therefore a desirable optimization goal, as it can improve routing time and quality, and reduce the likelihood of routing failures. This goal should typically be satisfied in conjunction with other optimization goals, including but not limited to, meeting a user's timing constraints, minimizing power consumption, or minimizing total design area.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of CHEN, Blaine, Das, Dasasathyan, and of Peters to yield predictable result of having all the relevant tools for prototype verification platform included in the respective processing units enabling a comprehensive and integrated platform to perform verification to meet design specifications, thereby simplifying design verification and reducing design time.
Regarding claim 9
CHEN discloses
A non-transitory computer-readable storage medium, having a computer program stored thereon, wherein the computer program, when executed by a processor, causes the processor to implement following operations
(CHEN, Specific implementation examples, “For example, an application specific integrated circuit (ASIC), a general purpose computer, or any other similar hardware device may be employed. In some embodiments, the software program application can be executed by a processor to implement the above steps or functions. Likewise, the software program of the present application (including related data structure) can be stored in the computer readable recording medium; For example, RAM memory, magnetic or optical driver or soft magnetic disk and similar device..”)
converting, based on a set constraint condition, codes for constructing the FPGA-based prototype verification platform into a gate-level netlist
(CHEN, Contents of the Invention, “each FPGA verification subsystem, forming a complete verification system; the comprehensive processing refers to converting the RTL code into a door-level netlist file or program”)
determining whether an operation result of the gate-level netlist meets a requirement defined by preset parameters,
(CHEN, Contents of the Invention, “… the comprehensive processing refers to converting the RTL code into a door-level netlist file or program, comprising compiling, converting, scheduling, distributing, controller synthesis and result generation; the resource refers to the comprehensive processing result, namely comprehensive processing the generated netlist file;
step S4, verifying the function and performance of the complete verification system
step S5, judging whether the verification is successful;”)
CHEN does not teach
wherein the operation result comprise parameters of fanout, timing and congestion
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist according to a set parameter optimization rule,
wherein the parameter optimization rule comprises a fanout optimization rule, a timing optimization rule, and a congestion optimization rule,
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers,
a logical replication instruction to adjust the fanout of the gate-level netlist
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
wherein the computer program, when executed by the processor, causes the processor to implement following operations after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule:
generating a placement file each time the physical optimization of the gate-level netlist is performed, and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
However Blaine discloses
wherein the operation result comprise parameters of fanout, timing and congestion
(Blaine, col. 3, lines 60-62 “The design checks can be categorized into classes, such as utilization, timing, design constraints, congestion and clocking.”)
(Blaine, col. 4, lines 27-29 “An example of a congestion design check is the level of fanout of a net that drives control pins in a particular congestion region.”)
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist according to a set parameter optimization rule,
(Blaine, col. 5, lines 42-45 “In response to the satisfaction level determined after block 114 being greater than the satisfaction threshold level, the design tool can proceed to block 104 and perform optimization processing on the circuit design.”)
(Blaine, col. 8, lines 6-10 “The synthesis and optimization phases both have threshold values of −0.250 ns, the placement and physical optimization phases both have threshold values of −0.300 ns, and the routing phase has a threshold value of −0.100 ns.”)
wherein the parameter optimization rule comprises a fanout optimization rule, a timing optimization rule, and a congestion optimization rule,
(Blaine, col. 6, lines 26-30 “An exemplary automated suggested action identifies a high fanout net in a critical path and the design tool can automatically tag the high fanout net with a property that causes design tool to replicate the net in an optimization phase of the design flow.”)
(Blaine, col. 2, line 64 – col. 3, line 2 “The design tool can assess the circuit design following design flow stages of synthesis, optimization, placement, and routing. The assessment indicates to the designer the likelihood that the design tool can successfully complete routing the circuit design and satisfy timing and/or power constraints.”)
(Blaine, col. 3, lines 32-35 “The optimizations can redirect an earlier stage of the design flow based on more accurate information of timing or congestion obtained later in the design flow.”)
(Blaine, col. 5, lines 42-45 “In response to the satisfaction level determined after block 114 being greater than the satisfaction threshold level, the design tool can proceed to block 104 and perform optimization processing on the circuit design.”)
(Blaine, col. 5, lines 58-62 “ The manual or automated suggested actions can change the timing or placement constraints of the circuit design to resolve the violation of the design check, and the design tool can rerun the optimization phase at block 104.”)
CHEN and Blaine do not teach
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers,
a logical replication instruction to adjust the fanout of the gate-level netlist
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
wherein the computer program, when executed by the processor, causes the processor to implement following operations after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule:
generating a placement file each time the physical optimization of the gate-level netlist is performed, and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
However Das discloses
and correspondingly,
performing,
when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters,
the physical optimization on the gate- level netlist according to the set parameter optimization rule comprises:
(Das, col. 3, lines 60-62 “The modules 202, 204, 206, 208, 210, 216, and 218 are just one example implementation of the circuit design tool 110.”)
(Das, col. 4, lines 8-15 “The circuit design tool 110 can process the abstract description of the circuit design through various intermediate transformations to produce the physical implementation of the circuit design. For a programmable IC (e.g., a field programmable gate array (FPGA)), a physical implementation of a circuit design can be formatted and loaded into the programmable IC to produce a physical circuit.”)
(Das, col. 4, lines 28-30 “A user can interact with the circuit design tool 110 to specify source files 222. The source files 222 can include register-transfer level (RTL) source 224 and constraints 232.”)
(Das, col. 4, lines 36-38 “The constraints 232 include one or more files specifying constraints on the circuit design.”)
(Das, col. 4, lines 42-43 “The constraints 232 can also include placement constraints 235 and routing constraints 237.”)
calling,
when there is a timing violation in the operation result,
a timing adjustment instruction to adjust timing of the gate-level netlist
(Das, col. 1, lines 49-58 “The method further includes executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack.”)
(Das, col. 4, lines 56-61 “The IDE module 202 controls the overall circuit design process, including invocation of the design entry module 204, the logic synthesis module 206, the physical implementation module 210, the timing analysis module 216, and the physical optimization module 218.”)
(Das, col. 5, lines 61-63 “The physical optimization module 218 performs timing-driven optimization on negative-slack timing paths in the physical description of the circuit design.”)
and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform,
(Das, col. 8, lines 36-39 “Various optimization strategies 316 can be performed, such as placement optimization, routing optimization, rewiring optimization, clock optimization, retiming optimization, or the like, as well as combinations thereof.”)
returning,
when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization,
to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
(Das, col. 8, lines 62-65 “In another example, the convergence criteria 310 can dictate that if timing performance of a path has not improved from a previous iteration, then that timing path is excluded from the candidate timing paths 312.”)
determining,
when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization,
whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters
(Das, col. 9, lines 11-18 “In another example, the convergence criteria 310 can dictate that if timing performance of a path as not improved by a threshold amount from a previous iteration, then the timing path is considered “timing-congested.” Timing performance can include setup-time performance, hold-time performance, or both. The threshold amount can be dynamically adjusted from one iteration to another based on the slope of the optimization trajectory.”)
performing,
when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters,
physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
(Das, col. 3, lines 60-62 “The modules 202, 204, 206, 208, 210, 216, and 218 are just one example implementation of the circuit design tool 110.”)
(Das, col. 4, lines 8-15 “The circuit design tool 110 can process the abstract description of the circuit design through various intermediate transformations to produce the physical implementation of the circuit design. For a programmable IC (e.g., a field programmable gate array (FPGA)), a physical implementation of a circuit design can be formatted and loaded into the programmable IC to produce a physical circuit.”)
(Das, col. 4, lines 28-30 “A user can interact with the circuit design tool 110 to specify source files 222. The source files 222 can include register-transfer level (RTL) source 224 and constraints 232.”)
(Das, col. 4, lines 36-38 “The constraints 232 include one or more files specifying constraints on the circuit design.”)
(Das, col. 4, lines 42-43 “The constraints 232 can also include placement constraints 235 and routing constraints 237.”)
(Das, col. 4, lines 56-61 “The IDE module 202 controls the overall circuit design process, including invocation of the design entry module 204, the logic synthesis module 206, the physical implementation module 210, the timing analysis module 216, and the physical optimization module 218.”)
(Das, col. 5, lines 61-63 “The physical optimization module 218 performs timing-driven optimization on negative-slack timing paths in the physical description of the circuit design.”)
and performing,
when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters,
routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end of any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
CHEN, Blaine, and Das do not teach
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers,
a logical replication instruction to adjust the fanout of the gate-level netlist
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
wherein the computer program, when executed by the processor, causes the processor to implement following operations after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule:
generating a placement file each time the physical optimization of the gate-level netlist is performed, and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
However Dasasathyan discloses
calling,
when a fanout in the operation result does not meet a set quantity of signal drivers,
a logical replication instruction to adjust the fanout of the gate-level netlist
(Dasasathyan, col. 4, lines 8-13 “Each strategy can target improvement of one or more aspects of the design known to make timing closure difficult, such as routing congestion, control set distribution, whitespace allocation in the placer, resource utilization of different primitives, net fanout distribution, distribution of control sets, etc.”)
(Dasasathyan, col. 6, lines 43-51 “Another exemplary strategy can specify a directive to merge equivalent drivers in a logic optimization phase, a directive to aggressively spread the logic during a placement phase, a directive to aggressively explore different algorithms in multiple passes of physical optimization, including replication for very high fanout nets, and phase in which a subset of physical optimizations are run on the top critical paths of all endpoint clocks, regardless of slack.”)
wherein the computer program, when executed by the processor, causes the processor to implement following operations after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule:
generating a placement file each time the physical optimization of the gate-level netlist is performed, and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization
(Dasasathyan, col. 2, lines 4-6 “The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).”)
(Dasasathyan, col. 2, lines 50-51 “FIG. 5 shows a flowchart of a process that aggregates the outputs of the classification models;”)
(Dasasathyan, col. 5, line 66 – col. 6, line 4 “The implementation flow process can be performed by one or more circuit design tools (collectively, “circuit design tool”) that perform netlist optimization, placement, physical synthesis, and routing. The implementation flow outputs circuit implementation data and run data.”)
(Dasasathyan, col. 6, lines 5-13 “The implementation data can specify characteristics of the target device on which the design is to be implemented, netlist features, the circuit structures (e.g., “primitives”) to be used in making an operable circuit, connections between the circuit structures, etc. The run data can include data such as wirelength after global placement, the congestion after an initial routing, the WNS after placement, the improvement seen in physical synthesis, the time spent routing the circuit design, etc.”)
(Dasasathyan, col. 9, lines 49-55 “At block 414, the data resulting from the runs of the implementation flow using the K strategies is analyzed to determine whether or not the targeted metric improved enough to satisfy the design constraints. If the design constraints are satisfied, the implementation data from one of the runs can be selected and further processed to generate data that is suitable for making an integrated circuit.”)
CHEN, Blaine, Das, and Dasasathyan do not teach
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
However Peters discloses
and calling,
when a congestion level in the operation result is greater than or equal to a preset level value,
an alternate replication instruction to adjust the congestion level of the gate- level netlist
(Peters, p. 2, par. [0033] “Verification module 50 may support and perform a variety of verification and simulation options, as desired. The options may include functional verification, …. formal netlist verification, … “)
(Peters, p. 1, par. [0004] “One aspect of the inventive concepts relates to a method of performing placement of resources. In one exemplary embodiment, the method includes performing a first congestion analysis, proposing a placement move, and evaluating the placement move. The method further includes incrementally updating information used for performing another congestion analysis.”)
(Peters, p. 2, par. [0023] “Creating a placement which minimizes the possibility for routing congestion is therefore a desirable optimization goal, as it can improve routing time and quality, and reduce the likelihood of routing failures. This goal should typically be satisfied in conjunction with other optimization goals, including but not limited to, meeting a user's timing constraints, minimizing power consumption, or minimizing total design area.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of CHEN, Blaine, Das, Dasasathyan, and of Peters to yield predictable result of having all the relevant tools for prototype verification platform included in the respective processing units enabling a comprehensive and integrated platform to perform verification to meet design specifications, thereby simplifying design verification and reducing design time, as well as generate a complete report of all the operational results.
Regarding claim 10
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 1 as disclosed above and the combination further discloses
The method for constructing the FPGA-based prototype verification platform according to claim 1, wherein converting, based on the set constraint condition, the codes for constructing the FPGA-based prototype verification platform into the gate- level netlist comprises
converting the codes for constructing the FPGA-based prototype verification platform into an initial netlist
(CHEN, Contents of the Invention, “each FPGA verification subsystem, forming a complete verification system; the comprehensive processing refers to converting the RTL code into a door-level netlist file or program”)
performing design optimization on the initial netlist based on set design indexes to obtain a logical relationship netlist that meets the design indexes
(Das, col. 5, lines 16-25 “For example, the logical description can include a representation of the circuit design in terms of specific logic elements optimized to the architecture of a programmable IC, such as lookup tables (LUTs), carry logic, 10 buffers, and like technology-specific components. In another example, the logical description can include a representation of the circuit design in terms of gates, flip-flops, and the like (sometimes referred to as a “gate-level description”). The logical description can be specified by a netlist 228 (e.g., a synthesized netlist).”)
and configuring elements in the logical relationship netlist into an FPGA based on the constraint condition to obtain the gate-level netlist.
(Das, col. 5, lines 51-60 “The timing analysis module 216 performs a timing analysis of the logical description and/or physical description of the circuit design. The timing analysis module 216 verifies that the logical description and/or the physical description meet the timing constraints 234 specified by the circuit designer. The timing analysis can include various timing checks to ensure that the circuit design is fully constrained and that the circuit design meets timing requirements (e.g., slack for timing paths) derived in response to the timing constraints 234.”)
(Das, col. 5, lines 16-25 “For example, the logical description can include a representation of the circuit design in terms of specific logic elements optimized to the architecture of a programmable IC, such as lookup tables (LUTs), carry logic, 10 buffers, and like technology-specific components. In another example, the logical description can include a representation of the circuit design in terms of gates, flip-flops, and the like (sometimes referred to as a “gate-level description”). The logical description can be specified by a netlist 228 (e.g., a synthesized netlist).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of CHEN, Blaine, Das, Dasasathyan, and of Peters to yield predictable result of having all the relevant tools for prototype verification platform included in the respective processing units enabling a comprehensive and integrated platform to perform verification to meet design specifications, thereby simplifying design verification and reducing design time, as well as generate a complete report of all the operational results.
Regarding claim 11
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 10 as disclosed above and the combination further discloses
The method for constructing the FPGA-based prototype verification platform according to claim 10, wherein the design indexes comprise a global buffer (BUFG), a shift register, a memory, and remapping.
(Das, col. 8, lines 27-39 “The candidate selection module 220 provides the selected timing path 314 to the physical optimization module 218 as parametric input for physical optimization. The physical optimization module 218 can perform one or more physical optimizations on the selected timing path 314 according to one or more optimization strategies 316. The physical optimization module 218 modifies the physical description 302 by applying the optimization strategies 316 to the selected timing path 314. Various optimization strategies 316 can be performed, such as placement optimization, routing optimization, rewiring optimization, clock optimization, retiming optimization, or the like, as well as combinations thereof.”)
(Das, col. 6, lines 34-47 “FIG. 4 is a block diagram depicting examples of timing paths that can be specified in a physical description of a circuit design. A physical description of a circuit design can specify sequential logic elements, such as flip-flops 412 and 414, within an IC 401. An external port DIN of the IC 401 is coupled to an output of an external flip-flop 410, and an external port DOUT of the IC 401 is coupled to an output of an external flip-flop 416. Clock ports of the external flip-flops 410 and 416 are clocked by an external clock referred to as a “board clock”. An external port CLK0 of the IC 401 receives an external clock signal referred to as “CLK0”. The clock signal CLK0 is coupled to a clock buffer 418, which couples the clock signal CLK0 to clock ports of the flip-flops 412 and 414.”)
Regarding claim 12
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 1 as disclosed above and the combination further discloses
The method for constructing the FPGA-based prototype verification platform according to claim 1, wherein the fanout indicates a maximum amount of digital signal input that is able to be driven by a single logic gate.
(Blaine, col. 4, lines 27-32 “An example of a congestion design check is the level of fanout of a net that drives control pins in a particular congestion region. A violation can be determined based on a first threshold value for identifying high-fanout nets and a second threshold value indicating a number of high-fanout nets in the region.”)
(Blaine, col. 6, lines 26-30 “An exemplary automated suggested action identifies a high fanout net in a critical path and the design tool can automatically tag the high fanout net with a property that causes design tool to replicate the net in an optimization phase of the design flow.”)
Regarding claim 13
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 1 as disclosed above and the combination further discloses
The method for constructing the FPGA-based prototype verification platform according to claim1, wherein it is determined that the fanout in the operation result does not meet the set quantity of signal drivers when the fanout in the operation result is greater than the set quantity of the signal drivers.
(Blaine, col. 4, lines 27-32 “An example of a congestion design check is the level of fanout of a net that drives control pins in a particular congestion region. A violation can be determined based on a first threshold value for identifying high-fanout nets and a second threshold value indicating a number of high-fanout nets in the region.”)
(Blaine, col. 6, lines 26-30 “An exemplary automated suggested action identifies a high fanout net in a critical path and the design tool can automatically tag the high fanout net with a property that causes design tool to replicate the net in an optimization phase of the design flow.”)
Regarding claim 20
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 8 as disclosed above and the combination further discloses
The device for constructing the FPGA-based prototype verification platform according to claim 8,
wherein the processor is further configured to execute the computer program to implement following operations after performing the routing on the elements in the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform:
determining whether there is a timing violation in the FPGA-based prototype verification platform
(Das, col. 5, lines 1-4 “The physical optimization module 218 can invoke the timing analysis module 216 in order to perform timing analysis of the physical description.”)
(Das, col. 2, lines 55-58 “Post-route physical optimization can be used in an attempt to eliminate or mitigate timing constraint violations (“timing-closure”) by optimizing timing path(s) in the placed and routed design.”)
and calling, when there is a timing violation in the FPGA-based prototype verification platform, a post place strategy to adjust the placement of the FPGA-based prototype verification platform, and performing re-routing based on the adjusted placement.
(Das, col. 1, lines 51-58 “In an example, physical optimization is performed on a placed and routed circuit design (“post-route physical optimization”). Often times, traditional place and route of a circuit design is not able to meet established timing requirements. Post-route physical optimization can be used in an attempt to eliminate or mitigate timing constraint violations (“timing-closure”) by optimizing timing path(s) in the placed and routed design.”)
Regarding claim 21
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 8 as disclosed above and the combination further discloses
The device for constructing the FPGA-based prototype verification platform according to claim 8,
wherein converting, based on the set constraint condition, the codes for constructing the FPGA-based prototype verification platform into the gate- level netlist comprises:
converting the codes for constructing the FPGA-based prototype verification platform into an initial netlist
(CHEN, Contents of the Invention, “each FPGA verification subsystem, forming a complete verification system; the comprehensive processing refers to converting the RTL code into a door-level netlist file or program”)
performing design optimization on the initial netlist based on set design indexes to obtain a logical relationship netlist that meets the design indexes
(Das, col. 5, lines 16-25 “For example, the logical description can include a representation of the circuit design in terms of specific logic elements optimized to the architecture of a programmable IC, such as lookup tables (LUTs), carry logic, 10 buffers, and like technology-specific components. In another example, the logical description can include a representation of the circuit design in terms of gates, flip-flops, and the like (sometimes referred to as a “gate-level description”). The logical description can be specified by a netlist 228 (e.g., a synthesized netlist).”)
and configuring elements in the logical relationship netlist into an FPGA based on the constraint condition to obtain the gate-level netlist.
(Das, col. 5, lines 51-60 “The timing analysis module 216 performs a timing analysis of the logical description and/or physical description of the circuit design. The timing analysis module 216 verifies that the logical description and/or the physical description meet the timing constraints 234 specified by the circuit designer. The timing analysis can include various timing checks to ensure that the circuit design is fully constrained and that the circuit design meets timing requirements (e.g., slack for timing paths) derived in response to the timing constraints 234.”)
(Das, col. 5, lines 16-25 “For example, the logical description can include a representation of the circuit design in terms of specific logic elements optimized to the architecture of a programmable IC, such as lookup tables (LUTs), carry logic, 10 buffers, and like technology-specific components. In another example, the logical description can include a representation of the circuit design in terms of gates, flip-flops, and the like (sometimes referred to as a “gate-level description”). The logical description can be specified by a netlist 228 (e.g., a synthesized netlist).”)
Claims 4, 14-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN, Blaine, Das, Dasasathyan, and Peters as applied to claim 1 and 8 respectively above, and further in view of Steven Teig et. al. (US 20150186561 A1) hereinafter Teig.
Regarding claim 4
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 1 as disclosed above and the combination further discloses
The method for constructing the FPGA-based prototype verification platform according to claim 1,
wherein the timing comprises a setup time and a hold time
(Das, col. 8, lines 65-67 “Timing performance can include setup-time performance, hold-time performance, or both.”)
and correspondingly,
calling,
when there is the timing violation in the operation result,
(Das, col. 5, lines 1-4 “The physical optimization module 218 can invoke the timing analysis module 216 in order to perform timing analysis of the physical description.”)
(Das, col. 2, lines 55-58 “Post-route physical optimization can be used in an attempt to eliminate or mitigate timing constraint violations (“timing-closure”) by optimizing timing path(s) in the placed and routed design.”)
CHEN, Blaine, Das, Dasasathyan, and Peters do not teach
the timing adjustment instruction to adjust the timing of the gate-level netlist comprises:
calling,
when there is a setup time violation, a retime instruction to adjust the setup time of the gate-level netlist
However, Teig discloses
the timing adjustment instruction to adjust the timing of the gate-level netlist comprises:
calling,
when there is a setup time violation, a retime instruction to adjust the setup time of the gate-level netlist
(Teig, p. 5, par. [0076] “In addition, the clock arrival times of two adjacent clocked elements have to satisfy setup and hold time constraints.”)
(Teig, p. 1, par. [0007] “Some embodiments provide a method of optimizing timing performance of an IC design.”)
(Teig, p. 3, par. [0045] “Retiming is a timing optimization technique that moves the clocked elements in a netlist of an IC design without changing the position of the combinational logic elements in order to optimize the performance of the IC without changing the IC output behavior.”)
(Teig, p. 3, par. [0046] “Accordingly, some embodiments provide a method of optimizing an IC design by using retiming that changes the netlist topology… “)
and calling,
when there is a hold time violation, a hold fix instruction to adjust the hold time of the gate-level netlist.
(Teig, p. 5, par. [0085] “… The optimization using a traditional clock skew scheduling is limited to skewing the clock by an amount that does not interfere with the required time of the signal at the inputs of the combinational logic 630 as well the setup and holding time of the next (or the previous) consecutive clocked element in the netlist.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of CHEN, Blaine, Das, Dasasathyan, Peters, and Teig to yield predictable result of having all the relevant tools including timing fixes for prototype verification platform included in the respective processing units enabling a comprehensive and integrated platform to perform verification to meet design specifications, thereby simplifying design verification and reducing design time, as well as generate a complete report of all the operational results.
Regarding claim 14
CHEN, Blaine, Das, Peters, Dasasathyan, and Teig teach all features of claim 4 as disclosed above and the combination further discloses
The method for constructing the FPGA-based prototype verification platform according to claim 4, wherein the setup time comprises a Worst Negative Slack (WNS); and the hold time comprises a Worst Hold Slack (WHS).
(Das, col. 8, lines 18-26 “ The selected timing path 314 is the timing path having the worst negative slack (WNS) of all candidate timing paths 312 (“WNS timing path”). If there are multiple clock groups 306, the selected timing path 314 comprises the WNS timing path across all of the clock groups 306. The WNS timing path is selected for physical optimization, since improvement of the WNS timing path is likely to improve the total negative slack of the entire circuit design, in addition to the WNS timing path itself.”)
Regarding claim 15
CHEN, Blaine, Das, Dasasathyan, Peters, and Teig teach all features of claim 14 as disclosed above and the combination further discloses
The method for constructing the FPGA-based prototype verification platform according to claim 14, wherein it is determined that there is the setup time violation when the WNS is negative; and it is determined that there is the hold time violation when the WHS is negative.
(Das, col. 2, lines 53-62 “Often times, traditional place and route of a circuit design is not able to meet established timing requirements. Post-route physical optimization can be used in an attempt to eliminate or mitigate timing constraint violations (“timing-closure”) by optimizing timing path(s) in the placed and routed design. In order to reduce runtime of post-route physical optimization, an opportunistic candidate selection approach is employed to select which negative slack timing paths are to be optimized.”)
(Das, col. 8, line 65 – col. 9, line 4 “Timing performance can include setup-time performance, hold-time performance, or both. In such case, the selected timing path 314 becomes the timing path having the next worst negative slack (i.e., the next worst negative slack path of timing paths 304 becomes the WNS timing path in the candidate timing paths 312).”)
Regarding claim 18
CHEN, Blaine, Das, Dasasathyan, and Peters teach all features of claim 8 as disclosed above and the combination further discloses
The device for constructing the FPGA-based prototype verification platform according to claim 8,
wherein the timing comprises a setup time and a hold time
(Das, col. 8, lines 65-67 “Timing performance can include setup-time performance, hold-time performance, or both.”)
and correspondingly, calling, when there is the timing violation in the operation result,
(Das, col. 5, lines 1-4 “The physical optimization module 218 can invoke the timing analysis module 216 in order to perform timing analysis of the physical description.”)
(Das, col. 2, lines 55-58 “Post-route physical optimization can be used in an attempt to eliminate or mitigate timing constraint violations (“timing-closure”) by optimizing timing path(s) in the placed and routed design.”)
the timing adjustment instruction to adjust the timing of the gate-level netlist comprises:
(Das, col. 5, lines 1-4 “The physical optimization module 218 can invoke the timing analysis module 216 in order to perform timing analysis of the physical description.”)
(Das, col. 2, lines 55-58 “Post-route physical optimization can be used in an attempt to eliminate or mitigate timing constraint violations (“timing-closure”) by optimizing timing path(s) in the placed and routed design.”)
CHEN, Blaine, Das, Dasasathyan, and Peters do not teach
calling, when there is a setup time violation, a retime instruction to adjust the setup time of the gate-level netlist
and calling, when there is a hold time violation, a hold fix instruction to adjust the hold time of the gate-level netlist.
However Teig teaches
calling, when there is a setup time violation, a retime instruction to adjust the setup time of the gate-level netlist
(Teig, p. 5, par. [0076] “In addition, the clock arrival times of two adjacent clocked elements have to satisfy setup and hold time constraints.”)
(Teig, p. 1, par. [0007] “Some embodiments provide a method of optimizing timing performance of an IC design.”)
(Teig, p. 3, par. [0045] “Retiming is a timing optimization technique that moves the clocked elements in a netlist of an IC design without changing the position of the combinational logic elements in order to optimize the performance of the IC without changing the IC output behavior.”)
(Teig, p. 3, par. [0046] “Accordingly, some embodiments provide a method of optimizing an IC design by using retiming that changes the netlist topology… “)
and calling, when there is a hold time violation, a hold fix instruction to adjust the hold time of the gate-level netlist.
(Teig, p. 5, par. [0085] “… The optimization using a traditional clock skew scheduling is limited to skewing the clock by an amount that does not interfere with the required time of the signal at the inputs of the combinational logic 630 as well the setup and holding time of the next (or the previous) consecutive clocked element in the netlist.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of CHEN, Blaine, Das, Dasasathyan, Peters, and Teig to yield predictable result of having all the relevant tools including timing fixes for prototype verification platform included in the respective processing units enabling a comprehensive and integrated platform to perform verification to meet design specifications, thereby simplifying design verification and reducing design time, as well as generate a complete report of all the operational results.
Response to Arguments
Applicant's arguments filed 08/17/2026 have been fully considered but they are not persuasive.
Argument: Rejections Under 35 U.S.C. § 103
Claims 1, 3, 6, 8-11, 17, and 20-21 are rejected under 35 U.S.C. § 103 as allegedly being
unpatentable over CN Publication No. 112906328 to Chen et al. ("Chen") in view of U.S. Patent No. 9,483,597 to Das et al. ("Das"), and further in view of U.S. Patent No. 11,003,826 to Dasasathyan et al. ("Dasasathyan"); Claims 2, 12-13, and 16 are rejected under 35 U.S.C. § 103 as allegedly being unpatentable over Chen in view of Das, in view of Dasasathyan, as applied to claims 1 and 8 above respectively, and further in view of U.S. Patent No. 10,867,093 to Blaine et al. ("Blaine"); Claims 4, 14-15, and 18 are rejected under 35 U.S.C. § 103 as allegedly being unpatentable over Chen in view of Das, in view of Dasasathyan, as applied to claims 3 and 17 above respectively, and further in view of U.S. Publication No. 2015/0186561 to Teig et al. ("Teig"); and Claims 5 and 19 are rejected under 35 U.S.C. § 103 as allegedly being unpatentable over Chen in view of Das, in view of Dasasathyan, as applied to claim 1 above, in view of Blaine, and further in view of U.S. Publication No. 2008/0059931 to Peters et al. ("Peters"). Applicant respectfully traverses these rejections, and the sufficiency of the rejections is not conceded.
Claim 1, as amended, recites as follows:
A method for constructing a Field Programmable Gate Array (FPGA)-based prototype verification platform, comprising: converting, based on a set constraint condition, codes for constructing the FPGA-based prototype verification platform into a gate-level netlist; determining whether an operation result of the gate-level netlist meets a requirement defined by preset parameters, wherein the operation result comprise parameters of fanout, timing and congestion; performing, when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters, physical optimization on the gate-level netlist according to a set parameter optimization rule, wherein the parameter optimization rule comprises a fanout optimization rule, a timing optimization rule, and a congestion optimization rule, and correspondingly, performing, when the operation result of the gate- level netlist does not meet the requirement defined by the preset parameters, the physical optimization on the gate-level netlist according to the set parameter optimization rule comprises: calling, when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist; calling, when there is a timing violation in the operation result, a timing adjustment instruction to adjust timing of the gate-level netlist; and calling, when a congestion level in the operation result is greater than or equal to a preset level value, an alternate replication instruction to adjust the congestion level of the gate-level netlist; and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform, wherein after performing the physical optimization on the gate-level netlist according to the set parameter optimization rule, the method further comprises: generating a placement file each time the physical optimization of the gate-level netlist is performed, and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization; returning, when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization, to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization; determining, when the parameters in the operation result generated after the latest physical optimization are smaller than the parameters in the operation result generated after the immediately previous physical optimization, whether the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters; performing, when the operation result generated after the latest physical optimization has a target parameter that does not meet the requirement defined by the preset parameters, physical optimization on the gate-level netlist based on the parameter optimization rule corresponding to the target parameter; and performing, when the parameters in the operation result generated after the latest physical optimization meet the requirement defined by the preset parameters, routing on the elements in the gate-level netlist subjected to the latest physical optimization to obtain the FPGA-based prototype verification platform.
Applicants respectfully submit that the cited references, alone or in combination, do not disclose the above limitations.
For example, in contrast to the cited references, Claim 1 recites "determining whether an operation result of the gate-level netlist meets a requirement defined by preset parameters, wherein the operation result comprise parameters of fanout, timing and congestion".
With respect to this recited subject matter, the Action references Contents of the Invention of CHEN which states the following:
The invention discloses an FPGA prototype verification system generation method and system and an FPGA prototype verification method and system. The generation method comprises the steps that the whole FPGA prototype verification system is divided into a plurality of verification subsystems; each verification subsystem can perform FPGA verification of set functions and performance; and the integrated resources of each verification subsystem are downloaded to each FPGA verification subsystem to form a complete verification system. The verification subsystem is used for correcting or modifying the setting; the corrected or modified verification subsystem is synthesized again; and the integrated verification subsystem resources are downloaded to the corresponding FPGA verification subsystem. According to the FPGA prototype verification system generation method and system and the FPGA prototype verification method and system, an original verification system is divided into a plurality of subsystems, each subsystem can be independently and synchronously integrated, the integration complexity can be reduced, the integration time can be shortened, and the integration efficiency can be improved.
Based on the above content, it is evident that CHEN discloses a high-level verification loop: "modify code -> re-synthesize RTL -> generate new netlist -> download for verification". CHEN's process is a closed-loop functional iteration aimed at correcting logical errors or modifying subsystem structures. It does not address physical implementation constraints such as fanout distribution, timing slack, or routing congestion at the netlist level before routing.
In contrast to CHEN, Claim 1 recites determining whether an operation result comprising "parameters of fanout, timing and congestion" meets a requirement defined by preset parameters. This limitation explicitly defines the verification object as physical parameters of the gate-level netlist, distinct from functional correctness. The subject-matter of the amended Claim 1 employs a physical constraint-based iterative optimization process. Upon generating the gate-level netlist, the solution explicitly checks physical metrics (fanout, timing, congestion). If these physical parameters fail preset requirements, the system invokes specific physical optimization instructions (e.g., logical replication for fanout, retiming for setup/hold violations, alternate replication for congestion) to adjust the netlist's physical layout. This occurs before routing, aiming to ensure routability and timing closure. CHEN's re-synthesis is a coarse-grained, logical correction that lacks the granularity of physical parameter adjustment. Therefore, CHEN does not teach or suggest verifying and optimizing based on specific physical parameters like fanout, timing, and congestion to facilitate subsequent routing. The combination of these features is not obvious.
For example, in contrast to the cited references, Claim 1 recites "performing, when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters, physical optimization on the gate-level netlist according to a set parameter optimization rule...... and performing routing on elements in ...... the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform", i.e., the physical optimization is performed on the gate-level netlist prior to performing routing on elements in the gate- level netlist to obtain the FPGA-based prototype verification platform.
With respect to this recited subject matter, the Action references the following content of Das:
The physical optimization module 218 performs timing- driven optimization on negative-slack timing paths in the physical description of the circuit design. "Slack" is defined (col. 5, lines 61-63)
timing path 314. Various optimization strategies 316 can be performed, such as placement optimization, routing optimization, rewiring optimization, clock optimization, retiming optimization, or the like, as well as combinations thereof. (col. 8, lines 36-39)
Regarding the order between routing and physical optimization, Das, col. 1, lines 43-60, discloses:
Techniques for opportunistic candidate path selection during physical optimization of a circuit design for an integrated circuit (IC). In an example, a method of implementing a circuit design for an integrated circuit (IC) includes placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths. The method further includes executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack. The method further includes generating a physical implementation of the circuit design for the IC based on the physical description. (col. 1, lines 43-60)
Based on the above content of Das, it is evident that Das explicitly defines its optimization process as post-route physical optimization, since the placing and routing a logical description of the circuit design is the first step performed in order to generate a physical description, and this physical description is the object to be optimized in terms of its timing paths.
In contrast, Claim 1 recites "performing routing on elements in ...... the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform", i.e., a sequence where physical optimization is performed on the gate-level netlist prior to the final routing step that obtains the FPGA-based prototype verification platform. Das does not teach optimizing a gate-level netlist in a pre-routing phase based on preset parameters to facilitate subsequent routing. Rather, Das teaches optimizing an already routed design to fix timing violations (negative slack) that were not resolved by the initial routing. Therefore, Das fails to teach or suggest the specific sequence of "pre-routing physical optimization based on preset parameters followed by routing" claimed in the present application.
Response:
CHEN establishes the foundation for FPGA-BASED PROTOTYPE VERIFICATION PLATFORM. As cited and presented in the argument “The invention discloses an FPGA prototype verification system generation method and system and an FPGA prototype verification method and system. The generation method comprises the steps that the whole FPGA prototype verification system is divided into a plurality of verification subsystems; each verification subsystem can perform FPGA verification of set functions and performance; and the integrated resources of each verification subsystem are downloaded to each FPGA verification subsystem to form a complete verification system.” This is all that matters for a person having ordinary skill to combine various verification sub systems to accomplish the tasks claimed in the application.
For example, with respect to Claim 1 recites "determining whether an operation result of the gate-level netlist meets a requirement defined by preset parameters, wherein the operation result comprise parameters of fanout, timing and congestion"
(Blaine, col. 4, lines 27-34 “ An example of a congestion design check is the level of fanout of a net that drives control pins in a particular congestion region. A violation can be determined based on a first threshold value for identifying high-fanout nets and a second threshold value indicating a number of high-fanout nets in the region. The severity level of the violation can be determined based on the number of high-fanout nets in the region.”)
With respect to the argument “This limitation explicitly defines the verification object as physical parameters of the gate-level netlist, distinct from functional correctness. The subject-matter of the amended Claim 1 employs a physical constraint-based iterative optimization process.”
(Blaine, col. 3, lines 53-59 “A design check is an aspect or characteristic exhibited by the circuit design that could contribute to timing failure, cause routability problems by increasing congestion, and/or violate power constraints. In most instances, the presence in the circuit design of an aspect or characteristic specified by a design check indicates a violation of the design check.”)
(Blaine, col. 3, lines 60-62 “The design checks can be categorized into classes, such as utilization, timing, design constraints, congestion and clocking.”)
(Blaine, col. 4, lines 10-12 “ An example of a timing check is the worst negative slack (WNS) of the circuit design. The violation of a WNS check can be determined based on a threshold value.”)
Blaine’s teaching is not about functional correctness but about design check consisting of physical quantities.
With respect to “For example, in contrast to the cited references, Claim 1 recites "performing, when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters, physical optimization on the gate-level netlist according to a set parameter optimization rule…”
Blaine again teaches the following:
(Blaine, col. 5, lines 42-45 “In response to the satisfaction level determined after block 114 being greater than the satisfaction threshold level, the design tool can proceed to block 104 and perform optimization processing on the circuit design.”)
(Blaine, col. 8, lines 6-10 “The synthesis and optimization phases both have threshold values of −0.250 ns, the placement and physical optimization phases both have threshold values of −0.300 ns, and the routing phase has a threshold value of −0.100 ns.”)
With respect to “and performing routing on elements in ...... the gate-level netlist subjected to the physical optimization to obtain the FPGA-based prototype verification platform."
Das discloses the following:
(Das, col. 8, lines 36-39 “Various optimization strategies 316 can be performed, such as placement optimization, routing optimization, rewiring optimization, clock optimization, retiming optimization, or the like, as well as combinations thereof.”)
With respect to “the physical optimization is performed on the gate-level netlist prior to performing routing on elements in the gate- level netlist to obtain the FPGA-based prototype verification platform.”
“And Based on the above content of Das, it is evident that Das explicitly defines its optimization process as post-route physical optimization, since the placing and routing a logical description of the circuit design is the first step performed in order to generate a physical description, and this physical description is the object to be optimized in terms of its timing paths.”
Das’s disclosure
“Techniques for opportunistic candidate path selection during physical optimization of a circuit design for an integrated circuit (IC). In an example, a method of implementing a circuit design for an integrated circuit (IC) includes placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths.”
is a comprehensive optimization considering physical, routing and timing as Das’s optimization generate a physical description having a plurality of paths, which a person having ordinary skill in the art would understand that plurality of paths is related to routing.
Argument:
For example, in contrast to the cited references, Claim 1 recites "wherein the parameter optimization rule comprises a fanout optimization rule, a timing optimization rule, and a congestion optimization rule, and correspondingly, performing, when the operation result of the gate-level netlist does not meet the requirement defined by the preset parameters, the physical optimization on the gate-level netlist according to the set parameter optimization rule comprises: calling, when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist; calling, when there is a timing violation in the operation result, a timing adjustment instruction to adjust timing of the gate-level netlist; and calling, when a congestion level in the operation result is greater than or equal to a preset level value, an alternate replication instruction to adjust the congestion level of the gate-level netlist"
With respect to the feature "the parameter optimization rule comprises a fanout optimization rule......calling, when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist", the Action references Dasasathyan and Blaine.
However, Das discloses a machine learning-based strategy selection process where "replication for very high fanout nets" is merely a pre-defined parameter setting (Directive) within a Strategy. Das selects which strategy to apply but does not teach the specific iterative control logic of: if fanout exceeds a threshold, then automatically invoke a "logical replication instruction". Das solves "what to run", whereas the present invention solves "how to automatically correct netlist topology based on real-time metrics". Furthermore, Blaine discloses an "Automated Guidance" system that presents suggested actions (e.g., via UI or scripts) based on severity levels. Blaine requires user intervention or script execution triggered by a suggestion; it does not teach an internal, automatic loop where the tool itself executes a "logical replication instruction" to modify the netlist topology upon detecting a fanout violation. The combination fails to teach the specific closed-loop, automatic instruction invocation reflected by the feature "the parameter optimization rule comprises a fanout optimization rule......calling, when a fanout in the operation result does not meet a set quantity of signal drivers, a logical replication instruction to adjust the fanout of the gate-level netlist" of the amended Claim 1.
Response:
Anyone having ordinary skill in the art would choose the strategy or strategies of Dasasathyan most relevant to the fanout optimization.
(Dasasathyan, col. 6, lines 43-51 “Another exemplary strategy can specify a directive to merge equivalent drivers in a logic optimization phase, a directive to aggressively spread the logic during a placement phase, a directive to aggressively explore different algorithms in multiple passes of physical optimization, including replication for very high fanout nets, and phase in which a subset of physical optimizations are run on the top critical paths of all endpoint clocks, regardless of slack.”)
Further,
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., automatically invoke a "logical replication instruction" ) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Argument:
With respect to the feature "the parameter optimization rule comprises a timing optimization rule......calling, when there is a timing violation in the operation result, a timing adjustment instruction to adjust timing of the gate-level netlist", the Action cites Das for timing optimization.
Specifically, Das states: "Post-route physical optimization can be used... to eliminate or mitigate timing constraint violations... by optimizing timing path(s) in the placed and routed design". This explicitly teaches post-route optimization regarding the timing constraints violations. In contrast, the amended Claim 1 recites physical optimization performed on the gate-level netlist prior to routing ("performing routing... on the gate-level netlist subjected to the physical optimization"). The present invention's physical optimization is a pre-routing step to ensure the placement is favorable for routing, whereas Das's optimization is a post-routing fix for timing closure. Das does not teach optimizing a gate-level netlist (before routing) based on timing violations to facilitate subsequent routing.
Response:
Das’s disclosure
“Techniques for opportunistic candidate path selection during physical optimization of a circuit design for an integrated circuit (IC). In an example, a method of implementing a circuit design for an integrated circuit (IC) includes placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths.”
is a comprehensive optimization considering physical, routing and timing as Das’s optimization generate a physical description having a plurality of paths, which a person having ordinary skill in the art would understand that plurality of paths is related to routing.
Argument:
With respect to the feature "the parameter optimization rule comprises a congestion optimization rule......and calling, when a congestion level in the operation result is greater than or equal to a preset level value, an alternate replication instruction to adjust the congestion level of the gate-level netlist", the Action combines Blaine and Peters.
Peters focuses on placement moves (moving existing resources) to reduce congestion cost, using an incremental congestion model. Peters never discloses replication (adding new resource instances) as a method to resolve congestion; its solution is spatial redistribution, not resource duplication. Blaine discloses "automated suggested actions" or tagging properties for replication in a later phase, which is a high-level guidance or tagging mechanism, not the direct invocation of an "alternate replication instruction" to modify the netlist. The feature "the parameter optimization rule comprises a congestion optimization rule......and calling, when a congestion level in the operation result is greater than or equal to a preset level value, an alternate replication instruction to adjust the congestion level of the gate-level netlist" specifically specifies to call an "alternate replication instruction" to adjust congestion levels. Neither Blaine nor Peters teaches the specific algorithmic step of automatically invoking a replication instruction based on a congestion threshold. Thus, the combination does not render the above feature of the amended Claim 1 obvious.
For example, in contrast to the cited references, Claim 1 recites "generating a placement file each time the physical optimization of the gate-level netlist is performed, and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization; returning, when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization, to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization"
Response:
Please refer to the respective citations presented in the rejection. A person having ordinary skill in the art would combine the teachings of Blaine and Peters to do congestion optimization based on congestion analysis as well as replication.
Argument:
With respect to the feature "returning, when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization, to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization", the Action references the following content of Das:
The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308.
That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re- compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302. (col. 8, lines 40-61)
In another example, the convergence criteria 310 can dictate that if timing performance of a path has not improved from a previous iteration, then that timing path is excluded from the candidate timing paths 312. Timing performance (col. 8, lines 62-65)
Based on the above content, it is evident that Das explicitly teaches excluding timing paths from the candidate set when performance does not improve (Das, Col. 9, Lines 13-26: "timing path is considered 'timing-congested'... can exclude timing-congested paths from the candidate paths"). This exclusion logic is designed to skip unproductive paths and proceed to the next optimization target or terminate, thereby moving forward in the optimization process. Thus, Das teaches a "forward-only" iterative optimization that excludes unimproved paths to accelerate convergence. Das does not teach restoring a previous physical layout.
In contrast to Das, Claim 1 recites "returning, when the parameters in the operation result generated after a latest physical optimization are greater than or equal to the parameters in the operation result generated after an immediately previous physical optimization, to a placement phase of the immediately previous physical optimization based on the placement file generated after the immediately previous physical optimization", that is, the logic returns to a previous placement phase based on a saved placement file when parameters worsen or stagnate. This "rollback" logic serves to prevent optimization degradation by reverting the physical state, which is fundamentally different from Das's path exclusion. Das's "exclusion" affects only the selection of future optimization targets, not the modification of the already-applied physical layout, whereas the claimed invention employs a "rollback" mechanism to restore previous states.
Response:
Proper interpretation of Das’s work is identified below in bold.
(Das, col. 8, lines 40-61 “The physical optimization process performed by the physical optimization module 218 can repeat for one or more iterations. At the end any iteration, the candidate selection module 220 can optionally invoke the timing analysis module 216 to re-compute the timing profile 308. That is, the timing analysis module 216 can be invoked after each iteration or after a plurality of iterations. In an example, when invoked, the timing analysis module 216 can re-compute timing of the entire circuit design. Alternatively, when invoked, the timing analysis module 216 can employ an incremental timing analysis that builds on results of the previous timing analysis. The candidate selection module 220 includes convergence criteria 310 that controls when the physical optimization process is complete. In general, the candidate selection module 220 continues invoking the physical optimization module 218 and optionally the timing analysis module 216 until there are no more candidate timing paths 312. In one example, the convergence criteria 310 can dictate that physical optimization is complete if there are no more timing paths with negative slack in the physical description 302. This results in the most optimum physical optimization of the physical description 302.”)
Note, as mentioned earlier, Das’s physical optimization is a comprehensive one considering of placement, routing and timing, and identifying plurality of paths for timing analysis. A person having ordinary skill in the art would exclude the path that does not improve time in the next iteration, as Das does.
Argument:
With respect to the feature "generating a placement file each time the physical optimization of the gate-level netlist is performed, and calling a report generation instruction to generate a corresponding operation result for the gate-level netlist subjected to the physical optimization", the Action references the following content of Dasasathyan:
training set using the default strategy. The implementation flow process can be performed by one or more circuit design tools (collectively, "circuit design tool") that perform netlist optimization, placement, physical synthesis, and routing. The implementation flow outputs circuit implementation data and run data. (col. 5, line 66-col. 6, line 4)
Dasasathyan is relied upon for "generating a placement file", and the above portion of Dasasathyan describes an implementation flow that outputs final "circuit implementation data and run data". Dasasathyan does not disclose generating a specific placement file snapshot each time a physical optimization iteration is performed, nor does it teach calling a report generation instruction to trigger this generation. Dasasathyan’s "run data" refers to final metrics, not intermediate placement state files generated via explicit instructions. The claimed feature requires active state saving and reporting at every iteration step to enable the rollback logic, which is absent in Dasasathyan.
Therefore, neither Das nor Dasasathyan teaches or suggests the specific combination of generating placement files per optimization iteration, calling report generation instructions, and rolling back to previous states when parameters degrade. The combination of these features is not obvious.
Response:
(Dasasathyan, col. 9, lines 49-55 “At block 414, the data resulting from the runs of the implementation flow using the K strategies is analyzed to determine whether or not the targeted metric improved enough to satisfy the design constraints. If the design constraints are satisfied, the implementation data from one of the runs can be selected and further processed to generate data that is suitable for making an integrated circuit.”)
(Dasasathyan, col. 6, lines 5-13 “The implementation data can specify characteristics of the target device on which the design is to be implemented, netlist features, the circuit structures (e.g., “primitives”) to be used in making an operable circuit, connections between the circuit structures, etc. The run data can include data such as wirelength after global placement, the congestion after an initial routing, the WNS after placement, the improvement seen in physical synthesis, the time spent routing the circuit design, etc.”)
“the implementation data from one of the runs can be selected” indicates that Multiple placement files are saved in the system.
Argument
It follows that the applied art does not disclose or suggest all of the features and relationships recited in Claim 1, as well as the corresponding subject matter recited in Claims 8 and 9. Thus the Office Action has not established a case of primafacie obviousness. Further the Office Action has not established an apparent reason to modify the applied art to include this recited subject matter which is missing from the applied art.
Response
A person having ordinary skill in the art to which the claimed invention pertains would have for the purpose of having a comprehensive tool for formal verification of circuit design, design rule check for all different violations, and for doing optimization would combine the teachings of CHEN, Blaine, Das, Dasasathyan, Peters, and Teig to produce such a tool.
Applicant’s arguments regarding the remaining dependent claims have been fully considered but are not persuasive for the reasons stated above
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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