Prosecution Insights
Last updated: April 19, 2026
Application No. 18/260,140

SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Jun 30, 2023
Examiner
AHMED, SHAHED
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Csmc Technologies Fab2 Co. Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
91%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
866 granted / 955 resolved
+22.7% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
45 currently pending
Career history
1000
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 955 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to application No. 18260140 filed on 06/30/2023. Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Priority Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Election/Restrictions Applicant’s election without traverse of claims 1-11, 13-15 in the reply filed on 10/29/2025 is acknowledged. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections Claim 10 is objected to because it contains the limitation “a geometric center of the an outer contour of the drift region”. To avoid typographical error the examiner recommends amending the claim to recite “a geometric center of Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites the limitation “source doped regions having the second conductivity type”. The metes and bounds of the claimed limitation can not be determined for the following reasons: The highlighted term lacks proper antecedent basis. Claim 2-11, 13-15 are also rejected under 112(b) as they depend on base claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-11, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Mun et al. (US 2019/0259829). Regarding Independent claim 1, Mun et al. teach a semiconductor device, comprising: a substrate (Figs. 2a-2c, element 210, paragraph 0015 discloses p type) having a first conductivity type; a shallow trench isolation (STI) structure (Figs. 2a-2c, element 280, paragraph 0022) disposed in the substrate, wherein a portion of the substrate surrounded by the STI structure serves as an active area (paragraph 0022); a drain doped region (Figs. 2a-2c, element 250, paragraph 0030 discloses n type) disposed at a top of a central portion of the active area and having a second conductivity type that is opposite to the first conductivity type; source doped regions (Figs. 2a-2c, elements 252, paragraph 0030 discloses n type) having the second conductivity type, wherein the source doped regions are disposed an the top of the active area on opposite sides of the drain doped region and are spaced apart from the drain doped region, and wherein a line connecting the drain doped region and the source doped regions defines a first direction, and a second direction is defined to be perpendicular to the first direction in a plane of the substrate (Figs. 2a-2c); a field oxide layer (Figs. 2a-2c, element 246, paragraph 0027) disposed over a top surface of the substrate within the active area, the field oxide layer being in a form of a second ring-like structure (Fig. 2a) and surrounding the drain doped region, wherein an outer boundary of the field oxide layer is spaced from the STI structure by a predetermined distance that is greater than 0 (Figs. 2a-2c); a gate polysilicon (Figs. 2a-2c, element 244, paragraph 0028) that is disposed over the top surface of the substrate and is in a form of a third ring-like structure surrounding the field oxide layer (Fig. 2a), wherein the gate polysilicon extends in the first direction from a position over the source doped regions to a position over the field oxide layer (Figs. 2a-2c), wherein the gate polysilicon extends in the second direction from a position over the STI structure to a position over the field oxide layer (Figs. 2a-2c, the gate polysilicon 244 extends at a level above the STI 280 and field oxide layer 246) , and wherein a gate oxide layer (Figs. 2a-2c, element 242, paragraph 0028) is provided between the gate polysilicon and the substrate; and a drift region (Figs. 2a-2c, element 230, paragraph 0039) having the second conductivity type, wherein the drift region is disposed in the substrate, surrounds the drain doped region and is spaced apart from the source doped regions (Figs. 2a-2c), and wherein the drift region extends in the second direction to a position under the STI structure (Figs. 2a-2c, the drift region 230 extends below a depth level of STI 280). Mun et al. do not explicitly disclose a shallow trench isolation (STI) structure in a form of a first ring-like structure. Mun et al. discloses the capability of forming ring like structures for the thermal oxide region 246 (Figs. 2a-2C, paragraph 0027). Accordingly, it would have been within the grasp of one of ordinary skill in the art before the effective filling date of the invention to design the STI structure in a ring like shape absent persuasive evidence that the particular shape of the claimed limitation was significant, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04. Regarding claim 2, Mun et al. teach wherein a portion of the active area extending in the second direction acts as a withstand voltage region of the device; and a portion of the active area extending in the first direction between the drain doped region and the source doped regions serves as an operating and withstand voltage region of the device (This is an intended use recitation. The examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. See, e.g., In re Schreiber, 128 F.3d 1473, 1477, 44 USPQ2d 1429, 1431 (Fed. Cir. 1997); In re Otto, 136 USPQ 458,459 (CCPA 1963)). Regarding claim 3, Mun et al. teach wherein a length of the field oxide layer in the first direction is smaller than a length of the field oxide layer in the second direction (Figs. 2a-2c). Regarding claim 4, Mun et al. teach wherein a length of the gate polysilicon in the first direction is smaller than a length of the gate polysilicon in the second direction (Figs. 2a-2c). Regarding claim 5, Mun et al. teach wherein in the second direction, the predetermined distance from the outer boundary of the field oxide layer to the STI structure ranges from 0.5 μm to 0.8 μm (paragraph 0036 discloses that the channel length has a range and can be adjusted which would also effect the distance between the field oxide layer and the STI. Accordingly, the distance is a result effective variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the distance and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed distance). Regarding claim 6, Mun et al. teach wherein each of the second ring-like structure and the third ring-like structure is an octagon (Fig. 2a). Regarding claim 7, Mun et al. teach wherein an outer contour of the drift region is an octagon in the plane of the substrate (Mun et al. discloses the capability of forming an octagon (Figs. 2a-2C). Accordingly, it would have been within the grasp of one of ordinary skill in the art before the effective filling date of the invention to design the drift region as an octagon absent persuasive evidence that the particular shape of the claimed limitation was significant, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04. Regarding claim 8, Mun et al. teach wherein the field oxide layer is formed over the drift region and an outer boundary of the drift region completely encircles and surrounds the outer boundary of the field oxide layer (Figs. 2a-2c). Regarding claim 9, Mun et al. teach wherein in the plane of the substrate, the source doped regions on opposite sides of the drain doped region are arranged in an axial symmetry with respect to the drain doped region (Figs. 2a-2c). Regarding claim 10, Mun et al. teach wherein the plane of the substrate is a horizontal plane, and wherein a geometric center of the first ring-like structure, a geometric center of the second ring-like structure, a geometric center of the third ring-like structure and a geometric center of the an outer contour of the drift region are in coincidence in the horizontal plane (Figs. 2a-2c). Regarding claim 11, Mun et al. teach wherein the field oxide layer is a local oxidation of silicon (LOCOS) field oxide layer (paragraph 0027). Regarding claim 13, Mun et al. teach wherein a critical dimension of the active area in the second direction is greater than a critical dimension of the active area in the first direction (Figs. 2a-2c). Regarding claim 14, Mun et al. teach wherein a substrate pickup structure (Figs. 2a-2c, element 254, paragraph 0037 discloses p type) is disposed at an outer side of the source doped regions, wherein the substrate pickup structure has a same conductivity type as a conductivity type of the substrate. Regarding claim 15, Mun et al. teach wherein the semiconductor device is an N-type laterally-double diffused metal-oxide semiconductor (NLDMOS) device (paragraph 0030) with a withstand voltage requirement equal to or greater than 100 V (paragraph 0021). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAHED AHMED/ Primary Examiner, Art Unit 2813
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Prosecution Timeline

Jun 30, 2023
Application Filed
Dec 17, 2025
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
91%
With Interview (+0.0%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 955 resolved cases by this examiner. Grant probability derived from career allow rate.

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