DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 04/08/2026 is acknowledged. The traversal is on the grounds that the application is a 371 so the restriction is improper. This is persuasive so the restriction is withdrawn.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202111529029.5, filed on 12/14/2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/04/2023 and 06/10/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities: patterning the the first source-drain layer. Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 4 recites the limitation "the third recess" in page 4 line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Jung et al.; US 11,177,282 B2; 07/2020
Claim 1: Basu discloses a method for manufacturing a semiconductor device ( Fig. 10A: wafer 100 ), comprising: providing a substrate ( Fig. 10A: substrate 10 ); providing a first source-drain layer ( Fig. 10A: first source contact 11 ) , a channel layer ( Fig. 10A: channel layer 13 ), a second source-drain layer ( Fig. 10A: first drain contact 15 ) , a gate dielectric layer ( Fig. 10A: gate dielectric layer 43 ), and a gate structure ( Fig. 10A: gate dielectric layer 43 and gate electrode 55 ), wherein: the first source-drain layer ( Fig. 10A #11 ), the channel layer ( Fig. 10A #13 ), and the second source-drain layer ( Fig. 10A #15 ) are stacked on the substrate ( Fig. 10A #10 ) in the above-listed sequence ( as shown in Fig. 10A ), both the gate dielectric layer ( Fig. 10A #43 ) and the gate structure ( Fig. 10A #43 and #55 ) surround the channel layer ( Fig. 10A #13 ) laterally forming a spacer layer ( Fig. 10A #32 ) and a first contact structure ( Fig. 10A: contact metal 88 ) contacting the gate structure ( Fig. 10A: #43 and #55 ).
Basu does not appear to disclose the first contact structure comprises a first portion and a second portion which are vertically aligned, the first portion contacts the gate structure and the second portion contacts the first portion, and a lateral dimension of the first portion is different from a lateral dimension of the second portion; and the spacer layer is located at an outer sidewall of the gate structure and an outer sidewall of the first portion.
However, Jung teaches the first contact structure ( Fig. 2C #140 and #150 ) comprises a first portion ( Fig. 2C #150 ) and a second portion ( Fig. 2C #140 ) which are vertically aligned ( as shown in Fig. 2C ), the first portion ( Fig. 2C #150 ) contacts the gate structure ( Fig. 2C: center of the pad 110p ) and the second portion ( Fig. 2C #140 ) contacts the first portion ( Fig. 2C #150 ), and a lateral dimension of the first portion is different from a lateral dimension of the second portion ( as shown in Fig. 2C ); and the spacer layer ( Fig. 2B insulating spacers SP ) is located at an outer sidewall of the gate structure ( Col. 4 lines 61 – 63 A dummy gate insulating layer DGI may be provided between the dummy lower semiconductor pattern DLS and the bottommost conductive pattern 110 ) and an outer sidewall of the first portion ( Fig. 2C #150 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jung with Basu to implement the first contact structure comprises a first portion and a second portion which are vertically aligned, the first portion contacts the gate structure and the second portion contacts the first portion, and a lateral dimension of the first portion is different from a lateral dimension of the second portion; and the spacer layer is located at an outer sidewall of the gate structure and an outer sidewall of the first portion because this approach can minimize resistance, reduce parasitics, and provide uniform current distribution.
Claims 2 is rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Jung et al.; US 11,177,282 B2; 07/2020 as it relates to claim 1 above and further in view of Li et al.; US 2018/0337243 A1; 05/2018 and Jin; US 2024/0250087 A1; 05/2021
Claim 2: Basu and Jung disclose the method according to claim 1 ( as discussed above).
Neither Basu nor Jung appear to disclose the gate structure comprises a third portion extending laterally and a fourth portion extending upward from a periphery of the first portion; and providing the first source-drain layer, the channel layer, the second source-drain layer, the gate dielectric layer, and the gate structure comprises: forming a first dielectric layer surrounding the first source-drain layer at a sidewall of the first source-drain layer, and forming a second dielectric layer surrounding the second source-drain layer at a sidewall of the second source-drain layer; forming the gate dielectric layer and the gate structure in a first recess; wherein the first recess is formed by a sidewall of the channel layer with respect to the first dielectric layer and the second dielectric layer; wherein the fourth portion extending upward reaches a sidewall of the second dielectric layer, and the fourth portion is formed before forming the spacer layer at the outer sidewall of the gate structure.
Li discloses the gate structure ( Fig. 10: first gate 304 ) comprises a third portion ( Fig. 4C third portion 234 ) extending laterally ( as shown in Fig. 4C ) and a fourth portion ( Fig. 4C: 244 ) extending upward ( [0048] The first oxide layer in this implementation may include the first portion 214, the second portion 224, the third portion 234, and the fourth portion 244 ) from a periphery of the first portion ( Fig. 10: first portion 214 ); forming the gate dielectric layer ( Fig. 19: gate dielectric layer 303 ) and the gate structure ( Fig. 10 #304 ) in a first recess ( Fig. 5A: first recess 205 ); wherein the first recess ( Fig. 5A #205 ) is formed by a sidewall of the channel layer ( Fig. 5A: first fin 202 ) with respect to the first dielectric layer ( Fig. 5A: first dielectric layer 213 ) and the second dielectric layer ( Fig. 11: second dielectric layer 413 ); wherein the fourth portion ( Fig. 4C #244 ) extending upward ( Fig. 11: first pseudo gate structure extends upward ) reaches a sidewall ( as shown in Fig. 11 ) of the second dielectric layer ( Fig. 11 #413 ), and the fourth portion is formed before forming the spacer layer at the outer sidewall of the gate structure.
Li does not appear to disclose the first source-drain layer, the channel layer, the second source-drain layer, the gate dielectric layer and the gate structure comprises: forming a first dielectric layer surrounding the first source-drain layer at a sidewall of the first source-drain layer, and forming a second dielectric layer surrounding the second source-drain layer at a sidewall of the second source-drain layer.
However, Jin teaches the first source-drain layer ( Fig. 9: first source/drain doped layer 207 ), the channel layer ( [0141] The operation method includes applying a voltage to the first electrical interconnection structure to turn off the channel region at the bottom of the first gate structure 211 ), the second source-drain layer ( Fig. 9: second source/drain doped layer 208 ), the gate dielectric layer ( Fig. 11: first dielectric layer 209 ), and the gate structure ( Fig. 9: first dummy gate structure 204 ) comprises: forming a first dielectric layer ( [0075] forming a first dielectric layer 209 on the substrate 200 ) surrounding the first source-drain layer at a sidewall of the first source-drain layer ( [0075] The first dielectric layer 209 covers sidewalls of the first dummy gate structure 20, the second dummy gate structure 206 and the third dummy gate structure 206 ), and forming a second dielectric layer ( [0086] a second dielectric layer 216 is formed on the first dielectric layer 209, the first gate structure 211, the second gate structure 212, and the third gate structure 213 ) surrounding the second source-drain layer ( Fig. 10 #208 ) at a sidewall of the second source-drain layer ( as shown in Fig. 12 #209 is at a sidewall of #208 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jin with Basu, Jung and Li to implement the first source-drain layer, the channel layer, the second source-drain layer, the gate dielectric layer and the gate structure comprises: forming a first dielectric layer surrounding the first source-drain layer at a sidewall of the first source-drain layer, and forming a second dielectric layer surrounding the second source-drain layer at a sidewall of the second source-drain layer because this approach can optimize both electrical performance and manufacturability.
Claim 3 is rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Jung et al.; US 11,177,282 B2; 07/2020, Li et al.; US 2018/0337243 A1; 05/2018 and Jin; US 2024/0250087 A1; 05/2021 as it relates to claim 2 above and further in view of Wang et al.; US 2021/0296318 A1; 03/2020
Claim 3: Basu, Jung, Li and Jin disclose the method according to claim 2 ( as discussed above).
Neither Basu nor Jung nor Jin appear to disclose the gate structure further comprises a fifth portion extending downward and reaching the sidewall of the first dielectric layer.
However, Wang (‘318 ) teaches the gate structure ( Fig. 1A gate structures 116 ) further comprises a fifth portion ( Fig. 1A fifth portion of the first gate structure 116a ) extending downward and reaching the sidewall of the first dielectric layer ( Fig. 1A isolation structure 108; [0029] the isolation structure 108 may comprise, for example, an oxide, a nitride, an oxy-nitride, some other dielectric material, or a combination of the foregoing ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang (‘318 ) with Basu, Jung, Li, and Jin to implement the gate structure further comprises a fifth portion extending downward and reaching the sidewall of the first dielectric layer because this approach can control short channel effects.
Claim 4 is rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Jung et al.; US 11,177,282 B2; 07/2020, Li et al.; US 2018/0337243 A1; 05/2018 and Jin; US 2024/0250087 A1; 05/2021 as it relates to claim 2 above and further in view of Wang et al.; US 2022/0036935 A1; 11/2020
Claim 4: Basu, Jung, Li and Jin disclose the method according to claim 2 ( as discussed above).
Neither Basu nor Jung nor Li appear to disclose before forming the first dielectric layer and forming the second dielectric layer, providing the first source-drain layer, the channel layer, the second source-drain layer, the gate dielectric layer, and the gate structure comprises: stacking the first source-drain layer, the channel layer, and the second source- drain layer sequentially on the substrate; patterning the first source-drain layer, the channel layer, and the second source-drain layer through etching; and forming the first dielectric layer and forming the second dielectric layer comprises: etching the channel layer from the sidewall of the channel layer to obtain a second recess, where a third recess is formed by a sidewall of the etched channel layer with respect to the first source-drain layer and the second source-drain layer; forming a dummy gate structure in the second recess; etching the first source-drain layer from the sidewall of the first source-drain layer to obtain a third recess, wherein the third recess is formed by a sidewall of the etched first source-drain layer with respect to the dummy gate structure; etching the second source-drain layer from the sidewall of the second source- drain layer to obtain a fourth recess, wherein the fourth recess is formed by a sidewall of the etched second source-drain layer with respect to the dummy gate structure; forming the first dielectric layer in the third recess; and forming the second dielectric layer in the fourth recess.
Jin discloses before forming the first dielectric layer ( [0075] forming a first dielectric layer 209 on the substrate 200 ) and forming the second dielectric layer ( [0086] a second dielectric layer 216 is formed on the first dielectric layer 209, the first gate structure 211, the second gate structure 212, and the third gate structure 213 ), providing the first source-drain layer ( Fig. 9: first source/drain doped layer 207 ), the channel layer ( [0141] The operation method includes applying a voltage to the first electrical interconnection structure to turn off the channel region at the bottom of the first gate structure 211 ), the second source-drain layer ( Fig. 9: second source/drain doped layer 208 ), the gate dielectric layer ( Fig. 11: first dielectric layer 209 ), and the gate structure ( Fig. 9: first dummy gate structure 204 ) comprises: stacking the first source-drain layer ( Fig. 9 #207 ), the channel layer ( as discussed above ), and the second source- drain layer ( Fig. 9 #208 ) sequentially on the substrate ( Fig. 9 #200 ); patterning the first source-drain layer ( [0071] etching the first fins 201 by using the first dummy gate structure 204 and the second dummy gate structure 205 as a mask to form a plurality of first source/drain openings in the first fins 201 (not marked)), the channel layer ( as discussed above), and the second source-drain layer ( Fig. 9 #208 ) through etching ( [0071] etching the second fins 202 by using the third dummy gate structure 206 as a mask to form a plurality of second source/drain openings (not marked) in the second fins 202 ); and forming the first dielectric layer ( [0075] forming a first dielectric layer 209 on the substrate 200 ) and forming the second dielectric layer ( [0086] a second dielectric layer 216 is formed on the first dielectric layer 209 ) comprises:
Jin does not appear to disclose etching the channel layer from the sidewall of the channel layer to obtain a second recess, where a third recess is formed by a sidewall of the etched channel layer with respect to the first source-drain layer and the second source-drain layer; forming a dummy gate structure in the second recess; etching the first source-drain layer from the sidewall of the first source-drain layer to obtain a third recess, wherein the third recess is formed by a sidewall of the etched first source-drain layer with respect to the dummy gate structure; etching the second source-drain layer from the sidewall of the second source- drain layer to obtain a fourth recess, wherein the fourth recess is formed by a sidewall of the etched second source-drain layer with respect to the dummy gate structure; forming the first dielectric layer in the third recess; and forming the second dielectric layer in the fourth recess.
However, Wang (‘935) teaches etching the channel layer ( Fig. 13B channel region 68 ) from the sidewall of the channel layer to obtain a second recess ( [0043] FIGS. 13A and 13B, the dummy gates 72, and the masks 74 if present, are removed in an etching step(s), so that second recesses 98 are formed ), where a third recess ( Fig. 15B: third recesses 103 ) is formed by a sidewall of the etched channel layer with respect to the first source-drain layer ( Fig. 15B source/drain region 92 center ) and the second source-drain layer ( Fig. 15B source/drain region 92 on the left side ); forming a dummy gate structure in the second recess ( Fig. 12B dummy gate 72 ); etching the first source-drain layer ( Fig. 15B #92 center ) from the sidewall of the first source-drain layer ( Fig. 15B #92 center ) to obtain a third recess ( [0049] In FIGS. 15A and 15B, the gate stacks (including the gate dielectric layers 100 and the gate electrodes 102) are recessed, so that third recesses 103 are formed directly over the gate stack and between opposing portions of first spacers 81 ), wherein the third recess ( as discussed above ) is formed by a sidewall of the etched first source-drain layer ( Fig. 15B #92 ) with respect to the dummy gate structure ( Fig. 12B #72 ); etching the second source-drain layer ( Fig. 15B #92 left side ) from the sidewall of the second source- drain layer ( Fig. 15B #92 left side ) to obtain a fourth recess ( [0051] In FIGS. 17A and 17B, fourth recesses 105 are patterned through the first dielectric layer 104. The fourth recesses 105 may be patterned in the first dielectric layer 104 through a combination of photolithography and etching ), wherein the fourth recess ( Fig. 17B #105 ) is formed by a sidewall of the etched second source-drain layer ( as shown in Fig. 17B ) with respect to the dummy gate structure ( Fig. 12B #72 ); forming the first dielectric layer ( Fig. 16B #104 ) in the third recess ( Fig. 15B #103 ); and forming the second dielectric layer ( Fig. 20B memory film 110 )in the fourth recess ( Fig. 17B #105 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang (‘935 ) with Basu, Jung, Li, and Jin to implement etching the channel layer from the sidewall of the channel layer to obtain a second recess, where a third recess is formed by a sidewall of the etched channel layer with respect to the first source-drain layer and the second source-drain layer; forming a dummy gate structure in the second recess; etching the first source-drain layer from the sidewall of the first source-drain layer to obtain a third recess, wherein the third recess is formed by a sidewall of the etched first source-drain layer with respect to the dummy gate structure; etching the second source-drain layer from the sidewall of the second source- drain layer to obtain a fourth recess, wherein the fourth recess is formed by a sidewall of the etched second source-drain layer with respect to the dummy gate structure; forming the first dielectric layer in the third recess; and forming the second dielectric layer in the fourth recess because this approach allows for the creation of precise 3D features.
Claim 5 is rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Jung et al.; US 11,177,282 B2; 07/2020 as it relates to claim 1 above and further in view of Li et al.; US 2018/0337243 A1; 05/2018
Claim 5: Basu and Jung disclose the method according to claim 1 ( as discussed above).
Basu discloses providing the first source-drain layer ( Fig. 10A: first source contact 11 ), the channel layer ( Fig. 10A: channel layer 13 ), the second source-drain layer ( Fig. 10A: second source contact 12 ), the gate dielectric layer ( Fig. 10A: gate dielectric layer 43 ), and the gate structure ( Fig. 10A: gate dielectric layer 43 and gate electrode 55 ) comprises:
Neither Basu nor Jung appear to disclose the gate structure comprises a third portion extending laterally and a fourth portion extending upward from a periphery of the first portion; forming the gate dielectric layer and the gate structure in a second recess, wherein: the second recess is formed by a sidewall of the channel layer with respect to the first source-drain layer and the second source-drain layer; wherein the fourth portion extending upward reaches the sidewall of the second source- drain layer, and the fourth portion is formed before forming the spacer layer at the outer sidewall of the gate structure; a lower surface of the gate structure is higher than an upper surface of the first source- drain layer; and wherein before forming the sacrificial structure covering the gate structure, the method further comprises: forming an isolation layer on the sidewall of the second source-drain layer.
However, Li teaches the gate structure ( Fig. 10: first gate 304 ) comprises a third portion ( Fig. 4C third portion 234 ) extending laterally ( as shown in Fig. 4C ) and a fourth portion ( Fig. 4C: 244 ) extending upward ( [0048] The first oxide layer in this implementation may include the first portion 214, the second portion 224, the third portion 234, and the fourth portion 244 ) from a periphery of the first portion ( Fig. 10: first portion 214 ); forming the gate dielectric layer ( Fig. 19: gate dielectric layer 303 ) and the gate structure in a second recess ( Fig. 5A: second recess 206 ); wherein the second recess ( Fig. 5A #206 ) is formed by a sidewall of the channel layer ( Fig. 5A: first fin 202 ) with respect to the first source-drain layer ( Fig. 6A: first source region 207 ) and the second source-drain layer ( Fig. 6A: first drain region 208 ); wherein the fourth portion ( Fig. 4C #244 ) extending upward ( Fig. 11 first pseudo gate structure extends upward ) reaches a sidewall ( as shown in Fig. 11 ) of the second source-drain layer ( Fig. 6A #208 ), and the fourth portion ( Fig. 4C #244 ) is formed before forming the spacer layer ( Fig. 4C first spacer layer 243 ) at the outer sidewall of the gate structure ( as shown in Fig. 4C ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Basu, and Jung to implement the gate structure comprises a third portion extending laterally and a fourth portion extending upward from a periphery of the first portion; forming the gate dielectric layer and the gate structure in a second recess, wherein: the second recess is formed by a sidewall of the channel layer with respect to the first source-drain layer and the second source-drain layer; wherein the fourth portion extending upward reaches the sidewall of the second source- drain layer, and the fourth portion is formed before forming the spacer layer at the outer sidewall of the gate structure; a lower surface of the gate structure is higher than an upper surface of the first source- drain layer; and wherein before forming the sacrificial structure covering the gate structure, the method further comprises: forming an isolation layer on the sidewall of the second source-drain layer because this approach provides electrical performance enhancement and also is tied to manufacturing integration constraints.
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Zhang; US 12,438,090 B2; 09/2021
Claim 8: Basu discloses a semiconductor device ( Fig. 10A: wafer 100 ), comprising: a first source-drain layer ( Fig. 10A: first source contact 11 ), a channel layer ( Fig. 10A: channel layer 13 ), a second source-drain layer ( Fig. 10A: first drain contact 15 ), which are stacked on a substrate ( Fig. 10A substrate 10 ) in the above-listed sequence; a gate dielectric layer ( Fig. 10A: gate dielectric layer 43 ) and a gate structure ( Fig. 10A #43 and #55 ), both of which surround the channel layer laterally ( Fig. 10A #13 is surrounded laterally by the gate structure ), where the gate structure extends laterally ( Fig. 10A #43 and #55 extend laterally and vertically from the substrate ); a first contact structure ( Fig. 10A: contact metal 88 and 15 ) contacting the gate structure ( Fig. 10A #55 ), wherein the first contact structure ( Fig. 10A #88 ) comprises a first portion ( Fig. 10A #88 on the left and right of the center portion ) and a second portion ( Fig. 10A #88 in the center of the substrate ) which are vertically aligned ( as shown in Fig. 10A ), the first portion ( Fig. 10A #88 on the left and right side of the center portion ) contacts the gate structure ( Fig. 10A #55 ) and a lateral dimension of the first portion ( Fig. 10B outer ring of 88 ) is different from a lateral dimension of the second portion ( Fig. 10B inner portion of 88 ) ; and a spacer layer ( Fig. 10A: spacer 62 ) , located at an outer sidewall of the gate structure ( as shown in Fig. 10A ) and an outer sidewall of the first portion ( Fig. 10A #88 on the left and right side of the center portion ).
Basu does not appear to disclose the second portion contacts the first portion.
However, Zhang teaches the second portion ( Fig. 2 contact structures 215 upper portion ) contacts the first portion ( Fig. 2 contact structures 215 lower portion).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Basu to implement the second portion contacts the first portion because this approach can reduce contact resistance and also accommodate junction or doping profiles.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Zhang; US 12,438,090 B2; 09/2021 as it relates to claim 8 above and further in view of Jin; US 2024/0250087 A1; 05/2021
Claim 9: Basu and Zhang disclose the semiconductor device according to claim 8 ( as discussed above ).
Neither Basu or appear to disclose a first dielectric layer surrounding the first source-drain layer, wherein the first dielectric layer is located at a sidewall of the first source-drain layer; a second dielectric layer surrounding the second source-drain layer, wherein the first dielectric layer is located at a sidewall of the second source-drain layer; wherein: a first recess is formed by a sidewall of the channel layer with respect to the first dielectric layer and the second dielectric layer; the gate dielectric layer and the gate structure are located in the first recess; and the first portion is located at a sidewall of the second dielectric layer.
Jin discloses a first dielectric layer ( Fig. 11: first dielectric layer 209 ) surrounding the first source-drain layer ( Fig. 11: first source/drain doped layer 207 ), wherein the first dielectric layer ( Fig. 11 #209 ) is located at a sidewall ( as shown in Fig. 11 ) of the first source-drain layer ( Fig. 11 #207 ); a second dielectric layer ( Fig. 18: second dielectric layer 216 ) surrounding the second source-drain layer ( Fig. 17: second source/drain layer 208 ), wherein the first dielectric layer ( Fig. 17 #209 ) is located at a sidewall ( as shown in Fig. 17 ) of the second source-drain layer ( Fig. 17 #208 ).
Jin does not appear to disclose a first recess is formed by a sidewall of the channel layer with respect to the first dielectric layer and the second dielectric layer; the gate dielectric layer and the gate structure are located in the first recess; and the first portion is located at a sidewall of the second dielectric layer.
However, Li teaches a first recess ( Fig. 5A: first recess 205 ) is formed by a sidewall of the channel layer ( Fig. 5A: first fin 202 ) with respect to the first dielectric layer ( Fig. 5A: first dielectric layer 213 ) and the second dielectric layer ( Fig. 11: second dielectric layer 413 ); the gate dielectric layer ( Fig. 10: gate dielectric layer 303 ) and the gate structure ( Fig. 10: first gate 304 ) are located in the first recess ( Fig. 5A #205 ); and the first portion (Fig. 12: first portion 214 ) is located at a sidewall of the second dielectric layer ( [0065] The oxidization process not only forms a first portion 214 of a first oxide layer, but also oxidizes a surface of the second fin 402 below an edge of the second dielectric layer 413 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Basu, Zhang, and Jin to implement a first dielectric layer surrounding the first source-drain layer, wherein the first dielectric layer is located at a sidewall of the first source-drain layer; a second dielectric layer surrounding the second source-drain layer, wherein the first dielectric layer is located at a sidewall of the second source-drain layer; wherein: a first recess is formed by a sidewall of the channel layer with respect to the first dielectric layer and the second dielectric layer; the gate dielectric layer and the gate structure are located in the first recess; and the first portion is located at a sidewall of the second dielectric layer because this can provide electrical insulation and isolation and also provide mechanical and chemical protection.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Zhang; US 12,438,090 B2; 09/2021 as it relates to claim 8 above and further in view of Li et al.; US 2018/0337243 A1; 05/2018
Claim 10: Basu and Zhang disclose the semiconductor device according to claim 8 ( as discussed above ).
Neither Basu nor Zhang appear to disclose a second recess is formed by a sidewall of the channel layer with respect to the first source-drain layer and the second source-drain layer; the gate dielectric layer and the gate structure are located in the second recess; a lower surface of the gate structure is higher than an upper surface of the first source- drain layer; and an isolation layer is formed between the second source-drain layer and the first portion.
However, Li teaches a second recess ( Fig. 5A: second recess 206 ) is formed by a sidewall of the channel layer ( Fig. 5A: first fin 202 ) with respect to the first source-drain layer ( Fig. 6A first source region 207 ) and the second source-drain layer ( Fig. 6A: first drain region 208 ); the gate dielectric layer ( Fig. 19: gate dielectric layer 303 ) and the gate structure (Fig. 11: gate structure 403 ) are located in the second recess ( Fig. 5A #206 ); a lower surface of the gate structure ( Fig. 14 #403 ) is higher than an upper surface of the first source-drain layer ( as shown in Fig. 14 #403 is higher than #207 ); and an isolation layer ( Fig. 10: first dielectric layer 213 ) is formed between the second source-drain layer ( Fig. 14 #208 ) and the first portion ( Fig. 10: first portion 214 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Basu, and Zhang to implement a second recess is formed by a sidewall of the channel layer with respect to the first source-drain layer and the second source-drain layer; the gate dielectric layer and the gate structure are located in the second recess; a lower surface of the gate structure is higher than an upper surface of the first source- drain layer; and an isolation layer is formed between the second source-drain layer and the first portion because this approach can be used to control source/drain dopant profiles along with electrical isolation and etch stop.
Claim 15 – 17 are rejected under U.S.C. 103 as being unpatentable over Basu et al.; US 9,287,362 B1; 11/2014 in view of Jung et al.; US 11,177,282 B2; 07/2020 as it relates to claim 1 above and further in view of Xu et al.; US 2024/0258238 A1; 05/2021
Claim 15: Basu and Jung disclose the method according to claim 1 ( as discussed above ).
Basu teaches forming the spacer layer ( Fig. 10A #32 ) and the first contact structure ( Fig. 10A: contact metal 88 ) contacting the gate structure ( Fig. 10A #43 and #55 ) comprises: forming the spacer layer ( Fig. 10A #32 ) at the outer sidewall of the gate structure ( Fig. 10A #43 and #55 ) ;
Basu does not appear to disclose etching the gate structure to reduce a vertical dimension of the gate structure; forming a sacrificial structure covering the etched gate structure, and forming a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer; etching the capping layer to obtain a first contact hole reaching the sacrificial structure; removing the sacrificial structure at a bottom of the first contact hole to form a gap under the first contact hole; and forming a first contact structure in the first contact hole and the gap.
Xu teaches etching the gate structure to reduce a vertical dimension of the gate structure ( [0050] etching away the dummy gate to form a groove (not marked in FIG. 6 ) in the interlayer dielectric layer 202; and forming the gate layer 203 within the groove ); forming a sacrificial structure covering the etched gate structure ( [0054] Referring to FIG. 7, the method also includes forming a covering layer 207 over a part of the substrate ), and forming a capping layer ( Fig. 8: first dielectric layer 210 ) covering the second source-drain layer ( Fig 8: source/drain layer 206 ), the sacrificial structure ( Fig. 8 #207 ), and the spacer layer ( Fig. 8: spacer 204 ); etching the capping layer ( Fig. 11 #213 ) to obtain a first contact hole ( Fig. 11: conductive structure 211 ) reaching the sacrificial structure ( [0072] sing the first patterned layer as a mask to etch the first dielectric layer 210, the first etch stop layer 209, and the interlayer dielectric layer 202 until the surface of the source/drain layer 206 is exposed ); removing the sacrificial structure ( as shown in Fig. 11 ) at a bottom of the first contact hole ( Fig. 11 second opening 215 ) to form a gap under the first contact hole ( as shown in Fig. 11 ); and forming a first contact structure ( Fig. 12 first conductive layer 217 ) in the first contact hole and the gap ( Fig. 11 #215 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Xu with Basu, and Jung to implement etching the gate structure to reduce a vertical dimension of the gate structure; forming a sacrificial structure covering the etched gate structure, and forming a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer; etching the capping layer to obtain a first contact hole reaching the sacrificial structure; removing the sacrificial structure at a bottom of the first contact hole to form a gap under the first contact hole; and forming a first contact structure in the first contact hole and the gap because this approach can affect electrical characteristics such as threshold voltage, gate capacitance, and current drive.
Claim 16: Basu, Jung and Xu disclose the method according to claim 15 ( as discussed above).
Neither Basu nor Jung appear to disclose etching the capping layer to obtain a second contact hole reaching the second source-drain layer; and forming a second contact structure in the second contact hole.
Xu teaches etching the capping layer ( Fig. 8 #213 ) to obtain a second contact hole ( Fig. #214 ) reaching the second source-drain layer ( Fig. 11 #210 ) ; and forming a second contact structure ( Fig. 12 #216 ) in the second contact hole ( Fig. 11 #214 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Xu with Basu, and Jung to implement etching the capping layer to obtain a second contact hole reaching the second source-drain layer; and forming a second contact structure in the second contact hole because this can be used to improve electrical performance.
Claim 17: Basu, Jung and Xu disclose the method according to claim 15 ( as discussed above ).
Neither Basu nor Jung appear to disclose removing the sacrificial structure at the bottom of the first contact hole comprises: removing the sacrificial structure at the bottom of the first contact hole through wet etching.
However, Xu teaches removing the sacrificial structure at the bottom of the first contact hole comprises: removing the sacrificial structure at the bottom of the first contact hole through wet etching.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Xu with Basu, and Jung to implement removing the sacrificial structure at the bottom of the first contact hole comprises: removing the sacrificial structure at the bottom of the first contact hole through wet etching because this approach can be used to provide electrical isolation.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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